- 04 2月, 2014 3 次提交
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由 Stephen Warren 提交于
The only place where the MASK_BITS_* values are used is in adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28, new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK, i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually implemented. Note that no Tegra clock register actually uses all of bits 31:28 as the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in those cases, nothing is stored in the bits above the mux field, so it's safe to pretend that the mux field extends all the way to the end of the register. As such, the U-Boot clock driver is currently a bit lazy, and doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps them all together and pretends they're all 31:28. This patch doesn't cause this issue; it was pre-existing. Hopefully, future patches will clean this up. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
The enum used to define the set of register bits used to represent a clock's input mux, MUX_BITS_*, is defined separately for each SoC at present. Move this definition to a common location to ease fixing up some issues with the definition, and the code that uses it. Signed-off-by: NTom Warren <twarren@nvidia.com> [swarren, extracted from a larger patch by Tom] Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
For Tegra20, the SKU ID actually impacts how U-Boot programs the chip, and hence we need to explicitly know about each and every SKU ID in order to operate correctly. However, for Tegra30/114, this isn't the case. Rather than forcing each new user with a different SKU to manually add their SKU ID into the code, simply accept any SKU ID. If U-Boot ever starts e.g. programming maximal CPU clocks etc., we'll need to undo this, or make the default case map to conservative defaults, but for now it's likely the path to least support cost. Reported-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 25 1月, 2014 4 次提交
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由 Masahiro Yamada 提交于
Before this commit, all arch/arm/cpu/${CPU}/config.mk except ARMv8 had the same option: $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) This commit moves it into arch/arm/config.mk. If the compiler does not support the option, it is ignored by $(call cc-option,...). So this commit gives no harm to ARMv8. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Darwin Rambo 提交于
If timer_init() is made a weak stub function, then it allows us to remove several empty timer_init functions for those boards that already have a timer initialized when u-boot starts. Architectures that use the timer framework may also remove the need for timer.c. Signed-off-by: NDarwin Rambo <drambo@broadcom.com> Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
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由 Nishanth Menon 提交于
Patch adds modification to shared omap5 abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain at OPP_NOM. Signed-off-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@ti.com>
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由 Nishanth Menon 提交于
ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support for ES1.1 IDCODE change. Signed-off-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@ti.com>
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- 24 1月, 2014 2 次提交
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由 Jassi Brar 提交于
The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>
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由 Jassi Brar 提交于
The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>
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- 21 1月, 2014 1 次提交
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由 Stephen Warren 提交于
My original intention was to have a 100ms timeout. However, the timer operations used return values in ms not us, so we ended up with a 100s timeout instead. Fixing this exposes that some operations need longer to operate than 100ms, so bump the timeout up to a whole second. Reported-by: NAndre Heider <a.heider@gmail.com> Reviewed-by: NAndre Heider <a.heider@gmail.com> Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
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- 17 1月, 2014 1 次提交
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由 Fabio Estevam 提交于
Commit 02229827 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: NOtavio Salvador <otavio@ossystems.com.br> Reported-by: NPierre Aubert <p.aubert@staubli.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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- 15 1月, 2014 1 次提交
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由 Fabio Estevam 提交于
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NStefano Babic <sbabic@denx.de>
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- 14 1月, 2014 2 次提交
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由 Andreas Bießmann 提交于
Building some arm boards with older binutils may produce errors like this: ---8<--- crt0.S: Assembler messages: crt0.S:70: Error: register expected, not '#(184)' -- `sub sp,#(184)' --->8--- Use canonical version of the subtract mnemonic to avoid those issues. Reported-by: NAlexey Smishlayev <alexey@xtech2.lv> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Albert ARIBAUD 提交于
Some targets will build fine but not boot if sections .hash and .got.plt are not present in the binary. Add them back. Also, Exynos machines require .machine_param section in SPL. Add it. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
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- 13 1月, 2014 2 次提交
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由 Marek Vasut 提交于
The OneNAND SPL used on PXA is slightly obscure. Due to the OneNAND limitation, where we have only the first 1KiB of the OneNAND available upon power-up as a memory-mapped area, from which the CPU starts executing, we place only the most essential code into this first 1KiB . This code copies the rest of the SPL into SRAM and jumps to it. This code is stored in section .text.0 . The rest of the SPL is stored in section .text.1 . When running the OBJCOPY on the SPL, it will preserve only .text section, but the .text.0 and .text.1 are stripped away from the result, thus making the SPL binary empty. The patch adds additional -j parameters to the OBJCOPY for PXA during the SPL build, which will preserve the .text.0 and .text.1 sections. Moreover, this patch also adds missing functions into the .text.0 section, since otherwise the PXA270 with 1KiB-window OneNAND won't be able to boot. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com>
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由 Christian Gmeiner 提交于
Commit 762a88cc introduces a 64-bit division without using the lldiv() function, which pulls in previously unused libgcc stuff. Signed-off-by: NMåns Rullgård <mans@mansr.com> Signed-off-by: NChristian Gmeiner <christian.gmeiner@gmail.com> Acked-by: NStefano Babic <sbabic@denx.de>
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- 10 1月, 2014 1 次提交
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Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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- 09 1月, 2014 1 次提交
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由 David Feng 提交于
Relocation code based on a patch by Scott Wood, which is: Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NDavid Feng <fenghua@phytium.com.cn>
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- 03 1月, 2014 8 次提交
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由 Sergey Alyoshin 提交于
Enable fuse supply before fuse programming and disable after. Signed-off-by: NSergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
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由 Otavio Salvador 提交于
The enable_fec_anatop_clock method should be available for all MX6 variant as it is not MX6 SoloLite specific. This moves the code out of the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC instead. Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br> Acked-by: NStefano Babic <sbabic@denx.de>
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由 Fabio Estevam 提交于
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NJason Liu <r64343@freescale.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
When changing LDO voltages we need to wait for the required amount of time for the voltage to settle. Also, as the timer is still not available when arch_cpu_init() is called, we need to call it later at board_postclk_init() phase. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Introduce set_ldo_voltage() so that all three LDO regulators can be configured. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V. Add a 25 mV margin and set it to 1.175V. This also matches the VDDSOC voltages for 792MHz operation that the kernel configures: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00: 00: 64 cycles of 24MHz clock; 01: 128 cycles of 24MHz clock; 02: 256 cycles of 24MHz clock; 03: 512 cycles of 24MHz clock; Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NJason Liu <r64343@freescale.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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- 30 12月, 2013 3 次提交
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由 Rajeshwari Birje 提交于
Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Rajeshwari Birje 提交于
This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Rajeshwari Birje 提交于
This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 19 12月, 2013 8 次提交
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由 Lokesh Vutla 提交于
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: NTom Rini <trini@ti.com>
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由 Lokesh Vutla 提交于
Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Selecting the Master osc clk as Timer2 clock source. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Alban Bedel 提交于
Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de> Reviewed-by: NJulian Scheel <julian.scheel@avionic-design.de> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Thierry Reding 提交于
PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Jimmy Zhang 提交于
The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly. Signed-off-by: NJimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 18 12月, 2013 3 次提交
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由 Sergei Ianovich 提交于
Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS. If SDRAM is not reset, it causes memory bus congestion and the device hangs. We put SDRAM in selfresh mode before watchdog reset, removing potential freezes. Signed-off-by: NSergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
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由 Frank Li 提交于
ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: NHuang yongcai <b20788@freescale.com> Signed-off-by: NFrank Li <Frank.Li@freescale.com>
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由 Fabio Estevam 提交于
According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: NRabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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