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  1. 19 2月, 2019 1 次提交
  3. 03 12月, 2018 1 次提交
    • H
      efi_loader: PSCI reset and shutdown · 81ea0083
      由 Heinrich Schuchardt 提交于 
      When an operating system started via bootefi tries to reset or power off
this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system
the actual reset relies on PSCI. Depending on whether the PSCI firmware
resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC
or an SMC command has to be issued.

The current implementation always uses SMC. This results in crashes on
systems where the PSCI firmware is implemented in the hypervisor, e.g.
qemu-arm64_defconfig.

The logic to decide which call is needed based on the device tree is
already implemented in the PSCI firmware driver. During the EFI runtime
the device driver model is not available. But we can minimize code
duplication by merging the EFI runtime reset and poweroff code with
the PSCI firmware driver.

As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff
and reset_misc routines let's move them into the same code module.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NSumit Garg <sumit.garg@linaro.org>
Tested-by: NSumit Garg <sumit.garg@linaro.org>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      81ea0083
  5. 17 11月, 2018 1 次提交
  7. 04 8月, 2018 1 次提交
    • A
      armv8: make SPL exception vectors optional · 1416e2d2
      由 Andre Przywara 提交于 
      Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.

On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.

Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      1416e2d2
  9. 30 7月, 2018 1 次提交
  11. 12 6月, 2018 1 次提交
  13. 16 1月, 2018 2 次提交
  15. 11 9月, 2017 2 次提交
  17. 07 7月, 2017 1 次提交
  19. 24 5月, 2017 1 次提交
  21. 29 1月, 2017 1 次提交
    • M
      arm64: spin-table: add more information in Kconfig help · 65f32196
      由 Masahiro Yamada 提交于 
      This feature seems to be sometimes misunderstood.  The intention is:

[1] Bring the slaves into the U-Boot proper image, not SPL (unless
    you have a special reason to do otherwise).

[2] The operation must be done in a board (SoC) specific manner
    since how to wake the slaves from the Boot ROM is SoC specific.

[3] The slaves must enter U-Boot proper after U-Boot relocates
    itself because the "cpu-release-addr" property points to the
    relocated memory area.

[2] is already explained in the help.  We can make [1] even clearer
by mentioning "U-Boot proper" instead of "U-Boot".  [3] is missing,
so I am adding it to the list.  Instead, "before the master CPU
jumps to the kernel" is a matter of course, so removed.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      65f32196
  23. 19 1月, 2017 3 次提交
  25. 16 12月, 2016 2 次提交
  27. 17 11月, 2016 1 次提交
  29. 19 10月, 2016 1 次提交
    • A
      arm: Provide common PSCI based reset handler · 8069821f
      由 Alexander Graf 提交于 
      Most armv8 systems have PSCI support enabled in EL3, either through
ARM Trusted Firmware or other firmware.

On these systems, we do not need to implement system reset manually,
but can instead rely on higher level firmware to deal with it.

The exclude list seems excessive right now, but NXP is working on
providing an in-tree PSCI implementation, so that all NXP systems
can eventually use PSCI as well.
Signed-off-by: NAlexander Graf <agraf@suse.de>
[agraf: fix meson]
Reviewed-by: NSimon Glass <sjg@chromium.org>
      8069821f
  31. 12 8月, 2016 1 次提交
  33. 15 7月, 2016 1 次提交
    • M
      arm64: add better and more generic spin-table support · 6b6024ea
      由 Masahiro Yamada 提交于 
      There are two enable methods supported by ARM64 Linux; psci and
spin-table.  The latter is simpler and helpful for quick SoC bring
up.  My main motivation for this patch is to improve the spin-table
support, which allows us to boot an ARMv8 system without the ARM
Trusted Firmware.

Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S
and the spin-table is supported in a really ad-hoc way, and I see
some problems:

  - We must hard-code CPU_RELEASE_ADDR so that it matches the
    "cpu-release-addr" property in the DT that comes from the
    kernel tree.

  - The Documentation/arm64/booting.txt in Linux requires that
    the release address must be zero-initialized, but it is not
    cared by the common code in U-Boot.  We must do it in a board
    function.

  - There is no systematic way to protect the spin-table code from
    the kernel.  We are supposed to do it in a board specific manner,
    but it is difficult to predict where the spin-table code will be
    located after the relocation.  So, it also makes difficult to
    hard-code /memreserve/ in the DT of the kernel.

So, here is a patch to solve those problems; the DT is run-time
modified to reserve the spin-table code (+ cpu-release-addr).
Also, the "cpu-release-addr" property is set to an appropriate
address after the relocation, which means we no longer need the
hard-coded CPU_RELEASE_ADDR.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      6b6024ea
  35. 06 2月, 2016 1 次提交
  37. 09 3月, 2015 1 次提交
    • L
      armv8/vexpress64: make multientry conditional · 23b5877c
      由 Linus Walleij 提交于 
      While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.

The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.

Make the single entry default and add a special
ARMV8_MULTIENTRY KConfig option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.

This makes the Juno platform start U-Boot properly.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      23b5877c
  39. 13 11月, 2014 1 次提交
  41. 17 9月, 2014 1 次提交