- 05 9月, 2014 1 次提交
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由 Ajay Kumar 提交于
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: NAjay Kumar <ajaykumar.rs@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 23 6月, 2014 1 次提交
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由 Akshay Saraswat 提交于
Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 13 6月, 2014 3 次提交
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由 Akshay Saraswat 提交于
Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Doug Anderson 提交于
when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Akshay Saraswat 提交于
Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: NHatim Ali <hatim.rv@samsung.com> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 30 12月, 2013 2 次提交
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由 Rajeshwari Birje 提交于
This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Rajeshwari Birje 提交于
This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 05 7月, 2013 1 次提交
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由 Rajeshwari Shinde 提交于
This patch performs the following: 1) Convert the assembly code for memory and clock initialization to C code. 2) Move the memory and clock init codes from board/samsung to arch/arm 3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code 4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5. 5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main. 6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250. TEST: Tested SD-MMC boot on SMDK5250 and Origen. Tested USB and SPI boot on SMDK5250 Compile tested for SMDKV310. Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 04 6月, 2013 1 次提交
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由 Inderpal Singh 提交于
tzpc_init is common for all exynos5 boards, hence move it to armv7/exynos so that all other boards can use it. Also update the smdk5250 Makefile and config file. Signed-off-by: NInderpal Singh <inderpal.singh@linaro.org> Acked-by: NChander Kashyap <chander.kashyap@linaro.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 01 4月, 2013 1 次提交
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由 Padmavathi Venna 提交于
MPLL is selected as the source clk of pwm by default Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 01 9月, 2012 2 次提交
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由 Rajeshwari Shinde 提交于
The patch adds the memory initialization sequence of DDR3. Signed-off-by: NHatim Ali <hatim.rv@samsung.com> Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Rajeshwari Shinde 提交于
Add new clock values for Exynos5250 Rev 1.0 Signed-off-by: NHatim Ali <hatim.rv@samsung.com> Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 12 2月, 2012 1 次提交
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由 Chander Kashyap 提交于
SMDK5250 board is based on Samsungs EXYNOS5250 SoC. Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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