Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This config is valid for two devices:
- Odroid X2,
- Odroid U3.
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch introduces code clean-up for exynos boot mode check.
It includes:
- removal of typedef: boot_mode
- move the boot mode enum to arch-exynos/power.h
- add bootmode for sequence: eMMC 4.4 ch4 / SD ch2
- add new function: get_boot_mode() for OM[5:1] pin check
- update spl boot code
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>

Changes v5:
- exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2)

Changes v6:
- none

changes v7:
- change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This change fixes the bad gpio configuration for the exynos dwmmc.
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Cc: Beomho Seo <beomho.seo@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Becuase the board select menu in arch/arm/Kconfig is too big,
move the Exynos board select menu to exynos/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="exynos").
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: NMinkyu Kang <mk7.kang@samsung.com>

Macros defined in exynos5_setup.h specific to SMDK5420
are required for Peach-Pit too. Hence, replacing
CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these
macros for all the boards based on Exynos5420.
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Sometimes Read DQ and DQS are not in phase. Since, this
phase shift differs from board to board, we need to
calibrate it at DRAM init phase, that's read DQ calibration.
This patch adds SW Read DQ calibration routine to compensate
this skew.
Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

when CLKM is running.  If we stop CLKM when sampling it the glitches
all go away, so we'll do that as per Samsung suggestion.

We also check the "is it locked" bits of PHY_CON13 and loop until they
show the the value sampled actually represents a locked value.  It
doesn't appear that the glitching and "is it locked" are related, but
it seems wise to wait until the PHY tells us the value is good before
we use it.  In practice we will not loop more than a couple times (and
usually won't loop at all).
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch intends to remove all code which enables hardware read
leveling. All characterization environments may not cope up with
h/w read leveling enabled, so we must disable this.
Also, disabling h/w read leveling improves the MIF LVcc value
(LVcc value is the value at which DDR will fail to work properly).
Improving LVcc means we have enough voltage margin for MIF.
When h/w leveling is enabled, we have almost zero volatge margin.
Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Passing fewer arguments is better and mem_iv_size is never
used. Let's keep only one argument and make it cleaner.
Signed-off-by: NHatim Ali <hatim.rv@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This reverts commit eb0dd998.

Signed-off-by: NVasili Galka <vvv444@gmail.com>

Setting ps_hold ought to be one of the first things we do when we
first boot up. If we wait until the main u-boot runs we won't set it
in time and the PMIC may power us back off.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

There is quite a tight deadline in enabling PSHOLD, less than a second.
In some cases (e.g. with USB download), U-Boot takes longer than that
to load, so the board powers off before U-Boot starts.

Add a call in SPL to enable PSHOLD.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

exynos4x12_set_mmc_clk function have been removed.
Because, exynos4x12_clock and exynos4_clock return same div_fsys* value.
Signed-off-by: NBeomho Seo <beomho.seo@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NPiotr Wilczek <p.wilczek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

For use dwmmc controller at exynos4, add SDMMC4 gpio configuration.
Signed-off-by: NBeomho Seo <beomho.seo@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NPiotr Wilczek <p.wilczek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
  To have consistent 0..n-1 GPIO numbering the banks are divided
  into different parts where ever they have holes in them.

* Rename GPIO definitions from GPIO_... to S5P_GPIO_...
  These changes were done to enable cmd_gpio for EXYNOS and
  cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
  getting a error during compilation.

* Adds support for name to gpio conversion in s5p_gpio to enable
  gpio command EXYNOS SoCs. Function has been added to asm/gpio.h
  to decode the input gpio name to gpio number.
  Example: SMDK5420 # gpio set gpa00
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Squash these warnings in pinmux.c found with GCC 4.8:

/arch/arm/cpu/armv7/exynos/pinmux.c: In function 'exynos_pinmux_config':
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'count' may be used uninitialized in this function [-Wmaybe-uninitialized]
  for (i = start; i < start + count; i++) {
                            ^
/arch/arm/cpu/armv7/exynos/pinmux.c:663:16: note: 'count' was declared here
  int i, start, count;
                ^
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'start' may be used uninitialized in this function [-Wmaybe-uninitialized]
  for (i = start; i < start + count; i++) {
                            ^
/arch/arm/cpu/armv7/exynos/pinmux.c:663:9: note: 'start' was declared here
  int i, start, count;
         ^
/arch/arm/cpu/armv7/exynos/pinmux.c:689:19: warning: 'bank' may be used uninitialized in this function [-Wmaybe-uninitialized]
   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
                   ^
/arch/arm/cpu/armv7/exynos/pinmux.c:662:24: note: 'bank' was declared here
  struct s5p_gpio_bank *bank;
                        ^
/arch/arm/cpu/armv7/exynos/pinmux.c: In function 'exynos_pinmux_config':
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'count' may be used uninitialized in this function [-Wmaybe-uninitialized]
  for (i = start; i < start + count; i++) {
                            ^
/arch/arm/cpu/armv7/exynos/pinmux.c:663:16: note: 'count' was declared here
  int i, start, count;
                ^
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'start' may be used uninitialized in this function [-Wmaybe-uninitialized]
  for (i = start; i < start + count; i++) {
                            ^
/arch/arm/cpu/armv7/exynos/pinmux.c:663:9: note: 'start' was declared here
  int i, start, count;
         ^
/arch/arm/cpu/armv7/exynos/pinmux.c:689:19: warning: 'bank' may be used uninitialized in this function [-Wmaybe-uninitialized]
   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
                   ^
/arch/arm/cpu/armv7/exynos/pinmux.c:662:24: note: 'bank' was declared here
  struct s5p_gpio_bank *bank;
                        ^

Note that the warning is bogus, the function can never be called with invalid
'peripheral' argument. GCC just cannot analyze this.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch adds api to decode peripheral id based on interrupt number.
Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Use setbits/clrbits macro instead of readl/writel function.
(Suggested by Wolfgang)
Signed-off-by: NInha Song <ideal.song@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch fixed that cfg value is set to wrong value.
Because it didn't read the related register.
Signed-off-by: NInha Song <ideal.song@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Because of the list of peripherals is not sequential,
such a routine does not check for valid correctly.
Error check will be done when call the exynos_pinmux_config function.
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Acked-by: NRajeshwari Shinde <rajeshwari.s@samsung.com>

The value of PERIPH_ID_COUNT was wrong, and unnecessary.
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Some targets will build fine but not boot if sections .hash and
.got.plt are not present in the binary. Add them back.

Also, Exynos machines require .machine_param section in SPL.
Add it.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>

Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch fix following errors and warnings

spl_boot.c: In function 'exynos_spi_copy':
spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function)
spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in
spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function)
spl_boot.c: In function 'copy_uboot_to_ram':
spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable]
spl_boot.c: At top level:
spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function]
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

This patch implements a custom spi_copy funtion to copy u-boot from SF
to RAM. This is faster then iROM spi_copy funtion as this runs spi at
50Mhz and also in WORD mode of operation.

Changed a printf in pinmux.c to debug just to avoid the compilation
error in SPL.
Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: NTom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Fix the set_mmc_clk() for exnos4x12.
If board is exynos4x12, mmc clock should be set to wrong value.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Adding methods to turn on/off power to USB3.0 type PHY
as and when required by the controller.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>

This patch makes the necessary changes for making use of
I2S0 channel instead of I2S1 channel on smdk board. This
changes are done to maintain the uniformity to use I2S0 channel.
Signed-off-by: NDani Krishna Mohan <krishna.md@samsung.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

Provide proper setting for the APLL fout frequency calculation for
Exynos4 based targets (especially Exynos4210 - Trats board).
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: NMinkyu Kang <mk7.kang@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com>

This patch performs the following:

1) Convert the assembly code for memory and clock initialization to C code.
2) Move the memory and clock init codes from board/samsung to arch/arm
3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted
   the common lowlevel_init from assembly to C-code
4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5.
5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already
   done in _main.
6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250.

TEST: Tested SD-MMC boot on SMDK5250 and Origen.
      Tested USB and SPI boot on SMDK5250
      Compile tested for SMDKV310.
Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch configures the gpio values for UART
on Origen and SMDKV310 using pinmux
Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>