- 15 1月, 2015 1 次提交
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由 Michal Simek 提交于
Trivial fix. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 25 10月, 2011 1 次提交
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由 Anton staaf 提交于
This macro is used to allocate cache line size aligned stack buffers for use with DMA hardware. Signed-off-by: NAnton Staaf <robotboy@chromium.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Aneesh V <aneesh@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
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- 04 9月, 2011 1 次提交
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由 Aneesh V 提交于
c2dd0d45 added dcache_enable() to board_init_r(). This enables d-cache for all ARM boards. As a result some of the arm boards that are not cache-ready are broken. Revert this change and allow platform code to take the decision on d-cache enabling. Also add some documentation for cache usage in ARM. Signed-off-by: NAneesh V <aneesh@ti.com>
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