For systems which has both sdhci controllers enable it is worth to export
bootseq number for variables. Then the variable can be used in custom
scripts to tune logic for OS.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is no need to define the same macros in drivers.
All macros have been added by commit 17a42abb ("mmc: Define timing
macro's").
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Enable this driver to get build and probe for our platform.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com>

This reverts commit 1231184c.

While the change is fine in theory, a number of tests need to be updated
to match.
Signed-off-by: NTom Rini <trini@konsulko.com>

- e1000, ftgmac100: Add support for getting the MAC
- General networking improvements
- dwc_eth_qos, ks8851 fixes

dev_read_alias_seq() used uc_drv->name compared to alias
stem string, Ethernet's alias stem uses "ethernet", which
does not match the eth-uclass driver name "eth", can not
get the correct index of ethernet alias namer. So it seems
change uclass driver name to match the alias stem is a more
reasonable way.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this lets Tegra
use the generic cache flush / invalidate operations.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NPatrice Chotard <patrice.chotard@foss.st.com>

A sporadic condition occurs when the "bad packet" error is triggered
repeatedly, which results in "bad packet" messages scrolling on the
console during transfer. To avoid triggering this, reset the internal
RXFC count on the first occurance of the "bad packet", which forces
the code to re-read the RX packet count from the MAC, and prevents
any additional "bad packet" messages if there are no more packets in
the MAC. Also print better debug information if this condition occurs.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Tom Rini <trini@konsulko.com>

When calling srand_mac we use a weak seed dependent on the
mac address. If present, use a RNG device instead to incerase entropy.
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>
Reviewed-by: NTorsten Duwe <duwe@suse.de>

When calculating a random UUID we use a weak seed.
Use a RNG device if present to increase entropy.
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>
Reviewed-by: NTorsten Duwe <duwe@suse.de>

Read and retain MAC address across flash and QEMU support.
Signed-off-by: NHongwei Zhang <hongweiz@ami.com>

Fix typo which would cause a build error.

Fixes: 3eaac630 ("net: introduce packet capture support")
Signed-off-by: NJorge Ramirez-Ortiz <jorge@foundries.io>

When the tftp server did not send any OACK, the tftp_next_ack variable
was not set to the correct value . As the server was transmitting
blocks we generated a lot of 'Received unexpected block: $n, expected
$n+1' error messages. Depending on the timeout setting the transfer
could still complete though.
Signed-off-by: NHarm Berntsen <harm.berntsen@nedap.com>
CC: Ramon Fried <rfried.dev@gmail.com>
Reviewed-By: NRamon Fried <rfried.dev@gmail.com>

While doing DHCP the interface IP is set to 0.0.0.0. This causes the
check in net.c on dst_ip to be effectively skipped, and all IP datagrams
are accepted up the IP stack. In the case of an ICMP_ECHO_REQUEST for the
matching MAC address (regardless of destination IP), the result is that
an ICMP_ECHO_REPLY is sent. The source address of the ICMP_ECHO_REPLY is
0.0.0.0, which is an illegal source address.

This can happen in common practice with the following sequence:
DHCP (U-Boot or OS) acquires IP address 10.0.0.1
System reboots
U-Boot starts DHCP and send DHCP DISCOVER
DHCP server decides to OFFER 10.0.0.1 again
  (perhaps because of existing lease or manual configuration)
DHCP server tries to PING 10.0.0.1 to see if anyone is squatting on it
DHCP server still has our MAC address in its ARP table for 10.0.0.1
U-Boot receives PING, and responds with an illegal source address
This may further result in a the DHCP server seeing the response as
  confirmation that someone is squatting on 10.0.0.1, and picking a
  new IP address from the pool to try again
Signed-off-by: NDavid Rivshin <drivshin@allworx.com>

Implement programming MAC address to the hardware also for device model
configuration.

Fixes: b565b18a ("board: ge: bx50v3: Enable DM for PCI and ethernet")
Signed-off-by: NIan Ray <ian.ray@ge.com>
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.com>

Running the start() handler twice without a stop() inbetween completely
breaks communication for some ethernet drivers like fec_mxc.

eth_halt() is called before each eth_init(). Due to the switch to
eth_is_active() in commit 68acb51f ("net: Only call halt on a driver
that has been init'ed"), this is not sufficient anymore when netconsole
is active: eth_init_state_only()/eth_halt_state_only() manipulate the
state check that is performed by eth_is_active() without actually
calling into the driver.

The issue can be triggered by starting a network operation (e.g. ping or
tftp) while netconsole is active.

Add an additional "running" flag that reflects the actual state of the
driver and use it to ensure that eth_halt() actually stops the device as
it is supposed to.

Fixes: 68acb51f ("net: Only call halt on a driver that has been init'ed")
Signed-off-by: NMatthias Schiffer <matthias.schiffer@ew.tq-group.com>

- Assorted MediaTek, AST2x00 updates
- Assorted driver fixes for various platforms
- Keymile platform updates
- Add pwm command, mp5416 pmic driver

The input system clock for mt7622 timer is 10MHz and can be retrieved
through the clk driver.
Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>

The timer being used by this driver may have already been used by first
stage bootloader (e.g. ATF/preloader), and it's settings may differ from
what this driver is going to use.

This may cause issues, such as inaccurate timer frequency due to
incorrect clock divider.

This patch adds the initialization code to avoid them.
Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>

If no GPIO controller is found, the return value should not depend on a
random value on the stack. Initialize variable ret.

The problem was indicated by cppcheck.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NChunfeng Yun <chunfeng.yun@mediatek.com>

drivers/mtd/mw_eeprom.c contains code that never worked. mw_eeprom_write()
and mw_eeprom_read() have incorrect loop conditions:

	while (len <= 2) {

CONFIG_MW_EEPROM is not set anywhere. So let's simply drop the module.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Avoid calling free(addr) twice if the device for ucode is not found.

The problem was indicated by cppcheck.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Freeing a buffer before calling hang() is superfluous. Removing the call
reduces the SPL size.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Update branch and version information of ATF and DDR firmware files to
point to latest releases provided by NXP.

This is especially critical for imx8mp evk, as the ATF support for that
SoC is only available in latest releases.

Align all SoCs from imx8m family to use identical revisions of ATF and
DDR firmware.
Signed-off-by: NAndrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

Calling calloc() for 0 members does not make any sense.
Setting ch_priv->busy_desc = NULL for ch_priv->desc_cnt > 0 is equally
unreasonable.

The current code will lead to a NULL dereference in bcm6348_iudma_enable().

The assignments for ch_priv->busy_desc are obviously swapped.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Add the command "pwm" for controlling the pwm channels. This
command provides pwm invert/config/enable/disable functionalities
via PWM uclass drivers
Signed-off-by: NPragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This adds basic register access and child regulator binding
for the Monolithic MP5416 Power Management IC which integrates
four DC/DC switching converters and five LDO regulators.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Add the default configuration for the AST2600 EVB.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

Add low level platform initialization for the AST2600 SoC.
The 2-stage booting with U-Boot SPL are leveraged to support
different booting mode.

However, currently the patch supports only the booting from
memory-mapped SPI flash.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

AST2600 is the 7th generation of Aspeed SoC designated for
Interated Remote Management Processor.

AST2600 has significant performance improvement by integrating
1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the
controllers are also improved with more features and better
performance than preceding AST24xx/AST25xx.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

Add controller reset support through the
System Control Unit (SCU) of AST2600 SoC.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

AST2600 has 8 watchdog timers including 8 sets of
32-bit decrement counters, based on 1MHz clock.

A 64-bit reset mask is also supported to specify
which controllers should be reset by the WDT reset.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600.
The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb),
512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.
Signed-off-by: NDylan Hung <dylan_hung@aspeedtech.com>
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

This patch adds the clock control driver
for the AST2600 SoC.
Signed-off-by: NRyan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>

Set environment for Nand flash (U-boot 2020.04):
- add nand flash in the device tree
- add new default configuration file for G3 using parallel Nand
- set nand parameters in presidio_asic.h
Signed-off-by: NKate Liu <kate.liu@cortina-access.com>
Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add Cortina Access parallel Nand support for CAxxxx SOCs
Signed-off-by: NKate Liu <kate.liu@cortina-access.com>
Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
CC: Scott Wood <oss@buserror.net>
Reviewed-by: NTom Rini <trini@konsulko.com>

Disable some unneeded config options and adapt the ident string.

CC: Stefan Roese <sr@denx.de>
Signed-off-by: NHolger Brunck <holger.brunck@hitachi-powergrids.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Our kirkwood device embeds a USB host controller that is now used
on some boards. This enables the support of USB and the corresponding
driver.
Signed-off-by: NHolger Brunck <holger.brunck@hitachi-powergrids.com>
CC: Stefan Roese <sr@denx.de>
Reviewed-by: NStefan Roese <sr@denx.de>

The driver only needs to retrieve the pin for the ACPI info. The driver
itself works without depending on GPIO.
Signed-off-by: NHarm Berntsen <harm.berntsen@nedap.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The pci_mmc.c driver can generate ACPI info and therefore includes
asm/acpi_table.h by proxy. This file does not exist for the ARM
architecture and thus code compilation failed when using this
driver on ARM.
Signed-off-by: NHarm Berntsen <harm.berntsen@nedap.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>