Merge branch '2021-01-18-assorted-platform-updates'

- Assorted MediaTek, AST2x00 updates
- Assorted driver fixes for various platforms
- Keymile platform updates
- Add pwm command, mp5416 pmic driver

MAINTAINERS

@@ -198,6 +198,9 @@ F:	drivers/mmc/ca_dw_mmc.c
 F:	drivers/spi/ca_sflash.c
 F:	drivers/i2c/i2c-cortina.c
 F:	drivers/i2c/i2c-cortina.h
+F:	drivers/mtd/nand/raw/cortina_nand.c
+F:	drivers/mtd/nand/raw/cortina_nand.h
+F:	configs/cortina_presidio-asic-pnand_defconfig
 
 ARM/CZ.NIC TURRIS MOX SUPPORT
 M:	Marek Behun <marek.behun@nic.cz>

README

@@ -3153,6 +3153,7 @@ i2c	- I2C sub-system
 sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
+pwm	- control pwm channels
 setenv	- set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection

arch/arm/dts/Makefile

@@ -960,6 +960,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \
 dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
 
 dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
+dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
 
 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 

arch/arm/dts/ast2600-evb.dts

+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+#include "ast2600-u-boot.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+	};
+
+	aliases {
+		mmc0 = &emmc_slot0;
+		mmc1 = &sdhci_slot0;
+		mmc2 = &sdhci_slot1;
+		spi0 = &fmc;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		ethernet0 = &mac0;
+		ethernet1 = &mac1;
+		ethernet2 = &mac2;
+		ethernet3 = &mac3;
+	};
+
+	cpus {
+		cpu@0 {
+			clock-frequency = <800000000>;
+		};
+		cpu@1 {
+			clock-frequency = <800000000>;
+		};
+	};
+};
+
+&uart5 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&sdrammc {
+	clock-frequency = <400000000>;
+};
+
+&wdt1 {
+	status = "okay";
+};
+
+&fmc {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fmcquad_default>;
+
+	flash@0 {
+		compatible = "spi-flash", "sst,w25q256";
+		status = "okay";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+
+	flash@1 {
+		compatible = "spi-flash", "sst,w25q256";
+		status = "okay";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+
+	flash@2 {
+		compatible = "spi-flash", "sst,w25q256";
+		status = "okay";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&spi1 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
+			&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
+			&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
+
+	flash@0 {
+		compatible = "spi-flash", "sst,w25q256";
+		status = "okay";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&spi2 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
+			&pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
+
+	flash@0 {
+		compatible = "spi-flash", "sst,w25q256";
+		status = "okay";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+	timing-phase = <0x700ff>;
+};
+
+&emmc_slot0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_emmc_default>;
+	sdhci-drive-type = <1>;
+};
+
+&i2c4 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c5_default>;
+};
+
+&i2c5 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c6_default>;
+};
+
+&i2c6 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c7_default>;
+};
+
+&i2c7 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c8_default>;
+};
+
+&i2c8 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c9_default>;
+};
+
+&scu {
+	mac0-clk-delay = <0x1d 0x1c
+			  0x10 0x17
+			  0x10 0x17>;
+	mac1-clk-delay = <0x1d 0x10
+			  0x10 0x10
+			  0x10 0x10>;
+	mac2-clk-delay = <0x0a 0x04
+			  0x08 0x04
+			  0x08 0x04>;
+	mac3-clk-delay = <0x0a 0x04
+			  0x08 0x04
+			  0x08 0x04>;
+};

arch/arm/dts/ast2600-u-boot.dtsi

+// SPDX-License-Identifier: GPL-2.0+
+#include <dt-bindings/clock/ast2600-clock.h>
+#include <dt-bindings/reset/ast2600-reset.h>
+
+#include "ast2600.dtsi"
+
+/ {
+	scu: clock-controller@1e6e2000 {
+		compatible = "aspeed,ast2600-scu";
+		reg = <0x1e6e2000 0x1000>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/
+	};
+
+	rst: reset-controller {
+		u-boot,dm-pre-reloc;
+		compatible = "aspeed,ast2600-reset";
+		aspeed,wdt = <&wdt1>;
+		#reset-cells = <1>;
+	};
+
+	sdrammc: sdrammc@1e6e0000 {
+		u-boot,dm-pre-reloc;
+		compatible = "aspeed,ast2600-sdrammc";
+		reg = <0x1e6e0000 0x100
+			0x1e6e0100 0x300
+			0x1e6e0400 0x200 >;
+		#reset-cells = <1>;
+		clocks = <&scu ASPEED_CLK_MPLL>;
+		resets = <&rst ASPEED_RESET_SDRAM>;
+	};
+
+	ahb {
+		u-boot,dm-pre-reloc;
+
+		apb {
+			u-boot,dm-pre-reloc;
+		};
+
+	};
+};
+

arch/arm/dts/ca-presidio-engboard.dts

@@ -52,6 +52,20 @@
 		clock-frequency = <400000>;
 	};
 
+	nand: nand-controller@f4324000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "cortina,ca-nand";
+		reg = <0 0xf4324000 0x3b0>, /* NAND controller */
+		      <0 0xf7001000 0xb4>, /* DMA_GLOBAL */
+		      <0 0xf7001a00 0x80>; /* DMA channel0 for FLASH */
+		status = "okay";
+		nand-ecc-mode = "hw";
+		nand-ecc-strength = <16>;
+		nand-ecc-step-size = <1024>;    /* Must be 1024 */
+		nand_flash_base_addr = <0xe0000000>;
+	};
+
 	sflash: sflash-controller@f4324000 {
 		#address-cells = <2>;
 		#size-cells = <1>;

arch/arm/dts/mt7622.dtsi

@@ -71,16 +71,10 @@
 		compatible = "mediatek,timer";
 		reg = <0x10004000 0x80>;
 		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&system_clk>;
+		clocks = <&infracfg CLK_INFRA_APXGPT_PD>;
 		clock-names = "system-clk";
 	};
 
-	system_clk: dummy13m {
-		compatible = "fixed-clock";
-		clock-frequency = <13000000>;
-		#clock-cells = <0>;
-	};
-
 	infracfg: infracfg@10000000 {
 		compatible = "mediatek,mt7622-infracfg",
 			     "syscon";

arch/arm/dts/mt8516-pumpkin.dts

@@ -108,3 +108,13 @@
 &watchdog {
 	status = "okay";
 };
+
+&usb0 {
+	status = "okay";
+	dr_mode = "peripheral";
+
+	usb_con_c: connector {
+		compatible = "usb-c-connector";
+		label = "USB-C";
+	};
+};

arch/arm/dts/mt8516.dtsi

@@ -123,6 +123,20 @@
 		status = "disabled";
 	};
 
+	usb0: usb@11100000 {
+		compatible = "mediatek,mt8516-musb",
+			     "mediatek,mt8518-musb";
+		reg = <0x11100000 0x1000>;
+		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "mc";
+		clocks = <&topckgen CLK_TOP_USB_PHY48M>,
+			 <&topckgen_cg CLK_TOP_USBIF>,
+			 <&topckgen_cg CLK_TOP_USB>,
+			 <&topckgen_cg CLK_TOP_USB_1P>;
+		clock-names = "usbpll", "usbmcu", "usb", "icusb";
+		status = "disabled";
+	};
+
 	uart0: serial@11005000 {
 		compatible = "mediatek,hsuart";
 		reg = <0x11005000 0x1000>;

arch/arm/include/asm/arch-aspeed/boot0.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+
+#ifndef _ASM_ARCH_BOOT0_H
+#define _ASM_ARCH_BOOT0_H
+
+_start:
+	ARM_VECTORS
+
+	.word	0x0	/* key location */
+	.word	0x0	/* start address of image */
+	.word	0xfc00  /* maximum image size: 63KB */
+	.word	0x0	/* signature address */
+	.word	0x0	/* header revision ID low */
+	.word	0x0	/* header revision ID high */
+	.word	0x0	/* reserved */
+	.word	0x0	/* checksum */
+	.word	0x0	/* BL2 secure header */
+	.word	0x0	/* public key or digest offset for BL2 */
+
+#endif

arch/arm/include/asm/arch-aspeed/platform.h

@@ -13,6 +13,11 @@
 #define ASPEED_DRAM_BASE	0x80000000
 #define ASPEED_SRAM_BASE	0x1e720000
 #define ASPEED_SRAM_SIZE	0x9000
+#elif defined(CONFIG_ASPEED_AST2600)
+#define ASPEED_MAC_COUNT	4
+#define ASPEED_DRAM_BASE	0x80000000
+#define ASPEED_SRAM_BASE	0x10000000
+#define ASPEED_SRAM_SIZE	0x10000
 #else
 #err "Unrecognized Aspeed platform."
 #endif

arch/arm/include/asm/arch-aspeed/scu_ast2600.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef _ASM_ARCH_SCU_AST2600_H
+#define _ASM_ARCH_SCU_AST2600_H
+
+#define SCU_UNLOCK_KEY			0x1688a8a8
+
+#define SCU_CLKGATE1_EMMC			BIT(27)
+#define SCU_CLKGATE1_MAC2			BIT(21)
+#define SCU_CLKGATE1_MAC1			BIT(20)
+#define SCU_CLKGATE1_USB_HUB		BIT(14)
+#define SCU_CLKGATE1_USB_HOST2		BIT(7)
+
+#define SCU_CLKGATE2_FSI			BIT(30)
+#define SCU_CLKGATE2_MAC4			BIT(21)
+#define SCU_CLKGATE2_MAC3			BIT(20)
+#define SCU_CLKGATE2_SDIO			BIT(4)
+
+#define SCU_DRAM_HDSHK_SOC_INIT			BIT(7)
+#define SCU_DRAM_HDSHK_RDY			BIT(6)
+
+#define SCU_CLKSRC1_ECC_RSA_DIV_MASK		GENMASK(27, 26)
+#define SCU_CLKSRC1_ECC_RSA_DIV_SHIFT		26
+#define SCU_CLKSRC1_PCLK_DIV_MASK		GENMASK(25, 23)
+#define SCU_CLKSRC1_PCLK_DIV_SHIFT		23
+#define SCU_CLKSRC1_BCLK_DIV_MASK		GENMASK(22, 20)
+#define SCU_CLKSRC1_BCLK_DIV_SHIFT		20
+#define SCU_CLKSRC1_ECC_RSA			BIT(19)
+#define SCU_CLKSRC1_MAC_DIV_MASK		GENMASK(18, 16)
+#define SCU_CLKSRC1_MAC_DIV_SHIFT		16
+#define SCU_CLKSRC1_EMMC_EN			BIT(15)
+#define SCU_CLKSRC1_EMMC_DIV_MASK		GENMASK(14, 12)
+#define SCU_CLKSRC1_EMMC_DIV_SHIFT		12
+#define SCU_CLKSRC1_EMMC			BIT(11)
+
+#define SCU_CLKSRC2_RMII12			BIT(19)
+#define SCU_CLKSRC2_RMII12_DIV_MASK		GENMASK(18, 16)
+#define SCU_CLKSRC2_RMII12_DIV_SHIFT		16
+#define SCU_CLKSRC2_UART5			BIT(14)
+
+#define SCU_CLKSRC4_SDIO_EN			BIT(31)
+#define SCU_CLKSRC4_SDIO_DIV_MASK		GENMASK(30, 28)
+#define SCU_CLKSRC4_SDIO_DIV_SHIFT		28
+#define SCU_CLKSRC4_MAC_DIV_MASK		GENMASK(26, 24)
+#define SCU_CLKSRC4_MAC_DIV_SHIFT		24
+#define SCU_CLKSRC4_RMII34_DIV_MASK		GENMASK(18, 16)
+#define SCU_CLKSRC4_RMII34_DIV_SHIFT		16
+#define SCU_CLKSRC4_PCLK_DIV_MASK		GENMASK(11, 9)
+#define SCU_CLKSRC4_PCLK_DIV_SHIFT		9
+#define SCU_CLKSRC4_SDIO			BIT(8)
+#define SCU_CLKSRC4_UART6			BIT(5)
+#define SCU_CLKSRC4_UART4			BIT(3)
+#define SCU_CLKSRC4_UART3			BIT(2)
+#define SCU_CLKSRC4_UART2			BIT(1)
+#define SCU_CLKSRC4_UART1			BIT(0)
+
+#define SCU_CLKSRC5_UART13			BIT(12)
+#define SCU_CLKSRC5_UART12			BIT(11)
+#define SCU_CLKSRC5_UART11			BIT(10)
+#define SCU_CLKSRC5_UART10			BIT(9)
+#define SCU_CLKSRC5_UART9			BIT(8)
+#define SCU_CLKSRC5_UART8			BIT(7)
+#define SCU_CLKSRC5_UART7			BIT(6)
+#define SCU_CLKSRC5_HUXCLK_MASK			GENMASK(5, 3)
+#define SCU_CLKSRC5_HUXCLK_SHIFT		3
+#define SCU_CLKSRC5_UXCLK_MASK			GENMASK(2, 0)
+#define SCU_CLKSRC5_UXCLK_SHIFT			0
+
+#define SCU_PINCTRL1_EMMC_MASK			GENMASK(31, 24)
+#define SCU_PINCTRL1_EMMC_SHIFT			24
+
+#define SCU_PINCTRL16_MAC4_DRIVING_MASK		GENMASK(3, 2)
+#define SCU_PINCTRL16_MAC4_DRIVING_SHIFT	2
+#define SCU_PINCTRL16_MAC3_DRIVING_MASK		GENMASK(1, 0)
+#define SCU_PINCTRL16_MAC3_DRIVING_SHIFT	0
+
+#define SCU_HWSTRAP1_CPU_AXI_CLK_RATIO		BIT(16)
+#define SCU_HWSTRAP1_VGA_MEM_MASK		GENMASK(14, 13)
+#define SCU_HWSTRAP1_VGA_MEM_SHIFT		13
+#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK	GENMASK(12, 11)
+#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT	11
+#define SCU_HWSTRAP1_CPU_FREQ_MASK		GENMASK(10, 8)
+#define SCU_HWSTRAP1_CPU_FREQ_SHIFT		8
+#define SCU_HWSTRAP1_MAC2_INTF			BIT(7)
+#define SCU_HWSTRAP1_MAC1_INTF			BIT(6)
+
+#define SCU_EFUSE_DIS_DP			BIT(17)
+#define SCU_EFUSE_DIS_VGA			BIT(14)
+#define SCU_EFUSE_DIS_PCIE_EP			BIT(13)
+#define SCU_EFUSE_DIS_USB			BIT(12)
+#define SCU_EFUSE_DIS_RVAS			BIT(10)
+#define SCU_EFUSE_DIS_VIDEO_DEC			BIT(9)
+#define SCU_EFUSE_DIS_VIDEO			BIT(8)
+#define SCU_EFUSE_DIS_PCIE_RC			BIT(7)
+#define SCU_EFUSE_DIS_CM3			BIT(6)
+#define SCU_EFUSE_DIS_CA7			BIT(5)
+
+#define SCU_PLL_RST				BIT(25)
+#define SCU_PLL_BYPASS				BIT(24)
+#define SCU_PLL_OFF				BIT(23)
+#define SCU_PLL_DIV_MASK			GENMASK(22, 19)
+#define SCU_PLL_DIV_SHIFT			19
+#define SCU_PLL_DENUM_MASK			GENMASK(18, 13)
+#define SCU_PLL_DENUM_SHIFT			13
+#define SCU_PLL_NUM_MASK			GENMASK(12, 0)
+#define SCU_PLL_NUM_SHIFT			0
+
+#define SCU_UART_CLKGEN_N_MASK			GENMASK(17, 8)
+#define SCU_UART_CLKGEN_N_SHIFT			8
+#define SCU_UART_CLKGEN_R_MASK			GENMASK(7, 0)
+#define SCU_UART_CLKGEN_R_SHIFT			0
+
+#define SCU_HUART_CLKGEN_N_MASK			GENMASK(17, 8)
+#define SCU_HUART_CLKGEN_N_SHIFT		8
+#define SCU_HUART_CLKGEN_R_MASK			GENMASK(7, 0)
+#define SCU_HUART_CLKGEN_R_SHIFT		0
+
+#define SCU_MISC_CTRL1_UART5_DIV		BIT(12)
+
+#ifndef __ASSEMBLY__
+struct ast2600_scu {
+	uint32_t prot_key1;		/* 0x000 */
+	uint32_t chip_id1;		/* 0x004 */
+	uint32_t rsv_0x08;		/* 0x008 */
+	uint32_t rsv_0x0c;		/* 0x00C */
+	uint32_t prot_key2;		/* 0x010 */
+	uint32_t chip_id2;		/* 0x014 */
+	uint32_t rsv_0x18[10];		/* 0x018 ~ 0x03C */
+	uint32_t modrst_ctrl1;		/* 0x040 */
+	uint32_t modrst_clr1;		/* 0x044 */
+	uint32_t rsv_0x48;		/* 0x048 */
+	uint32_t rsv_0x4C;		/* 0x04C */
+	uint32_t modrst_ctrl2;		/* 0x050 */
+	uint32_t modrst_clr2;		/* 0x054 */
+	uint32_t rsv_0x58;		/* 0x058 */
+	uint32_t rsv_0x5C;		/* 0x05C */
+	uint32_t extrst_sel1;		/* 0x060 */
+	uint32_t sysrst_sts1_1;		/* 0x064 */
+	uint32_t sysrst_sts1_2;		/* 0x068 */
+	uint32_t sysrst_sts1_3;		/* 0x06C */
+	uint32_t extrst_sel2;		/* 0x070 */
+	uint32_t sysrst_sts2_1;		/* 0x074 */
+	uint32_t sysrst_sts2_2;		/* 0x078 */
+	uint32_t stsrst_sts3_2;		/* 0x07C */
+	uint32_t clkgate_ctrl1;		/* 0x080 */
+	uint32_t clkgate_clr1;		/* 0x084 */
+	uint32_t rsv_0x88;		/* 0x088 */
+	uint32_t rsv_0x8C;		/* 0x08C */
+	uint32_t clkgate_ctrl2;		/* 0x090 */
+	uint32_t clkgate_clr2;		/* 0x094 */
+	uint32_t rsv_0x98[10];		/* 0x098 ~ 0x0BC */
+	uint32_t misc_ctrl1;		/* 0x0C0 */
+	uint32_t misc_ctrl2;		/* 0x0C4 */
+	uint32_t debug_ctrl1;		/* 0x0C8 */
+	uint32_t rsv_0xCC;		/* 0x0CC */
+	uint32_t misc_ctrl3;		/* 0x0D0 */
+	uint32_t misc_ctrl4;		/* 0x0D4 */
+	uint32_t debug_ctrl2;		/* 0x0D8 */
+	uint32_t rsv_0xdc[9];		/* 0x0DC ~ 0x0FC */
+	uint32_t dram_hdshk;		/* 0x100 */
+	uint32_t soc_scratch[3];	/* 0x104 ~ 0x10C */
+	uint32_t rsv_0x110[4];		/* 0x110 ~ 0x11C*/
+	uint32_t cpu_scratch_wp;	/* 0x120 */
+	uint32_t rsv_0x124[23];		/* 0x124 */
+	uint32_t smp_boot[12];		/* 0x180 */
+	uint32_t cpu_scratch[20];	/* 0x1b0 */
+	uint32_t hpll;			/* 0x200 */
+	uint32_t hpll_ext;		/* 0x204 */
+	uint32_t rsv_0x208[2];		/* 0x208 ~ 0x20C */
+	uint32_t apll;			/* 0x210 */
+	uint32_t apll_ext;		/* 0x214 */
+	uint32_t rsv_0x218[2];		/* 0x218 ~ 0x21C */
+	uint32_t mpll;			/* 0x220 */
+	uint32_t mpll_ext;		/* 0x224 */
+	uint32_t rsv_0x228[6];		/* 0x228 ~ 0x23C */
+	uint32_t epll;			/* 0x240 */
+	uint32_t epll_ext;		/* 0x244 */
+	uint32_t rsv_0x248[6];		/* 0x248 ~ 0x25C */
+	uint32_t dpll;			/* 0x260 */
+	uint32_t dpll_ext;		/* 0x264 */
+	uint32_t rsv_0x268[38];		/* 0x268 ~ 0x2FC */
+	uint32_t clksrc1;		/* 0x300 */
+	uint32_t clksrc2;		/* 0x304 */
+	uint32_t clksrc3;		/* 0x308 */
+	uint32_t rsv_0x30c;		/* 0x30C */
+	uint32_t clksrc4;		/* 0x310 */
+	uint32_t clksrc5;		/* 0x314 */
+	uint32_t rsv_0x318[2];		/* 0x318 ~ 0x31C */
+	uint32_t freq_counter_ctrl1;	/* 0x320 */
+	uint32_t freq_counter_cmp1;	/* 0x324 */
+	uint32_t rsv_0x328[2];		/* 0x328 ~ 0x32C */
+	uint32_t freq_counter_ctrl2;	/* 0x330 */
+	uint32_t freq_counter_cmp2;	/* 0x334 */
+	uint32_t uart_clkgen;		/* 0x338 */
+	uint32_t huart_clkgen;		/* 0x33C */
+	uint32_t mac12_clk_delay;	/* 0x340 */
+	uint32_t rsv_0x344;		/* 0x344 */
+	uint32_t mac12_clk_delay_100M;	/* 0x348 */
+	uint32_t mac12_clk_delay_10M;	/* 0x34C */
+	uint32_t mac34_clk_delay;	/* 0x350 */
+	uint32_t rsv_0x354;		/* 0x354 */
+	uint32_t mac34_clk_delay_100M;	/* 0x358 */
+	uint32_t mac34_clk_delay_10M;	/* 0x35C */
+	uint32_t clkduty_meas_ctrl;	/* 0x360 */
+	uint32_t clkduty1;		/* 0x364 */
+	uint32_t clkduty2;		/* 0x368 */
+	uint32_t clkduty_meas_res;	/* 0x36C */
+	uint32_t clkduty_meas_ctrl2;	/* 0x370 */
+	uint32_t clkduty3;		/* 0x374 */
+	uint32_t rsv_0x378[34];		/* 0x378 ~ 0x3FC */
+	uint32_t pinmux1;		/* 0x400 */
+	uint32_t pinmux2;		/* 0x404 */
+	uint32_t rsv_0x408;		/* 0x408 */
+	uint32_t pinmux3;		/* 0x40C */
+	uint32_t pinmux4;		/* 0x410 */
+	uint32_t pinmux5;		/* 0x414 */
+	uint32_t pinmux6;		/* 0x418 */
+	uint32_t pinmux7;		/* 0x41C */
+	uint32_t rsv_0x420[4];		/* 0x420 ~ 0x42C */
+	uint32_t pinmux8;		/* 0x430 */
+	uint32_t pinmux9;		/* 0x434 */
+	uint32_t pinmux10;		/* 0x438 */
+	uint32_t rsv_0x43c;		/* 0x43C */
+	uint32_t pinmux12;		/* 0x440 */
+	uint32_t pinmux13;		/* 0x444 */
+	uint32_t rsv_0x448[2];		/* 0x448 ~ 0x44C */
+	uint32_t pinmux14;		/* 0x450 */
+	uint32_t pinmux15;		/* 0x454 */
+	uint32_t pinmux16;		/* 0x458 */
+	uint32_t rsv_0x45c[21];		/* 0x45C ~ 0x4AC */
+	uint32_t pinmux17;		/* 0x4B0 */
+	uint32_t pinmux18;		/* 0x4B4 */
+	uint32_t pinmux19;		/* 0x4B8 */
+	uint32_t pinmux20;		/* 0x4BC */
+	uint32_t rsv_0x4c0[5];		/* 0x4C0 ~ 0x4D0 */
+	uint32_t pinmux22;		/* 0x4D4 */
+	uint32_t pinmux23;		/* 0x4D8 */
+	uint32_t rsv_0x4dc[9];		/* 0x4DC ~ 0x4FC */
+	uint32_t hwstrap1;		/* 0x500 */
+	uint32_t hwstrap_clr1;		/* 0x504 */
+	uint32_t hwstrap_prot1;		/* 0x508 */
+	uint32_t rsv_0x50c;		/* 0x50C */
+	uint32_t hwstrap2;		/* 0x510 */
+	uint32_t hwstrap_clr2;		/* 0x514 */
+	uint32_t hwstrap_prot2;		/* 0x518 */
+	uint32_t rsv_0x51c;		/* 0x51C */
+	uint32_t rng_ctrl;		/* 0x520 */
+	uint32_t rng_data;		/* 0x524 */
+	uint32_t rsv_0x528[6];		/* 0x528 ~ 0x53C */
+	uint32_t pwr_save_wakeup_en1;	/* 0x540 */
+	uint32_t pwr_save_wakeup_ctrl1;	/* 0x544 */
+	uint32_t rsv_0x548[2];		/* 0x548 */
+	uint32_t pwr_save_wakeup_en2;	/* 0x550 */
+	uint32_t pwr_save_wakeup_ctrl2;	/* 0x554 */
+	uint32_t rsv_0x558[2];		/* 0x558 */
+	uint32_t intr1_ctrl_sts;	/* 0x560 */
+	uint32_t rsv_0x564[3];		/* 0x564 */
+	uint32_t intr2_ctrl_sts;	/* 0x570 */
+	uint32_t rsv_0x574[7];		/* 0x574 ~ 0x58C */
+	uint32_t otp_ctrl;		/* 0x590 */
+	uint32_t efuse;			/* 0x594 */
+	uint32_t rsv_0x598[6];		/* 0x598 */
+	uint32_t chip_unique_id[8];	/* 0x5B0 */
+	uint32_t rsv_0x5e0[8];		/* 0x5E0 ~ 0x5FC */
+	uint32_t disgpio_in_pull_down0;	/* 0x610 */
+	uint32_t disgpio_in_pull_down1;	/* 0x614 */
+	uint32_t disgpio_in_pull_down2;	/* 0x618 */
+	uint32_t disgpio_in_pull_down3;	/* 0x61C */
+	uint32_t rsv_0x620[4];		/* 0x620 ~ 0x62C */
+	uint32_t disgpio_in_pull_down4;	/* 0x630 */
+	uint32_t disgpio_in_pull_down5;	/* 0x634 */
+	uint32_t disgpio_in_pull_down6;	/* 0x638 */
+	uint32_t rsv_0x63c[5];		/* 0x63C ~ 0x64C */
+	uint32_t sli_driving_strength;	/* 0x650 */
+	uint32_t rsv_0x654[107];	/* 0x654 ~ 0x7FC */
+	uint32_t ca7_ctrl1;		/* 0x800 */
+	uint32_t ca7_ctrl2;		/* 0x804 */
+	uint32_t ca7_ctrl3;		/* 0x808 */
+	uint32_t ca7_ctrl4;		/* 0x80C */
+	uint32_t rsv_0x810[4];		/* 0x810 ~ 0x81C */
+	uint32_t ca7_parity_chk;	/* 0x820 */
+	uint32_t ca7_parity_clr;	/* 0x824 */
+	uint32_t rsv_0x828[118];	/* 0x828 ~ 0x9FC */
+	uint32_t cm3_ctrl;		/* 0xA00 */
+	uint32_t cm3_base;		/* 0xA04 */
+	uint32_t cm3_imem_addr;		/* 0xA08 */
+	uint32_t cm3_dmem_addr;		/* 0xA0C */
+	uint32_t rsv_0xa10[12];		/* 0xA10 ~ 0xA3C */
+	uint32_t cm3_cache_area;	/* 0xA40 */
+	uint32_t cm3_cache_invd_ctrl;	/* 0xA44 */
+	uint32_t cm3_cache_func_ctrl;	/* 0xA48 */
+	uint32_t rsv_0xa4c[108];	/* 0xA4C ~ 0xBFC */
+	uint32_t pci_cfg[3];		/* 0xC00 */
+	uint32_t rsv_0xc0c[5];		/* 0xC0C ~ 0xC1C */
+	uint32_t pcie_cfg;		/* 0xC20 */
+	uint32_t mmio_decode;		/* 0xC24 */
+	uint32_t reloc_ctrl_decode[2];	/* 0xC28 */
+	uint32_t rsv_0xc30[4];		/* 0xC30 ~ 0xC3C */
+	uint32_t mbox_decode;		/* 0xC40 */
+	uint32_t shared_sram_decode[2];	/* 0xC44 */
+	uint32_t bmc_rev_id;		/* 0xC4C */
+	uint32_t rsv_0xc50[5];		/* 0xC50 ~ 0xC60 */
+	uint32_t bmc_device_id;		/* 0xC64 */
+	uint32_t rsv_0xc68[102];	/* 0xC68 ~ 0xDFC */
+	uint32_t vga_scratch1;		/* 0xE00 */
+	uint32_t vga_scratch2;		/* 0xE04 */
+	uint32_t vga_scratch3;		/* 0xE08 */
+	uint32_t vga_scratch4;		/* 0xE0C */
+	uint32_t rsv_0xe10[4];		/* 0xE10 ~ 0xE1C */
+	uint32_t vga_scratch5;		/* 0xE20 */
+	uint32_t vga_scratch6;		/* 0xE24 */
+	uint32_t vga_scratch7;		/* 0xE28 */
+	uint32_t vga_scratch8;		/* 0xE2C */
+	uint32_t rsv_0xe30[52];		/* 0xE30 ~ 0xEFC */
+	uint32_t wr_prot1;		/* 0xF00 */
+	uint32_t wr_prot2;		/* 0xF04 */
+	uint32_t wr_prot3;		/* 0xF08 */
+	uint32_t wr_prot4;		/* 0xF0C */
+	uint32_t wr_prot5;		/* 0xF10 */
+	uint32_t wr_prot6;		/* 0xF18 */
+	uint32_t wr_prot7;		/* 0xF1C */
+	uint32_t wr_prot8;		/* 0xF20 */
+	uint32_t wr_prot9;		/* 0xF24 */
+	uint32_t rsv_0xf28[2];		/* 0xF28 ~ 0xF2C */
+	uint32_t wr_prot10;		/* 0xF30 */
+	uint32_t wr_prot11;		/* 0xF34 */
+	uint32_t wr_prot12;		/* 0xF38 */
+	uint32_t wr_prot13;		/* 0xF3C */
+	uint32_t wr_prot14;		/* 0xF40 */
+	uint32_t rsv_0xf44;		/* 0xF44 */
+	uint32_t wr_prot15;		/* 0xF48 */
+	uint32_t rsv_0xf4c[5];		/* 0xF4C ~ 0xF5C */
+	uint32_t wr_prot16;		/* 0xF60 */
+};
+#endif
+#endif

arch/arm/include/asm/arch-aspeed/sdram_ast2600.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef _ASM_ARCH_SDRAM_AST2600_H
+#define _ASM_ARCH_SDRAM_AST2600_H
+
+/* keys for unlocking HW */
+#define SDRAM_UNLOCK_KEY		0xFC600309
+#define SDRAM_VIDEO_UNLOCK_KEY		0x00440003
+
+/* Fixed priority DRAM Requests mask */
+#define REQ_PRI_VGA_HW_CURSOR_R         0
+#define REQ_PRI_VGA_CRT_R               1
+#define REQ_PRI_SOC_DISPLAY_CTRL_R      2
+#define REQ_PRI_PCIE_BUS1_RW            3
+#define REQ_PRI_VIDEO_HIGH_PRI_W        4
+#define REQ_PRI_CPU_RW                  5
+#define REQ_PRI_SLI_RW                  6
+#define REQ_PRI_PCIE_BUS2_RW            7
+#define REQ_PRI_USB2_0_HUB_EHCI1_DMA_RW 8
+#define REQ_PRI_USB2_0_DEV_EHCI2_DMA_RW 9
+#define REQ_PRI_USB1_1_UHCI_HOST_RW     10
+#define REQ_PRI_AHB_BUS_RW              11
+#define REQ_PRI_CM3_DATA_RW             12
+#define REQ_PRI_CM3_INST_R              13
+#define REQ_PRI_MAC0_DMA_RW             14
+#define REQ_PRI_MAC1_DMA_RW             15
+#define REQ_PRI_SDIO_DMA_RW             16
+#define REQ_PRI_PILOT_ENGINE_RW         17
+#define REQ_PRI_XDMA1_RW                18
+#define REQ_PRI_MCTP1_RW                19
+#define REQ_PRI_VIDEO_FLAG_RW           20
+#define REQ_PRI_VIDEO_LOW_PRI_W         21
+#define REQ_PRI_2D_ENGINE_DATA_RW       22
+#define REQ_PRI_ENC_ENGINE_RW           23
+#define REQ_PRI_MCTP2_RW                24
+#define REQ_PRI_XDMA2_RW                25
+#define REQ_PRI_ECC_RSA_RW              26
+
+#define MCR30_RESET_DLL_DELAY_EN	BIT(4)
+#define MCR30_MODE_REG_SEL_SHIFT	1
+#define MCR30_MODE_REG_SEL_MASK		GENMASK(3, 1)
+#define MCR30_SET_MODE_REG		BIT(0)
+
+#define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_SHIFT) | MCR30_SET_MODE_REG)
+
+#define MCR34_SELF_REFRESH_STATUS_MASK	GENMASK(30, 28)
+
+#define MCR34_ODT_DELAY_SHIFT		12
+#define MCR34_ODT_DELAY_MASK		GENMASK(15, 12)
+#define MCR34_ODT_EXT_SHIFT		10
+#define MCR34_ODT_EXT_MASK		GENMASK(11, 10)
+#define MCR34_ODT_AUTO_ON		BIT(9)
+#define MCR34_ODT_EN			BIT(8)
+#define MCR34_RESETN_DIS		BIT(7)
+#define MCR34_MREQI_DIS			BIT(6)
+#define MCR34_MREQ_BYPASS_DIS		BIT(5)
+#define MCR34_RGAP_CTRL_EN		BIT(4)
+#define MCR34_CKE_OUT_IN_SELF_REF_DIS	BIT(3)
+#define MCR34_FOURCE_SELF_REF_EN	BIT(2)
+#define MCR34_AUTOPWRDN_EN		BIT(1)
+#define MCR34_CKE_EN			BIT(0)
+
+#define MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT	16
+#define MCR38_RW_MAX_GRANT_CNT_RQ_MASK	GENMASK(20, 16)
+
+/* default request queued limitation mask (0xFFBBFFF4) */
+#define MCR3C_DEFAULT_MASK                                                     \
+	~(REQ_PRI_VGA_HW_CURSOR_R | REQ_PRI_VGA_CRT_R | REQ_PRI_PCIE_BUS1_RW | \
+	  REQ_PRI_XDMA1_RW | REQ_PRI_2D_ENGINE_DATA_RW)
+
+#define MCR50_RESET_ALL_INTR		BIT(31)
+#define SDRAM_CONF_ECC_AUTO_SCRUBBING	BIT(9)
+#define SDRAM_CONF_SCRAMBLE		BIT(8)
+#define SDRAM_CONF_ECC_EN		BIT(7)
+#define SDRAM_CONF_DUALX8		BIT(5)
+#define SDRAM_CONF_DDR4			BIT(4)
+#define SDRAM_CONF_VGA_SIZE_SHIFT	2
+#define SDRAM_CONF_VGA_SIZE_MASK	GENMASK(3, 2)
+#define SDRAM_CONF_CAP_SHIFT		0
+#define SDRAM_CONF_CAP_MASK		GENMASK(1, 0)
+
+#define SDRAM_CONF_CAP_256M		0
+#define SDRAM_CONF_CAP_512M		1
+#define SDRAM_CONF_CAP_1024M		2
+#define SDRAM_CONF_CAP_2048M		3
+#define SDRAM_CONF_ECC_SETUP		(SDRAM_CONF_ECC_AUTO_SCRUBBING | SDRAM_CONF_ECC_EN)
+
+#define SDRAM_MISC_DDR4_TREFRESH	(1 << 3)
+
+#define SDRAM_PHYCTRL0_PLL_LOCKED	BIT(4)
+#define SDRAM_PHYCTRL0_NRST		BIT(2)
+#define SDRAM_PHYCTRL0_INIT		BIT(0)
+
+/* MCR0C */
+#define SDRAM_REFRESH_PERIOD_ZQCS_SHIFT	16
+#define SDRAM_REFRESH_PERIOD_ZQCS_MASK	GENMASK(31, 16)
+#define SDRAM_REFRESH_PERIOD_SHIFT	8
+#define SDRAM_REFRESH_PERIOD_MASK	GENMASK(15, 8)
+#define SDRAM_REFRESH_ZQCS_EN		BIT(7)
+#define SDRAM_RESET_DLL_ZQCL_EN		BIT(6)
+#define SDRAM_LOW_PRI_REFRESH_EN	BIT(5)
+#define SDRAM_FORCE_PRECHARGE_EN	BIT(4)
+#define SDRAM_REFRESH_EN		BIT(0)
+
+#define SDRAM_TEST_LEN_SHIFT		4
+#define SDRAM_TEST_LEN_MASK		0xfffff
+#define SDRAM_TEST_START_ADDR_SHIFT	24
+#define SDRAM_TEST_START_ADDR_MASK	0x3f
+
+#define SDRAM_TEST_EN			(1 << 0)
+#define SDRAM_TEST_MODE_SHIFT		1
+#define SDRAM_TEST_MODE_MASK		(0x3 << SDRAM_TEST_MODE_SHIFT)
+#define SDRAM_TEST_MODE_WO		(0x0 << SDRAM_TEST_MODE_SHIFT)
+#define SDRAM_TEST_MODE_RB		(0x1 << SDRAM_TEST_MODE_SHIFT)
+#define SDRAM_TEST_MODE_RW		(0x2 << SDRAM_TEST_MODE_SHIFT)
+
+#define SDRAM_TEST_GEN_MODE_SHIFT	3
+#define SDRAM_TEST_GEN_MODE_MASK	(7 << SDRAM_TEST_GEN_MODE_SHIFT)
+#define SDRAM_TEST_TWO_MODES		(1 << 6)
+#define SDRAM_TEST_ERRSTOP		(1 << 7)
+#define SDRAM_TEST_DONE			(1 << 12)
+#define SDRAM_TEST_FAIL			(1 << 13)
+
+#define SDRAM_AC_TRFC_SHIFT		0
+#define SDRAM_AC_TRFC_MASK		0xff
+
+#define SDRAM_ECC_RANGE_ADDR_MASK	GENMASK(30, 20)
+#define SDRAM_ECC_RANGE_ADDR_SHIFT	20
+
+#ifndef __ASSEMBLY__
+struct ast2600_sdrammc_regs {
+	u32 protection_key;		/* offset 0x00 */
+	u32 config;			/* offset 0x04 */
+	u32 gm_protection_key;		/* offset 0x08 */
+	u32 refresh_timing;		/* offset 0x0C */
+	u32 ac_timing[4];		/* offset 0x10 ~ 0x1C */
+	u32 mr01_mode_setting;		/* offset 0x20 */
+	u32 mr23_mode_setting;		/* offset 0x24 */
+	u32 mr45_mode_setting;		/* offset 0x28 */
+	u32 mr6_mode_setting;		/* offset 0x2C */
+	u32 mode_setting_control;	/* offset 0x30 */
+	u32 power_ctrl;			/* offset 0x34 */
+	u32 arbitration_ctrl;		/* offset 0x38 */
+	u32 req_limit_mask;		/* offset 0x3C */
+	u32 max_grant_len[4];		/* offset 0x40 ~ 0x4C */
+	u32 intr_ctrl;			/* offset 0x50 */
+	u32 ecc_range_ctrl;		/* offset 0x54 */
+	u32 first_ecc_err_addr;		/* offset 0x58 */
+	u32 last_ecc_err_addr;		/* offset 0x5C */
+	u32 phy_ctrl[4];		/* offset 0x60 ~ 0x6C */
+	u32 ecc_test_ctrl;		/* offset 0x70 */
+	u32 test_addr;			/* offset 0x74 */
+	u32 test_fail_dq_bit;		/* offset 0x78 */
+	u32 test_init_val;		/* offset 0x7C */
+	u32 req_input_ctrl;		/* offset 0x80 */
+	u32 req_high_pri_ctrl;		/* offset 0x84 */
+	u32 reserved0[6];		/* offset 0x88 ~ 0x9C */
+};
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _ASM_ARCH_SDRAM_AST2600_H */

arch/arm/include/asm/arch-aspeed/wdt_ast2600.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 Aspeed Technology Inc.
+ */
+
+#ifndef _ASM_ARCH_WDT_AST2600_H
+#define _ASM_ARCH_WDT_AST2600_H
+
+#define WDT_BASE			0x1e785000
+
+/*
+ * Special value that needs to be written to counter_restart register to
+ * (re)start the timer
+ */
+#define WDT_COUNTER_RESTART_VAL		0x4755
+
+/* reset mode */
+#define WDT_RESET_MODE_SOC		0
+#define WDT_RESET_MODE_CHIP		1
+#define WDT_RESET_MODE_CPU		2
+
+/* bit-fields of WDT control register */
+#define WDT_CTRL_2ND_BOOT		BIT(7)
+#define WDT_CTRL_RESET_MODE_MASK	GENMASK(6, 5)
+#define WDT_CTRL_RESET_MODE_SHIFT	5
+#define WDT_CTRL_CLK1MHZ		BIT(4)
+#define WDT_CTRL_RESET			BIT(1)
+#define WDT_CTRL_EN			BIT(0)
+
+/* bit-fields of WDT reset mask1 register */
+#define WDT_RESET_MASK1_RVAS		BIT(25)
+#define WDT_RESET_MASK1_GPIO1		BIT(24)
+#define WDT_RESET_MASK1_XDMA2		BIT(23)
+#define WDT_RESET_MASK1_XDMA1		BIT(22)
+#define WDT_RESET_MASK1_MCTP2		BIT(21)
+#define WDT_RESET_MASK1_MCTP1		BIT(20)
+#define WDT_RESET_MASK1_JTAG1		BIT(19)
+#define WDT_RESET_MASK1_SD_SDIO1	BIT(18)
+#define WDT_RESET_MASK1_MAC2		BIT(17)
+#define WDT_RESET_MASK1_MAC1		BIT(16)
+#define WDT_RESET_MASK1_GPMCU		BIT(15)
+#define WDT_RESET_MASK1_DPMCU		BIT(14)
+#define WDT_RESET_MASK1_DP		BIT(13)
+#define WDT_RESET_MASK1_HAC		BIT(12)
+#define WDT_RESET_MASK1_VIDEO		BIT(11)
+#define WDT_RESET_MASK1_CRT		BIT(10)
+#define WDT_RESET_MASK1_GCRT		BIT(9)
+#define WDT_RESET_MASK1_USB11_UHCI	BIT(8)
+#define WDT_RESET_MASK1_USB_PORTA	BIT(7)
+#define WDT_RESET_MASK1_USB_PORTB	BIT(6)
+#define WDT_RESET_MASK1_COPROC		BIT(5)
+#define WDT_RESET_MASK1_SOC		BIT(4)
+#define WDT_RESET_MASK1_SLI		BIT(3)
+#define WDT_RESET_MASK1_AHB		BIT(2)
+#define WDT_RESET_MASK1_SDRAM		BIT(1)
+#define WDT_RESET_MASK1_ARM		BIT(0)
+
+/* bit-fields of WDT reset mask2 register */
+#define WDT_RESET_MASK2_ESPI		BIT(26)
+#define WDT_RESET_MASK2_I3C_BUS8	BIT(25)
+#define WDT_RESET_MASK2_I3C_BUS7	BIT(24)
+#define WDT_RESET_MASK2_I3C_BUS6	BIT(23)
+#define WDT_RESET_MASK2_I3C_BUS5	BIT(22)
+#define WDT_RESET_MASK2_I3C_BUS4	BIT(21)
+#define WDT_RESET_MASK2_I3C_BUS3	BIT(20)
+#define WDT_RESET_MASK2_I3C_BUS2	BIT(19)
+#define WDT_RESET_MASK2_I3C_BUS1	BIT(18)
+#define WDT_RESET_MASK2_I3C_GLOBAL	BIT(17)
+#define WDT_RESET_MASK2_I2C		BIT(16)
+#define WDT_RESET_MASK2_FSI		BIT(15)
+#define WDT_RESET_MASK2_ADC		BIT(14)
+#define WDT_RESET_MASK2_PWM		BIT(13)
+#define WDT_RESET_MASK2_PECI		BIT(12)
+#define WDT_RESET_MASK2_LPC		BIT(11)
+#define WDT_RESET_MASK2_MDC_MDIO	BIT(10)
+#define WDT_RESET_MASK2_GPIO2		BIT(9)
+#define WDT_RESET_MASK2_JTAG2		BIT(8)
+#define WDT_RESET_MASK2_SD_SDIO2	BIT(7)
+#define WDT_RESET_MASK2_MAC4		BIT(6)
+#define WDT_RESET_MASK2_MAC3		BIT(5)
+#define WDT_RESET_MASK2_SOC		BIT(4)
+#define WDT_RESET_MASK2_SLI2		BIT(3)
+#define WDT_RESET_MASK2_AHB2		BIT(2)
+#define WDT_RESET_MASK2_SPI1_SPI2	BIT(1)
+#define WDT_RESET_MASK2_ARM		BIT(0)
+
+#define WDT_RESET_MASK1_DEFAULT						\
+	(WDT_RESET_MASK1_RVAS | WDT_RESET_MASK1_GPIO1 |			\
+	 WDT_RESET_MASK1_JTAG1 | WDT_RESET_MASK1_SD_SDIO1 |		\
+	 WDT_RESET_MASK1_MAC2 | WDT_RESET_MASK1_MAC1 |			\
+	 WDT_RESET_MASK1_HAC | WDT_RESET_MASK1_VIDEO |			\
+	 WDT_RESET_MASK1_CRT | WDT_RESET_MASK1_GCRT |			\
+	 WDT_RESET_MASK1_USB11_UHCI | WDT_RESET_MASK1_USB_PORTA	|	\
+	 WDT_RESET_MASK1_USB_PORTB | WDT_RESET_MASK1_COPROC |		\
+	 WDT_RESET_MASK1_SOC | WDT_RESET_MASK1_ARM)
+
+#define WDT_RESET_MASK2_DEFAULT						\
+	(WDT_RESET_MASK2_I3C_BUS8 | WDT_RESET_MASK2_I3C_BUS7 |		\
+	 WDT_RESET_MASK2_I3C_BUS6 | WDT_RESET_MASK2_I3C_BUS5 |		\
+	 WDT_RESET_MASK2_I3C_BUS4 | WDT_RESET_MASK2_I3C_BUS3 |		\
+	 WDT_RESET_MASK2_I3C_BUS2 | WDT_RESET_MASK2_I3C_BUS1 |		\
+	 WDT_RESET_MASK2_I3C_GLOBAL | WDT_RESET_MASK2_I2C |		\
+	 WDT_RESET_MASK2_FSI | WDT_RESET_MASK2_ADC |			\
+	 WDT_RESET_MASK2_PWM | WDT_RESET_MASK2_PECI |			\
+	 WDT_RESET_MASK2_LPC | WDT_RESET_MASK2_MDC_MDIO |		\
+	 WDT_RESET_MASK2_GPIO2 | WDT_RESET_MASK2_JTAG2 |		\
+	 WDT_RESET_MASK2_SD_SDIO2 | WDT_RESET_MASK2_MAC4 |		\
+	 WDT_RESET_MASK2_MAC3 | WDT_RESET_MASK2_SOC |			\
+	 WDT_RESET_MASK2_ARM)
+
+#ifndef __ASSEMBLY__
+struct ast2600_wdt {
+	u32 counter_status;
+	u32 counter_reload_val;
+	u32 counter_restart;
+	u32 ctrl;
+	u32 timeout_status;
+	u32 clr_timeout_status;
+	u32 reset_width;
+	u32 reset_mask1;
+	u32 reset_mask2;
+	u32 sw_reset_ctrl;
+	u32 sw_reset_mask1;
+	u32 sw_reset_mask2;
+	u32 sw_reset_disable;
+};
+#endif  /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARCH_WDT_AST2600_H */

arch/arm/include/asm/gpio.h

@@ -3,7 +3,8 @@
 	!defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
 	!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
 	!defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \
-	!defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE)
+	!defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \
+	!defined(CONFIG_ARCH_QEMU)
 #include <asm/arch/gpio.h>
 #endif
 #include <asm-generic/gpio.h>

arch/arm/mach-aspeed/Kconfig

@@ -9,6 +9,11 @@ config SYS_SOC
 config SYS_TEXT_BASE
 	default 0x00000000
 
+choice
+	prompt "Aspeed SoC select"
+	depends on ARCH_ASPEED
+	default ASPEED_AST2500
+
 config ASPEED_AST2500
 	bool "Support Aspeed AST2500 SoC"
 	depends on DM_RESET
@@ -18,6 +23,21 @@ config ASPEED_AST2500
 	  It is used as Board Management Controller on many server boards,
 	  which is enabled by support of LPC and eSPI peripherals.
 
+config ASPEED_AST2600
+	bool "Support Aspeed AST2600 SoC"
+	select CPU_V7A
+	select CPU_V7_HAS_NONSEC
+	select SYS_ARCH_TIMER
+	select SUPPORT_SPL
+	select ENABLE_ARM_SOC_BOOT0_HOOK
+	help
+	  The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU.
+	  It is used as Board Management Controller on many server boards,
+	  which is enabled by support of LPC and eSPI peripherals.
+
+endchoice
+
 source "arch/arm/mach-aspeed/ast2500/Kconfig"
+source "arch/arm/mach-aspeed/ast2600/Kconfig"
 
 endif

arch/arm/mach-aspeed/Makefile

@@ -4,3 +4,4 @@
 
 obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o
 obj-$(CONFIG_ASPEED_AST2500) += ast2500/
+obj-$(CONFIG_ASPEED_AST2600) += ast2600/

arch/arm/mach-aspeed/ast2600/Kconfig

+if ASPEED_AST2600
+
+config SYS_CPU
+	default "armv7"
+
+config TARGET_EVB_AST2600
+	bool "EVB-AST2600"
+	depends on ASPEED_AST2600
+	help
+	  EVB-AST2600 is Aspeed evaluation board for AST2600A0 chip.
+	  It has 512M of RAM, 32M of SPI flash, two Ethernet ports,
+	  4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot,
+	  20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs.
+
+source "board/aspeed/evb_ast2600/Kconfig"
+
+endif

arch/arm/mach-aspeed/ast2600/Makefile

+obj-y   += lowlevel_init.o board_common.o
+obj-$(CONFIG_SPL_BUILD) += spl.o

arch/arm/mach-aspeed/ast2600/board_common.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <dm/uclass.h>
+#include <asm/arch/scu_ast2600.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Memory Control registers */
+#define MCR_BASE			0x1e6e0000
+#define MCR_CONF			(MCR_BASE + 0x004)
+
+/* bit fields of MCR_CONF */
+#define MCR_CONF_ECC_EN			BIT(7)
+#define MCR_CONF_VGA_MEMSZ_MASK		GENMASK(3, 2)
+#define MCR_CONF_VGA_MEMSZ_SHIFT	2
+#define MCR_CONF_MEMSZ_MASK		GENMASK(1, 0)
+#define MCR_CONF_MEMSZ_SHIFT		0
+
+int dram_init(void)
+{
+	int ret;
+	struct udevice *dev;
+	struct ram_info ram;
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("cannot get DRAM driver\n");
+		return ret;
+	}
+
+	ret = ram_get_info(dev, &ram);
+	if (ret) {
+		debug("cannot get DRAM information\n");
+		return ret;
+	}
+
+	gd->ram_size = ram.size;
+	return 0;
+}
+
+int board_init(void)
+{
+	int i = 0, rc;
+	struct udevice *dev;
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	while (1) {
+		rc = uclass_get_device(UCLASS_MISC, i++, &dev);
+		if (rc)
+			break;
+	}
+
+	return 0;
+}
+
+void board_add_ram_info(int use_default)
+{
+	int rc;
+	uint32_t conf;
+	uint32_t ecc, act_size, vga_rsvd;
+	struct udevice *scu_dev;
+	struct ast2600_scu *scu;
+
+	rc = uclass_get_device_by_driver(UCLASS_CLK,
+					 DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
+	if (rc) {
+		debug("%s: cannot find SCU device, rc=%d\n", __func__, rc);
+		return;
+	}
+
+	scu = devfdt_get_addr_ptr(scu_dev);
+	if (IS_ERR_OR_NULL(scu)) {
+		debug("%s: cannot get SCU address pointer\n", __func__);
+		return;
+	}
+
+	conf = readl(MCR_CONF);
+
+	ecc = conf & MCR_CONF_ECC_EN;
+	act_size = 0x100 << ((conf & MCR_CONF_MEMSZ_MASK) >> MCR_CONF_MEMSZ_SHIFT);
+	vga_rsvd = 0x8 << ((conf & MCR_CONF_VGA_MEMSZ_MASK) >> MCR_CONF_VGA_MEMSZ_SHIFT);
+
+	/* no VGA reservation if efuse VGA disable bit is set */
+	if (readl(scu->efuse) & SCU_EFUSE_DIS_VGA)
+		vga_rsvd = 0;
+
+	printf(" (capacity:%d MiB, VGA:%d MiB), ECC %s", act_size,
+	       vga_rsvd, (ecc) ? "on" : "off");
+}
+
+void enable_caches(void)
+{
+	/* get rid of the warning message */
+}

arch/arm/mach-aspeed/ast2600/lowlevel_init.S

+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) ASPEED Technology Inc.
+ */
+#include <config.h>
+#include <asm/armv7.h>
+#include <linux/linkage.h>
+#include <asm/arch/scu_ast2600.h>
+
+/* SCU register offsets */
+#define SCU_BASE		0x1e6e2000
+#define SCU_PROT_KEY1		(SCU_BASE + 0x000)
+#define SCU_PROT_KEY2		(SCU_BASE + 0x010)
+#define SCU_SMP_BOOT		(SCU_BASE + 0x180)
+#define SCU_HWSTRAP1		(SCU_BASE + 0x510)
+#define SCU_CA7_PARITY_CHK	(SCU_BASE + 0x820)
+#define SCU_CA7_PARITY_CLR	(SCU_BASE + 0x824)
+#define SCU_MMIO_DEC		(SCU_BASE + 0xc24)
+
+/* FMC SPI register offsets */
+#define FMC_BASE		0x1e620000
+#define FMC_CE0_CTRL		(FMC_BASE + 0x010)
+#define FMC_SW_RST_CTRL		(FMC_BASE + 0x050)
+#define FMC_WDT1_CTRL_MODE	(FMC_BASE + 0x060)
+#define FMC_WDT2_CTRL_MODE	(FMC_BASE + 0x064)
+
+/*
+ * The SMP mailbox provides a space with few instructions in it
+ * for secondary cores to execute on and wait for the signal of
+ * SMP core bring up.
+ *
+ *       SMP mailbox
+ * +----------------------+
+ * |                      |
+ * | mailbox insn. for    |
+ * | cpuN polling SMP go  |
+ * |                      |
+ * +----------------------+ 0xC
+ * | mailbox ready signal |
+ * +----------------------+ 0x8
+ * | cpuN GO signal       |
+ * +----------------------+ 0x4
+ * | cpuN entrypoint      |
+ * +----------------------+ SMP_MAILBOX_BASE
+ */
+#define SMP_MBOX_BASE		(SCU_SMP_BOOT)
+#define SMP_MBOX_FIELD_ENTRY	(SMP_MBOX_BASE + 0x0)
+#define SMP_MBOX_FIELD_GOSIGN	(SMP_MBOX_BASE + 0x4)
+#define SMP_MBOX_FIELD_READY	(SMP_MBOX_BASE + 0x8)
+#define SMP_MBOX_FIELD_POLLINSN	(SMP_MBOX_BASE + 0xc)
+
+.macro scu_unlock
+	movw	r0, #(SCU_UNLOCK_KEY & 0xffff)
+	movt	r0, #(SCU_UNLOCK_KEY >> 16)
+
+	ldr	r1, =SCU_PROT_KEY1
+	str	r0, [r1]
+	ldr	r1, =SCU_PROT_KEY2
+	str	r0, [r1]
+.endm
+
+.macro timer_init
+	ldr	r1, =SCU_HWSTRAP1
+	ldr	r1, [r1]
+	and	r1, #0x700
+	lsr	r1, #0x8
+
+	/* 1.2GHz */
+	cmp	r1, #0x0
+	movweq	r0, #0x8c00
+	movteq	r0, #0x4786
+
+	/* 1.6GHz */
+	cmp	r1, #0x1
+	movweq	r0, #0x1000
+	movteq	r0, #0x5f5e
+
+	/* 1.2GHz */
+	cmp	r1, #0x2
+	movweq	r0, #0x8c00
+	movteq	r0, #0x4786
+
+	/* 1.6GHz */
+	cmp	r1, #0x3
+	movweq	r0, #0x1000
+	movteq	r0, #0x5f5e
+
+	/* 800MHz */
+	cmp	r1, #0x4
+	movwge	r0, #0x0800
+	movtge	r0, #0x2faf
+
+	mcr	p15, 0, r0, c14, c0, 0	@; update CNTFRQ
+.endm
+
+
+.globl lowlevel_init
+
+lowlevel_init:
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	mov	pc, lr
+#else
+	/* setup ARM arch timer frequency */
+	timer_init
+
+	/* reset SMP mailbox as early as possible */
+	mov	r0, #0x0
+	ldr	r1, =SMP_MBOX_FIELD_READY
+	str	r0, [r1]
+
+	/* set ACTLR.SMP to enable cache use */
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, #0x40
+	mcr	p15, 0, r0, c1, c0, 1
+
+	/*
+	 * we treat cpu0 as the primary core and
+	 * put secondary core (cpuN) to sleep
+	 */
+	mrc   p15, 0, r0, c0, c0, 5	@; Read CPU ID register
+	ands  r0, #0xff			@; Mask off, leaving the CPU ID field
+	movw  r2, #0xab00
+	movt  r2, #0xabba
+	orr   r2, r0
+
+	beq   do_primary_core_setup
+
+	/* hold cpuN until mailbox is ready */
+poll_mailbox_ready:
+	wfe
+	ldr	r0, =SMP_MBOX_FIELD_READY
+	ldr	r0, [r0]
+	movw	r1, #0xcafe
+	movt	r1, #0xbabe
+	cmp	r1, r0
+	bne	poll_mailbox_ready
+
+	/* parameters for relocated SMP go polling insn. */
+	ldr	r0, =SMP_MBOX_FIELD_GOSIGN
+	ldr	r1, =SMP_MBOX_FIELD_ENTRY
+
+	/* no return */
+	ldr	pc, =SMP_MBOX_FIELD_POLLINSN
+
+do_primary_core_setup:
+	scu_unlock
+
+	/* MMIO decode setting */
+	ldr	r0, =SCU_MMIO_DEC
+	mov	r1, #0x2000
+	str	r1, [r0]
+
+	/* enable CA7 cache parity check */
+	mov	r0, #0
+	ldr	r1, =SCU_CA7_PARITY_CLR
+	str	r0, [r1]
+
+	mov	r0, #0x1
+	ldr	r1, =SCU_CA7_PARITY_CHK
+	str	r0, [r1]
+
+	/* do not fill FMC50[1] if boot from eMMC */
+	ldr	r0, =SCU_HWSTRAP1
+	ldr	r1, [r0]
+	ands	r1, #0x04
+	bne	skip_fill_wip_bit
+
+	/* fill FMC50[1] for waiting WIP idle */
+	mov	r0, #0x02
+	ldr	r1, =FMC_SW_RST_CTRL
+	str	r0, [r1]
+
+skip_fill_wip_bit:
+	/* disable FMC WDT for SPI address mode detection */
+	mov	r0, #0
+	ldr	r1, =FMC_WDT1_CTRL_MODE
+	str	r0, [r1]
+
+	/* relocate mailbox insn. for cpuN polling SMP go signal */
+	adrl	r0, mailbox_insn
+	adrl	r1, mailbox_insn_end
+
+	ldr	r2, =#SMP_MBOX_FIELD_POLLINSN
+
+relocate_mailbox_insn:
+	ldr	r3, [r0], #0x4
+	str	r3, [r2], #0x4
+	cmp	r0, r1
+	bne	relocate_mailbox_insn
+
+	/* reset SMP go sign */
+	mov	r0, #0
+	ldr	r1, =SMP_MBOX_FIELD_GOSIGN
+	str	r0, [r1]
+
+	/* notify cpuN mailbox is ready */
+	movw	r0, #0xCAFE
+	movt	r0, #0xBABE
+	ldr	r1, =SMP_MBOX_FIELD_READY
+	str	r0, [r1]
+	sev
+
+	/* back to arch calling code */
+	mov	pc, lr
+
+/*
+ * insn. inside mailbox to poll SMP go signal.
+ *
+ * Note that as this code will be relocated, any
+ * pc-relative assembly should NOT be used.
+ */
+mailbox_insn:
+	/*
+	 * r0 ~ r3 are parameters:
+	 *  r0 = SMP_MBOX_FIELD_GOSIGN
+	 *  r1 = SMP_MBOX_FIELD_ENTRY
+	 *  r2 = per-cpu go sign value
+	 *  r3 = no used now
+	 */
+poll_mailbox_smp_go:
+	wfe
+	ldr	r4, [r0]
+	cmp	r2, r4
+	bne	poll_mailbox_smp_go
+
+	/* SMP GO signal confirmed, release cpuN */
+	ldr	pc, [r1]
+
+mailbox_insn_end:
+	/* should never reach */
+	b	.
+
+#endif

arch/arm/mach-aspeed/ast2600/spl.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <spl.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2600.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+	spl_early_init();
+	preloader_console_init();
+	timer_init();
+	dram_init();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_RAM;
+}
+
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+	/*
+	 * When boot from SPI, AST2600 already remap 0x00000000 ~ 0x0fffffff
+	 * to BMC SPI memory space 0x20000000 ~ 0x2fffffff. The next stage BL
+	 * has been located in SPI for XIP. In this case, the load buffer for
+	 * SPL image loading will be set to the remapped address of the next
+	 * BL instead of the DRAM space CONFIG_SYS_LOAD_ADDR
+	 */
+	return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* boot linux */
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+	return 0;
+}
+#endif

board/aspeed/evb_ast2600/Kconfig

+if TARGET_EVB_AST2600
+
+config SYS_BOARD
+	default "evb_ast2600"
+
+config SYS_VENDOR
+	default "aspeed"
+
+config SYS_CONFIG_NAME
+	default "evb_ast2600"
+
+endif

board/aspeed/evb_ast2600/MAINTAINERS

+EVB AST2600 BOARD
+M:	Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
+S:	Maintained
+F:	board/aspeed/evb_ast2600/
+F:	include/configs/evb_ast2600.h
+F:	configs/evb-ast2600_defconfig

board/aspeed/evb_ast2600/Makefile

+obj-y += evb_ast2600.o

board/aspeed/evb_ast2600/evb_ast2600.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#include <common.h>

board/keymile/km_arm/Kconfig

@@ -58,8 +58,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
+	select USB
+	select USB_EHCI_HCD
+	select USB_EHCI_MARVELL
 	imply CMD_CRAMFS
 	imply CMD_DIAG
 	imply FS_CRAMFS
+	imply CMD_USB
 
 endif

board/mediatek/pumpkin/pumpkin.c

@@ -4,8 +4,25 @@
  */
 
 #include <common.h>
+#include <dm.h>
 
 int board_init(void)
 {
 	return 0;
 }
+
+int board_late_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (CONFIG_IS_ENABLED(USB_GADGET)) {
+		ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+		if (ret) {
+			pr_err("%s: Cannot find USB device\n", __func__);
+			return ret;
+		}
+	}
+
+	return 0;
+}

cmd/Kconfig

@@ -928,6 +928,12 @@ config CMD_GPIO
 	help
 	  GPIO support.
 
+config CMD_PWM
+	bool "pwm"
+	depends on DM_PWM
+	help
+	  Control PWM channels, this allows invert/config/enable/disable PWM channels.
+
 config CMD_GPT
 	bool "GPT (GUID Partition Table) command"
 	select EFI_PARTITION

cmd/Makefile

@@ -120,6 +120,7 @@ endif
 obj-$(CONFIG_CMD_PINMUX) += pinmux.o
 obj-$(CONFIG_CMD_PMC) += pmc.o
 obj-$(CONFIG_CMD_PSTORE) += pstore.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
 obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
 obj-$(CONFIG_CMD_WOL) += wol.o
 obj-$(CONFIG_CMD_QFW) += qfw.o

cmd/pwm.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Control PWM channels
+ *
+ * Copyright (c) 2020 SiFive, Inc
+ * author: Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <command.h>
+#include <dm.h>
+#include <pwm.h>
+
+enum pwm_cmd {
+	PWM_SET_INVERT,
+	PWM_SET_CONFIG,
+	PWM_SET_ENABLE,
+	PWM_SET_DISABLE,
+};
+
+static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
+		  char *const argv[])
+{
+	const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
+	const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
+	enum pwm_cmd sub_cmd;
+	struct udevice *dev;
+	u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
+	int ret;
+
+	if (argc < 4)
+		return CMD_RET_USAGE;
+
+	str_cmd = argv[1];
+	argc -= 2;
+	argv += 2;
+
+	if (argc > 0) {
+		str_pwm = *argv;
+		argc--;
+		argv++;
+	}
+
+	if (!str_pwm)
+		return CMD_RET_USAGE;
+
+	switch (*str_cmd) {
+	case 'i':
+		sub_cmd = PWM_SET_INVERT;
+		break;
+	case 'c':
+		sub_cmd = PWM_SET_CONFIG;
+		break;
+	case 'e':
+		sub_cmd = PWM_SET_ENABLE;
+		break;
+	case 'd':
+		sub_cmd = PWM_SET_DISABLE;
+		break;
+	default:
+		return CMD_RET_USAGE;
+	}
+
+	pwm_dev = simple_strtoul(str_pwm, NULL, 10);
+	ret = uclass_get_device(UCLASS_PWM, pwm_dev, &dev);
+	if (ret) {
+		printf("pwm: '%s' not found\n", str_pwm);
+		return cmd_process_error(cmdtp, ret);
+	}
+
+	if (argc > 0) {
+		str_channel = *argv;
+		channel = simple_strtoul(str_channel, NULL, 10);
+		argc--;
+		argv++;
+	} else {
+		return CMD_RET_USAGE;
+	}
+
+	if (sub_cmd == PWM_SET_INVERT && argc > 0) {
+		str_enable = *argv;
+		pwm_enable = simple_strtoul(str_enable, NULL, 10);
+		ret = pwm_set_invert(dev, channel, pwm_enable);
+	} else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
+		str_period = *argv;
+		argc--;
+		argv++;
+		period_ns = simple_strtoul(str_period, NULL, 10);
+
+		if (argc > 0) {
+			str_duty = *argv;
+			duty_ns = simple_strtoul(str_duty, NULL, 10);
+		}
+
+		ret = pwm_set_config(dev, channel, period_ns, duty_ns);
+	} else if (sub_cmd == PWM_SET_ENABLE) {
+		ret = pwm_set_enable(dev, channel, 1);
+	} else if (sub_cmd == PWM_SET_DISABLE) {
+		ret = pwm_set_enable(dev, channel, 0);
+	} else {
+		printf("PWM arguments missing\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (ret) {
+		printf("error(%d)\n", ret);
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(pwm, 6, 0, do_pwm,
+	   "control pwm channels",
+	   "pwm <invert> <pwm_dev_num> <channel> <polarity>\n"
+	   "pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns>\n"
+	   "pwm <enable/disable> <pwm_dev_num> <channel>\n"
+	   "Note: All input values are in decimal");

configs/cortina_presidio-asic-pnand_defconfig

+CONFIG_ARM=y
+# CONFIG_SYS_ARCH_TIMER is not set
+CONFIG_TARGET_PRESIDIO_ASIC=y
+CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_IDENT_STRING="Presidio-SoC"
+CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SYS_PROMPT="G3#"
+CONFIG_CMD_MTD=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_SMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_NET is not set
+CONFIG_DM=y
+CONFIG_CORTINA_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_CORTINA_NAND=y
+CONFIG_DM_SERIAL=y
+CONFIG_CORTINA_UART=y
+CONFIG_WDT=y
+CONFIG_WDT_CORTINA=y

configs/evb-ast2600_defconfig

+CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_ASPEED=y
+CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_ASPEED_AST2600=y
+CONFIG_TARGET_EVB_AST2600=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SIZE_LIMIT=0x10000
+CONFIG_SPL=y
+# CONFIG_ARMV7_NONSEC is not set
+CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="bootm 20100000"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_SPL_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ASPEED=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_FTGMAC100=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_WDT=y
+CONFIG_HEXDUMP=y
+# CONFIG_SPL_HEXDUMP is not set
+# CONFIG_EFI_LOADER is not set

configs/km_kirkwood_128m16_defconfig

@@ -8,7 +8,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_ENV_OFFSET_REDUND=0x2000
-CONFIG_IDENT_STRING="\nKeymile Kirkwood 128M16"
+CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood 128M16"
 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
 CONFIG_AUTOBOOT_KEYED=y
@@ -17,16 +17,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"

configs/km_kirkwood_defconfig

@@ -8,7 +8,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_ENV_OFFSET_REDUND=0x2000
-CONFIG_IDENT_STRING="\nKeymile Kirkwood"
+CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
 CONFIG_AUTOBOOT_KEYED=y
@@ -17,16 +17,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"

configs/km_kirkwood_pci_defconfig

@@ -9,7 +9,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_ENV_OFFSET_REDUND=0x2000
-CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI"
+CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood PCI"
 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
 CONFIG_AUTOBOOT_KEYED=y
@@ -18,16 +18,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
@@ -46,6 +48,7 @@ CONFIG_BOOTCOUNT_RAM=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SF_DEFAULT_SPEED=8100000
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MVGBE=y
 CONFIG_MII=y

configs/kmcoge5un_defconfig

@@ -12,7 +12,7 @@ CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_ENV_OFFSET_REDUND=0xD0000
-CONFIG_IDENT_STRING="\nKeymile COGE5UN"
+CONFIG_IDENT_STRING="\nHitachi Power Grids COGE5UN"
 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
 CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
 CONFIG_AUTOBOOT_KEYED=y
@@ -21,16 +21,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"

configs/kmnusa_defconfig

@@ -12,7 +12,7 @@ CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_ENV_OFFSET_REDUND=0xD0000
-CONFIG_IDENT_STRING="\nKeymile NUSA"
+CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
 CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
 CONFIG_AUTOBOOT_KEYED=y
@@ -21,16 +21,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"

configs/kmsuse2_defconfig

@@ -13,7 +13,7 @@ CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_ENV_OFFSET_REDUND=0xD0000
-CONFIG_IDENT_STRING="\nABB SUSE2"
+CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
 CONFIG_SYS_EXTRA_OPTIONS="KM_SUSE2"
 CONFIG_AUTOBOOT_KEYED=y
@@ -22,16 +22,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"

configs/pumpkin_defconfig

@@ -17,6 +17,7 @@ CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin"
 # CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -45,8 +46,13 @@ CONFIG_CMD_PART=y
 # CONFIG_CMD_SLEEP is not set
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_NET is not set
 CONFIG_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4d000000
+CONFIG_FASTBOOT_BUF_SIZE=0x4000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y
 # CONFIG_INPUT is not set
 CONFIG_DM_MMC=y
 # CONFIG_MMC_QUIRKS is not set
@@ -59,6 +65,13 @@ CONFIG_BAUDRATE=921600
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_MTK_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_MT85XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d
+CONFIG_USB_GADGET_PRODUCT_NUM=0x201c
 CONFIG_WDT=y
 CONFIG_WDT_MTK=y
 # CONFIG_EFI_LOADER is not set

configs/sandbox_defconfig

@@ -58,6 +58,7 @@ CONFIG_CMD_LSBLK=y
 CONFIG_CMD_MUX=y
 CONFIG_CMD_OSD=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_PWM=y
 CONFIG_CMD_READ=y
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_SPI=y

doc/board/freescale/imx8mm_evk.rst

@@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware
 
 Note: builddir is U-Boot build directory (source directory for in-tree builds)
 Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_4.19.35_1.0.0
+branch: imx_5.4.47_2.2.0
 
 .. code-block:: bash
 
@@ -30,10 +30,10 @@ Get the ddr firmware
 
 .. code-block:: bash
 
-   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
-   $ chmod +x firmware-imx-8.0.bin
-   $ ./firmware-imx-8.0
-   $ cp firmware-imx-8.0/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
 
 Build U-Boot
 ------------

doc/board/freescale/imx8mn_evk.rst

@@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware
 
 Note: srctree is U-Boot source directory
 Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_4.19.35_1.1.0
+branch: imx_5.4.47_2.2.0
 
 .. code-block:: bash
 
@@ -30,10 +30,10 @@ Get the ddr firmware
 
 .. code-block:: bash
 
-   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin
-   $ chmod +x firmware-imx-8.5.bin
-   $ ./firmware-imx-8.5
-   $ cp firmware-imx-8.5/firmware/ddr/synopsys/ddr4*.bin $(srctree)
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/ddr4*.bin $(srctree)
 
 Build U-Boot
 ------------

doc/board/freescale/imx8mp_evk.rst

@@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware
 
 Note: $(srctree) is the U-Boot source directory
 Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_5.4.3_2.0.0
+branch: imx_5.4.47_2.2.0
 
 .. code-block:: bash
 
@@ -30,13 +30,13 @@ Get the ddr firmware
 
 .. code-block:: bash
 
-   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin
-   $ chmod +x firmware-imx-8.7.bin
-   $ ./firmware-imx-8.7.bin
-   $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
-   $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
-   $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
-   $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9.bin
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
 
 Build U-Boot
 ------------

doc/board/freescale/imx8mq_evk.rst

@@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware
 
 Note: srctree is U-Boot source directory
 Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_4.19.35_1.0.0
+branch: imx_5.4.47_2.2.0
 
 .. code-block:: bash
 
@@ -30,11 +30,11 @@ Get the ddr and hdmi firmware
 
 .. code-block:: bash
 
-   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
-   $ chmod +x firmware-imx-7.9.bin
-   $ ./firmware-imx-7.9.bin
-   $ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
-   $ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9.bin
+   $ cp firmware-imx-8.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
 
 Build U-Boot
 ------------

drivers/clk/aspeed/Makefile

@@ -4,3 +4,4 @@
 #
 
 obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o
+obj-$(CONFIG_ASPEED_AST2600) += clk_ast2600.o

drivers/clk/mediatek/Makefile

@@ -7,5 +7,6 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o
 obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
 obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
+obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
 obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o

drivers/dma/bcm6348-iudma.c

@@ -313,10 +313,10 @@ static int bcm6348_iudma_request(struct dma *dma)
 	ch_priv->desc_id = 0;
 	if (bcm6348_iudma_chan_is_rx(dma->id)) {
 		ch_priv->desc_cnt = 0;
-		ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
+		ch_priv->busy_desc = NULL;
 	} else {
 		ch_priv->desc_cnt = ch_priv->dma_ring_size;
-		ch_priv->busy_desc = NULL;
+		ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
 	}
 
 	return 0;

drivers/mmc/fsl_esdhc_spl.c

@@ -91,20 +91,17 @@ void __noreturn mmc_boot(void)
 					CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
 	if (err != 1) {
 		puts("spl: mmc read failed!!\n");
-		free(tmp_buf);
 		hang();
 	}
 
 	val = *(tmp_buf + MBRDBR_BOOT_SIG_55);
 	if (0x55 != val) {
 		puts("spl: mmc signature is not valid!!\n");
-		free(tmp_buf);
 		hang();
 	}
 	val = *(tmp_buf + MBRDBR_BOOT_SIG_AA);
 	if (0xAA != val) {
 		puts("spl: mmc signature is not valid!!\n");
-		free(tmp_buf);
 		hang();
 	}
 

drivers/mmc/pci_mmc.c

@@ -52,9 +52,11 @@ static int pci_mmc_probe(struct udevice *dev)
 
 static int pci_mmc_of_to_plat(struct udevice *dev)
 {
-	struct pci_mmc_priv *priv = dev_get_priv(dev);
+	if (CONFIG_IS_ENABLED(DM_GPIO)) {
+		struct pci_mmc_priv *priv = dev_get_priv(dev);
 
-	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+		gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+	}
 
 	return 0;
 }

drivers/mtd/Makefile

@@ -11,7 +11,6 @@ mtd-$(CONFIG_ALTERA_QSPI) += altera_qspi.o
 mtd-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
 mtd-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
 mtd-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
-mtd-$(CONFIG_MW_EEPROM) += mw_eeprom.o
 mtd-$(CONFIG_FLASH_PIC32) += pic32_flash.o
 mtd-$(CONFIG_ST_SMI) += st_smi.o
 mtd-$(CONFIG_STM32_FLASH) += stm32_flash.o

drivers/mtd/nand/raw/Kconfig

@@ -321,6 +321,18 @@ config NAND_STM32_FMC2
 	  The controller supports a maximum 8k page size and supports
 	  a maximum 8-bit correction error per sector of 512 bytes.
 
+config CORTINA_NAND
+	bool "Support for NAND controller on Cortina-Access SoCs"
+	depends on CORTINA_PLATFORM
+	select SYS_NAND_SELF_INIT
+	select DM_MTD
+	imply CMD_NAND
+	help
+	  Enables support for NAND Flash chips on Coartina-Access SoCs platform
+	  This controller is found on Presidio/Venus SoCs.
+	  The controller supports a maximum 8k page size and supports
+	  a maximum 40-bit error correction per sector of 1024 bytes.
+
 comment "Generic NAND options"
 
 config SYS_NAND_BLOCK_SIZE

drivers/mtd/nand/raw/Makefile

@@ -69,6 +69,7 @@ obj-$(CONFIG_NAND_PLAT) += nand_plat.o
 obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
 obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
 obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
+obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
 
 else  # minimal SPL drivers
 

drivers/pinctrl/mediatek/pinctrl-mtk-common.c

@@ -615,6 +615,7 @@ static int mtk_gpiochip_register(struct udevice *parent)
 	if (!drv)
 		return -ENOENT;
 
+	ret = -ENOENT;
 	dev_for_each_subnode(node, parent)
 		if (ofnode_read_bool(node, "gpio-controller")) {
 			ret = 0;

drivers/power/pmic/Kconfig

@@ -91,6 +91,21 @@ config DM_PMIC_FAN53555
 	  The driver implements read/write operations for use with the FAN53555
 	  regulator driver and binds the regulator driver to its node.
 
+config DM_PMIC_MP5416
+	bool "Enable Driver Model for PMIC MP5416"
+	depends on DM_PMIC
+	help
+	  This config enables implementation of driver-model pmic uclass features
+	  for PMIC MP5416. The driver implements read/write operations.
+
+config SPL_DM_PMIC_MP5416
+	bool "Enable Driver Model for PMIC MP5416 in SPL stage"
+	depends on DM_PMIC
+	help
+	  This config enables implementation of driver-model pmic uclass
+	  features for PMIC MP5416. The driver implements read/write
+	  operations.
+
 config DM_PMIC_PCA9450
 	bool "Enable Driver Model for PMIC PCA9450"
 	depends on DM_PMIC

drivers/power/pmic/Makefile

@@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
 obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_MP5416) += mp5416.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o
 obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o

drivers/qe/qe.c

@@ -288,7 +288,6 @@ void u_qe_init(void)
 	struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
 
 	if (!mmc) {
-		free(addr);
 		printf("\nMMC cannot find device for ucode\n");
 	} else {
 		printf("\nMMC read: dev # %u, block # %u, count %u ...\n",

drivers/ram/aspeed/Makefile

 # SPDX-License-Identifier: GPL-2.0+
 #
-obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o
\ No newline at end of file
+obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o
+obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o

drivers/reset/Kconfig

@@ -81,6 +81,15 @@ config RESET_AST2500
 	  Say Y if you want to control reset signals of different peripherals
 	  through System Control Unit (SCU).
 
+config RESET_AST2600
+	bool "Reset controller driver for AST2600 SoCs"
+	depends on DM_RESET
+	default y if ASPEED_AST2600
+	help
+	  Support for reset controller on AST2600 SoC.
+	  Say Y if you want to control reset signals of different peripherals
+	  through System Control Unit (SCU).
+
 config RESET_ROCKCHIP
 	bool "Reset controller driver for Rockchip SoCs"
 	depends on DM_RESET && ARCH_ROCKCHIP && CLK

drivers/reset/Makefile

@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
 obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
+obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
 obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o

drivers/sysreset/sysreset_ast.c

@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/arch/wdt.h>
 #include <linux/err.h>
+#include <hang.h>
 
 static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
@@ -33,11 +34,15 @@ static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
 		return -EPROTONOSUPPORT;
 	}
 
+#if !defined(CONFIG_SPL_BUILD)
 	ret = wdt_expire_now(wdt, reset_mode);
 	if (ret) {
 		debug("Sysreset failed: %d", ret);
 		return ret;
 	}
+#else
+	hang();
+#endif
 
 	return -EINPROGRESS;
 }