1. 19 9月, 2007 1 次提交
  2. 18 9月, 2007 1 次提交
  3. 16 9月, 2007 10 次提交
  4. 14 9月, 2007 1 次提交
  5. 12 9月, 2007 1 次提交
  6. 11 9月, 2007 5 次提交
  7. 10 9月, 2007 3 次提交
  8. 09 9月, 2007 3 次提交
  9. 08 9月, 2007 2 次提交
    • G
      [PPC440SPe] PCIe environment settings for Katmai and Yucca · 6efc1fc0
      Grzegorz Bernacki 提交于
      - 'pciconfighost' is set by default in order to be able to scan bridges
      behind the primary host/PCIe
      
      - 'pciscandelay' env variable is recognized to allow for user-controlled
      delay before the PCIe bus enumeration; some peripheral devices require a
      significant delay before they can be scanned (e.g. LSI8408E); without the
      delay they are not detected
      Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com>
      6efc1fc0
    • G
      [PPC440SPe] Improve PCIe configuration space access · 7f191393
      Grzegorz Bernacki 提交于
      - correct configuration space mapping
      - correct bus numbering
      - better access to config space
      
      Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
      first device on the first bus. We now allow to configure up to 16 buses;
      also, scanning for devices behind the PCIe-PCIe bridge is supported, so
      peripheral devices farther in hierarchy can be identified.
      Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com>
      7f191393
  10. 07 9月, 2007 13 次提交