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体验新版 GitCode,发现更多精彩内容 >>
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87eb200e
编写于
9月 08, 2007
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
下载
差异文件
Merge with /home/raj/git/u-boot#440SPe_PCIe_fixes
上级
fd63d832
6efc1fc0
变更
11
隐藏空白更改
内联
并排
Showing
11 changed file
with
191 addition
and
104 deletion
+191
-104
board/amcc/katmai/init.S
board/amcc/katmai/init.S
+6
-6
board/amcc/katmai/katmai.c
board/amcc/katmai/katmai.c
+17
-4
board/amcc/yucca/init.S
board/amcc/yucca/init.S
+6
-6
board/amcc/yucca/yucca.c
board/amcc/yucca/yucca.c
+17
-4
cpu/ppc4xx/405gp_pci.c
cpu/ppc4xx/405gp_pci.c
+10
-7
cpu/ppc4xx/440spe_pcie.c
cpu/ppc4xx/440spe_pcie.c
+118
-44
cpu/ppc4xx/440spe_pcie.h
cpu/ppc4xx/440spe_pcie.h
+2
-14
cpu/ppc4xx/traps.c
cpu/ppc4xx/traps.c
+0
-6
include/common.h
include/common.h
+1
-1
include/configs/katmai.h
include/configs/katmai.h
+7
-6
include/configs/yucca.h
include/configs/yucca.h
+7
-6
未找到文件。
board/amcc/katmai/init.S
浏览文件 @
87eb200e
...
...
@@ -67,9 +67,9 @@ tlbtabA:
tlbentry
(
CFG_PCIE_MEMBASE
,
SZ_256M
,
0xB0000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE_BASE
,
SZ_16K
,
0x20000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_1
K
,
0x40000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_1
K
,
0x80000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_1
K
,
0xC0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_1
6M
,
0x40000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_1
6M
,
0x80000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_1
6M
,
0xC0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_XCFGBASE
,
SZ_1K
,
0x50000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_XCFGBASE
,
SZ_1K
,
0x90000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_XCFGBASE
,
SZ_1K
,
0xD0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
...
...
@@ -109,9 +109,9 @@ tlbtabB:
tlbentry
(
CFG_PCI_MEMBASE
,
SZ_256M
,
0x10000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE_MEMBASE
,
SZ_256M
,
0xB0000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_1
K
,
0x001
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_1
K
,
0x201
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_1
K
,
0x401
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_1
6M
,
0x000
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_1
6M
,
0x200
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_1
6M
,
0x400
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_XCFGBASE
,
SZ_1K
,
0x10000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_XCFGBASE
,
SZ_1K
,
0x30000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_XCFGBASE
,
SZ_1K
,
0x50000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
...
...
board/amcc/katmai/katmai.c
浏览文件 @
87eb200e
...
...
@@ -392,16 +392,18 @@ int katmai_pcie_card_present(int port)
static
struct
pci_controller
pcie_hose
[
3
]
=
{{
0
},{
0
},{
0
}};
void
pcie_setup_hoses
(
void
)
void
pcie_setup_hoses
(
int
busno
)
{
struct
pci_controller
*
hose
;
int
i
,
bus
;
char
*
env
;
unsigned
int
delay
;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus
=
1
;
bus
=
busno
;
for
(
i
=
0
;
i
<=
2
;
i
++
)
{
/* Check for katmai card presence */
if
(
!
katmai_pcie_card_present
(
i
))
...
...
@@ -418,8 +420,8 @@ void pcie_setup_hoses(void)
hose
=
&
pcie_hose
[
i
];
hose
->
first_busno
=
bus
;
hose
->
last_busno
=
bus
;
bus
++
;
hose
->
last_busno
=
bus
;
hose
->
current_busno
=
bus
;
/* setup mem resource */
pci_set_region
(
hose
->
regions
+
0
,
...
...
@@ -439,10 +441,21 @@ void pcie_setup_hoses(void)
*/
#else
ppc440spe_setup_pcie_rootpoint
(
hose
,
i
);
env
=
getenv
(
"pciscandelay"
);
if
(
env
!=
NULL
)
{
delay
=
simple_strtoul
(
env
,
NULL
,
10
);
if
(
delay
>
5
)
printf
(
"Warning, expect noticable delay before PCIe"
"scan due to 'pciscandelay' value!
\n
"
);
mdelay
(
delay
*
1000
);
}
/*
* Config access can only go down stream
*/
hose
->
last_busno
=
pci_hose_scan
(
hose
);
bus
=
hose
->
last_busno
+
1
;
#endif
}
}
...
...
board/amcc/yucca/init.S
浏览文件 @
87eb200e
...
...
@@ -70,9 +70,9 @@ tlbtabA:
tlbentry
(
CFG_PCIE_MEMBASE
,
SZ_256M
,
0xB0000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE_BASE
,
SZ_16K
,
0x20000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_1
K
,
0x40000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_1
K
,
0x80000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_1
K
,
0xC0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_1
6M
,
0x40000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_1
6M
,
0x80000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_1
6M
,
0xC0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_XCFGBASE
,
SZ_1K
,
0x50000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_XCFGBASE
,
SZ_1K
,
0x90000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_XCFGBASE
,
SZ_1K
,
0xD0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
...
...
@@ -112,9 +112,9 @@ tlbtabB:
tlbentry
(
CFG_PCI_MEMBASE
,
SZ_256M
,
0x10000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE_MEMBASE
,
SZ_256M
,
0xB0000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_1
K
,
0x001
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_1
K
,
0x201
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_1
K
,
0x401
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_1
6M
,
0x000
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_1
6M
,
0x200
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_1
6M
,
0x400
00000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_XCFGBASE
,
SZ_1K
,
0x10000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_XCFGBASE
,
SZ_1K
,
0x30000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_XCFGBASE
,
SZ_1K
,
0x50000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
...
...
board/amcc/yucca/yucca.c
浏览文件 @
87eb200e
...
...
@@ -846,16 +846,18 @@ void yucca_setup_pcie_fpga_endpoint(int port)
static
struct
pci_controller
pcie_hose
[
3
]
=
{{
0
},{
0
},{
0
}};
void
pcie_setup_hoses
(
void
)
void
pcie_setup_hoses
(
int
busno
)
{
struct
pci_controller
*
hose
;
int
i
,
bus
;
char
*
env
;
unsigned
int
delay
;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus
=
1
;
bus
=
busno
;
for
(
i
=
0
;
i
<=
2
;
i
++
)
{
/* Check for yucca card presence */
if
(
!
yucca_pcie_card_present
(
i
))
...
...
@@ -874,8 +876,8 @@ void pcie_setup_hoses(void)
hose
=
&
pcie_hose
[
i
];
hose
->
first_busno
=
bus
;
hose
->
last_busno
=
bus
;
bus
++
;
hose
->
last_busno
=
bus
;
hose
->
current_busno
=
bus
;
/* setup mem resource */
pci_set_region
(
hose
->
regions
+
0
,
...
...
@@ -895,10 +897,21 @@ void pcie_setup_hoses(void)
*/
#else
ppc440spe_setup_pcie_rootpoint
(
hose
,
i
);
env
=
getenv
(
"pciscandelay"
);
if
(
env
!=
NULL
)
{
delay
=
simple_strtoul
(
env
,
NULL
,
10
);
if
(
delay
>
5
)
printf
(
"Warning, expect noticable delay before PCIe"
"scan due to 'pciscandelay' value!
\n
"
);
mdelay
(
delay
*
1000
);
}
/*
* Config access can only go down stream
*/
hose
->
last_busno
=
pci_hose_scan
(
hose
);
bus
=
hose
->
last_busno
+
1
;
#endif
}
}
...
...
cpu/ppc4xx/405gp_pci.c
浏览文件 @
87eb200e
...
...
@@ -443,7 +443,7 @@ void pci_init_board(void)
static
struct
pci_controller
ppc440_hose
=
{
0
};
void
pci_440_init
(
struct
pci_controller
*
hose
)
int
pci_440_init
(
struct
pci_controller
*
hose
)
{
int
reg_num
=
0
;
...
...
@@ -459,7 +459,7 @@ void pci_440_init (struct pci_controller *hose)
if
((
strap
&
SDR0_SDSTP1_PISE_MASK
)
==
0
)
{
printf
(
"PCI: SDR0_STRP1[PISE] not set.
\n
"
);
printf
(
"PCI: Configuration aborted.
\n
"
);
return
;
return
-
1
;
}
#elif defined(CONFIG_440GP)
unsigned
long
strap
;
...
...
@@ -468,7 +468,7 @@ void pci_440_init (struct pci_controller *hose)
if
((
strap
&
CPC0_STRP1_PISE_MASK
)
==
0
)
{
printf
(
"PCI: CPC0_STRP1[PISE] not set.
\n
"
);
printf
(
"PCI: Configuration aborted.
\n
"
);
return
;
return
-
1
;
}
#endif
#endif
/* CONFIG_DISABLE_PISE_TEST */
...
...
@@ -477,7 +477,7 @@ void pci_440_init (struct pci_controller *hose)
* PCI controller init
*--------------------------------------------------------------------------*/
hose
->
first_busno
=
0
;
hose
->
last_busno
=
0
xff
;
hose
->
last_busno
=
0
;
/* PCI I/O space */
pci_set_region
(
hose
->
regions
+
reg_num
++
,
...
...
@@ -515,7 +515,7 @@ void pci_440_init (struct pci_controller *hose)
if
(
pci_pre_init
(
hose
)
==
0
)
{
printf
(
"PCI: Board-specific initialization failed.
\n
"
);
printf
(
"PCI: Configuration aborted.
\n
"
);
return
;
return
-
1
;
}
pci_register_hose
(
hose
);
...
...
@@ -578,13 +578,16 @@ void pci_440_init (struct pci_controller *hose)
#endif
hose
->
last_busno
=
pci_hose_scan
(
hose
);
}
return
hose
->
last_busno
;
}
void
pci_init_board
(
void
)
{
pci_440_init
(
&
ppc440_hose
);
int
busno
;
busno
=
pci_440_init
(
&
ppc440_hose
);
#if defined(CONFIG_440SPE)
pcie_setup_hoses
();
pcie_setup_hoses
(
busno
+
1
);
#endif
}
...
...
cpu/ppc4xx/440spe_pcie.c
浏览文件 @
87eb200e
...
...
@@ -40,73 +40,126 @@ enum {
LNKW_X8
=
0x8
};
static
inline
int
pcie_in_8
(
const
volatile
unsigned
char
__iomem
*
addr
)
static
u8
*
pcie_get_base
(
struct
pci_controller
*
hose
,
unsigned
int
devfn
)
{
int
ret
;
PCIE_IN
(
lbzx
,
ret
,
addr
);
u8
*
base
=
(
u8
*
)
hose
->
cfg_data
;
/* use local configuration space for the first bus */
if
(
PCI_BUS
(
devfn
)
==
0
)
{
if
(
hose
->
cfg_data
==
(
u8
*
)
CFG_PCIE0_CFGBASE
)
base
=
(
u8
*
)
CFG_PCIE0_XCFGBASE
;
if
(
hose
->
cfg_data
==
(
u8
*
)
CFG_PCIE1_CFGBASE
)
base
=
(
u8
*
)
CFG_PCIE1_XCFGBASE
;
if
(
hose
->
cfg_data
==
(
u8
*
)
CFG_PCIE2_CFGBASE
)
base
=
(
u8
*
)
CFG_PCIE2_XCFGBASE
;
}
return
ret
;
return
base
;
}
static
inline
int
pcie_in_le16
(
const
volatile
unsigned
short
__iomem
*
addr
)
static
void
pcie_dmer_disable
(
void
)
{
int
ret
;
PCIE_IN
(
lhbrx
,
ret
,
addr
)
return
ret
;
mtdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE0_BASE
),
mfdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE0_BASE
))
|
GPL_DMER_MASK_DISA
);
mtdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE1_BASE
),
mfdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE1_BASE
))
|
GPL_DMER_MASK_DISA
);
mtdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE2_BASE
),
mfdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE2_BASE
))
|
GPL_DMER_MASK_DISA
);
}
static
inline
unsigned
pcie_in_le32
(
const
volatile
unsigned
__iomem
*
addr
)
static
void
pcie_dmer_enable
(
void
)
{
unsigned
ret
;
PCIE_IN
(
lwbrx
,
ret
,
addr
);
return
ret
;
mtdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE0_BASE
),
mfdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE0_BASE
))
&
~
GPL_DMER_MASK_DISA
);
mtdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE1_BASE
),
mfdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE1_BASE
))
&
~
GPL_DMER_MASK_DISA
);
mtdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE2_BASE
),
mfdcr
(
DCRN_PEGPL_CFG
(
DCRN_PCIE2_BASE
))
&
~
GPL_DMER_MASK_DISA
);
}
static
int
pcie_read_config
(
struct
pci_controller
*
hose
,
unsigned
int
devfn
,
int
offset
,
int
len
,
u32
*
val
)
{
u8
*
address
;
*
val
=
0
;
/*
* Bus numbers are relative to hose->first_busno
*/
devfn
-=
PCI_BDF
(
hose
->
first_busno
,
0
,
0
);
/*
* 440SPE implements only one function per port
* NOTICE: configuration space ranges are currenlty mapped only for
* the first 16 buses, so such limit must be imposed. In case more
* buses are required the TLB settings in board/amcc/<board>/init.S
* need to be altered accordingly (one bus takes 1 MB of memory space).
*/
if
(
!
((
PCI_FUNC
(
devfn
)
==
0
)
&&
(
PCI_DEV
(
devfn
)
==
1
))
)
if
(
PCI_BUS
(
devfn
)
>=
16
)
return
0
;
devfn
=
PCI_BDF
(
0
,
0
,
0
);
/*
* Only single device/single function is supported for the primary and
* secondary buses of the 440SPe host bridge.
*/
if
((
!
((
PCI_FUNC
(
devfn
)
==
0
)
&&
(
PCI_DEV
(
devfn
)
==
0
)))
&&
((
PCI_BUS
(
devfn
)
==
0
)
||
(
PCI_BUS
(
devfn
)
==
1
)))
return
0
;
address
=
pcie_get_base
(
hose
,
devfn
);
offset
+=
devfn
<<
4
;
/*
* Reading from configuration space of non-existing device can
* generate transaction errors. For the read duration we suppress
* assertion of machine check exceptions to avoid those.
*/
pcie_dmer_disable
();
switch
(
len
)
{
case
1
:
*
val
=
pcie_
in_8
(
hose
->
cfg_data
+
offset
);
*
val
=
in_8
(
hose
->
cfg_data
+
offset
);
break
;
case
2
:
*
val
=
pcie_
in_le16
((
u16
*
)(
hose
->
cfg_data
+
offset
));
*
val
=
in_le16
((
u16
*
)(
hose
->
cfg_data
+
offset
));
break
;
default:
*
val
=
pcie_
in_le32
((
u32
*
)(
hose
->
cfg_data
+
offset
));
*
val
=
in_le32
((
u32
*
)(
hose
->
cfg_data
+
offset
));
break
;
}
pcie_dmer_enable
();
return
0
;
}
static
int
pcie_write_config
(
struct
pci_controller
*
hose
,
unsigned
int
devfn
,
int
offset
,
int
len
,
u32
val
)
{
u8
*
address
;
/*
* Bus numbers are relative to hose->first_busno
*/
devfn
-=
PCI_BDF
(
hose
->
first_busno
,
0
,
0
);
/*
*
440SPE implements only one function per port
*
Same constraints as in pcie_read_config().
*/
if
(
!
((
PCI_FUNC
(
devfn
)
==
0
)
&&
(
PCI_DEV
(
devfn
)
==
1
))
)
if
(
PCI_BUS
(
devfn
)
>=
16
)
return
0
;
devfn
=
PCI_BDF
(
0
,
0
,
0
);
if
((
!
((
PCI_FUNC
(
devfn
)
==
0
)
&&
(
PCI_DEV
(
devfn
)
==
0
)))
&&
((
PCI_BUS
(
devfn
)
==
0
)
||
(
PCI_BUS
(
devfn
)
==
1
)))
return
0
;
address
=
pcie_get_base
(
hose
,
devfn
);
offset
+=
devfn
<<
4
;
/*
* Suppress MCK exceptions, similar to pcie_read_config()
*/
pcie_dmer_disable
();
switch
(
len
)
{
case
1
:
out_8
(
hose
->
cfg_data
+
offset
,
val
);
...
...
@@ -118,6 +171,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
out_le32
((
u32
*
)(
hose
->
cfg_data
+
offset
),
val
);
break
;
}
pcie_dmer_enable
();
return
0
;
}
...
...
@@ -126,7 +182,7 @@ int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u
u32
v
;
int
rv
;
rv
=
pcie_read_config
(
hose
,
dev
,
offset
,
1
,
&
v
);
rv
=
pcie_read_config
(
hose
,
dev
,
offset
,
1
,
&
v
);
*
val
=
(
u8
)
v
;
return
rv
;
}
...
...
@@ -783,12 +839,12 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
volatile
void
*
rmbase
=
NULL
;
pci_set_ops
(
hose
,
pcie_read_config_byte
,
pcie_read_config_word
,
pcie_read_config_dword
,
pcie_write_config_byte
,
pcie_write_config_word
,
pcie_write_config_dword
);
pcie_read_config_byte
,
pcie_read_config_word
,
pcie_read_config_dword
,
pcie_write_config_byte
,
pcie_write_config_word
,
pcie_write_config_dword
);
switch
(
port
)
{
case
0
:
...
...
@@ -811,14 +867,9 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
/*
* Set bus numbers on our root port
*/
if
(
ppc440spe_revB
())
{
out_8
((
u8
*
)
mbase
+
PCI_PRIMARY_BUS
,
0
);
out_8
((
u8
*
)
mbase
+
PCI_SECONDARY_BUS
,
1
);
out_8
((
u8
*
)
mbase
+
PCI_SUBORDINATE_BUS
,
1
);
}
else
{
out_8
((
u8
*
)
mbase
+
PCI_PRIMARY_BUS
,
0
);
out_8
((
u8
*
)
mbase
+
PCI_SECONDARY_BUS
,
0
);
}
out_8
((
u8
*
)
mbase
+
PCI_PRIMARY_BUS
,
0
);
out_8
((
u8
*
)
mbase
+
PCI_SECONDARY_BUS
,
1
);
out_8
((
u8
*
)
mbase
+
PCI_SUBORDINATE_BUS
,
1
);
/*
* Set up outbound translation to hose->mem_space from PLB
...
...
@@ -875,6 +926,29 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
in_le16
((
u16
*
)(
mbase
+
PCI_COMMAND
))
|
PCI_COMMAND_IO
|
PCI_COMMAND_MEMORY
|
PCI_COMMAND_MASTER
);
printf
(
"PCIE:%d successfully set as rootpoint
\n
"
,
port
);
/* Set Device and Vendor Id */
switch
(
port
)
{
case
0
:
out_le16
(
mbase
+
0x200
,
0xaaa0
);
out_le16
(
mbase
+
0x202
,
0xbed0
);
break
;
case
1
:
out_le16
(
mbase
+
0x200
,
0xaaa1
);
out_le16
(
mbase
+
0x202
,
0xbed1
);
break
;
case
2
:
out_le16
(
mbase
+
0x200
,
0xaaa2
);
out_le16
(
mbase
+
0x202
,
0xbed2
);
break
;
default:
out_le16
(
mbase
+
0x200
,
0xaaa3
);
out_le16
(
mbase
+
0x202
,
0xbed3
);
}
/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
out_le32
(
mbase
+
0x208
,
0x06040001
);
}
int
ppc440spe_setup_pcie_endpoint
(
struct
pci_controller
*
hose
,
int
port
)
...
...
@@ -952,8 +1026,8 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
/* Enable I/O, Mem, and Busmaster cycles */
out_le16
((
u16
*
)(
mbase
+
PCI_COMMAND
),
in_le16
((
u16
*
)(
mbase
+
PCI_COMMAND
))
|
PCI_COMMAND_IO
|
PCI_COMMAND_MEMORY
|
PCI_COMMAND_MASTER
);
in_le16
((
u16
*
)(
mbase
+
PCI_COMMAND
))
|
PCI_COMMAND_IO
|
PCI_COMMAND_MEMORY
|
PCI_COMMAND_MASTER
);
out_le16
(
mbase
+
0x200
,
0xcaad
);
/* Setting vendor ID */
out_le16
(
mbase
+
0x202
,
0xfeed
);
/* Setting device ID */
attempts
=
10
;
...
...
cpu/ppc4xx/440spe_pcie.h
浏览文件 @
87eb200e
...
...
@@ -38,6 +38,7 @@
#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
#define DCRN_PEGPL_CFG(base) (base + 0x16)
/*
* System DCRs (SDRs)
...
...
@@ -161,20 +162,7 @@
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mtdcr(DCRN_SDR0_CFGDATA,data);})
#define PCIE_IN(opcode, ret, addr) \
__asm__ __volatile__( \
"sync\n" \
#opcode " %0,0,%1\n" \
"1: twi 0,%0,0\n" \
"isync\n" \
"b 3f\n" \
"2: li %0,-1\n" \
"3:\n" \
".section __ex_table,\"a\"\n" \
".balign 4\n" \
".long 1b,2b\n" \
".previous\n" \
: "=r" (ret) : "r" (addr), "m" (*addr));
#define GPL_DMER_MASK_DISA 0x02000000
int
ppc440spe_init_pcie
(
void
);
int
ppc440spe_init_pcie_rootport
(
int
port
);
...
...
cpu/ppc4xx/traps.c
浏览文件 @
87eb200e
...
...
@@ -151,12 +151,6 @@ MachineCheckException(struct pt_regs *regs)
int
uncorr_ecc
=
0
;
#endif
/* Probing PCI(E) using config cycles may cause this exception
* when a device is not present. To gracefully recover in such
* scenarios config read/write routines need to be instrumented in
* order to return via fixup handler. For examples refer to
* pcie_in_8(), pcie_in_le16() and pcie_in_le32()
*/
if
((
fixup
=
search_exception_table
(
regs
->
nip
))
!=
0
)
{
regs
->
nip
=
fixup
;
val
=
mfspr
(
MCSR
);
...
...
include/common.h
浏览文件 @
87eb200e
...
...
@@ -275,7 +275,7 @@ void pciinfo (int, int);
# endif
int
is_pci_host
(
struct
pci_controller
*
);
#if defined(CONFIG_440SPE)
void
pcie_setup_hoses
(
void
);
void
pcie_setup_hoses
(
int
busno
);
#endif
#endif
...
...
include/configs/katmai.h
浏览文件 @
87eb200e
...
...
@@ -66,11 +66,11 @@
#define CFG_PCIE_BASE 0xe0000000
/* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
#define CFG_PCIE
0_XCFGBASE 0xc00004
00
#define CFG_PCIE
1_CFGBASE 0xc0001
000
#define CFG_PCIE
1_XCFGBASE 0xc00014
00
#define CFG_PCIE
2_CFGBASE 0xc0002
000
#define CFG_PCIE2_XCFGBASE 0xc
00024
00
#define CFG_PCIE
1_CFGBASE 0xc10000
00
#define CFG_PCIE
2_CFGBASE 0xc2000
000
#define CFG_PCIE
0_XCFGBASE 0xc30000
00
#define CFG_PCIE
1_XCFGBASE 0xc3001
000
#define CFG_PCIE2_XCFGBASE 0xc
30020
00
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
...
...
@@ -201,6 +201,7 @@
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"kozio=bootm ffc60000\0" \
"pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
...
...
@@ -322,7 +323,7 @@
#define CONFIG_PCI
/* include pci support */
#define CONFIG_PCI_PNP 1
/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1
/* show pci devices on startup */
#
undef
CONFIG_PCI_CONFIG_HOST_BRIDGE
#
define
CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
/* let board init pci target */
...
...
include/configs/yucca.h
浏览文件 @
87eb200e
...
...
@@ -68,11 +68,11 @@
#define CFG_PCIE_BASE 0xe0000000
/* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
#define CFG_PCIE
0_XCFGBASE 0xc00004
00
#define CFG_PCIE
1_CFGBASE 0xc0001
000
#define CFG_PCIE
1_XCFGBASE 0xc00014
00
#define CFG_PCIE
2_CFGBASE 0xc0002
000
#define CFG_PCIE2_XCFGBASE 0xc
00024
00
#define CFG_PCIE
1_CFGBASE 0xc10000
00
#define CFG_PCIE
2_CFGBASE 0xc2000
000
#define CFG_PCIE
0_XCFGBASE 0xc30000
00
#define CFG_PCIE
1_XCFGBASE 0xc3001
000
#define CFG_PCIE2_XCFGBASE 0xc
30020
00
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
...
...
@@ -182,6 +182,7 @@
"cp.b ${fileaddr} FFFB0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
...
...
@@ -297,7 +298,7 @@
#define CONFIG_PCI
/* include pci support */
#define CONFIG_PCI_PNP 1
/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1
/* show pci devices on startup */
#
undef
CONFIG_PCI_CONFIG_HOST_BRIDGE
#
define
CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
/* let board init pci target */
...
...
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