Move USE_ARCH_MEMCPY/MEMSET options to Kconfig.

Make it "default y" for the ARMv7 architecture and make it
depend on !ARM64 && !SPL.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

PSCI implementation needs the SMC instruction to be enabled.
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.

ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and
ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here
in Kconfig too.
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
implementation in PPA firmware, but this macro naming too generic, so this
patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
which will be added in following patchs.
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

LS2080A SoC family has QBMAN ver 4.0 whereas newer
SoCs like LS2088A, LS1088A has QBMAN ver 4.1
QBMAN ver 4.0 and ver 4.1 supports dqrr size as 4 and 8 respectively.

Add support of
	to check QBMAN version based on SoC SVR
	update dqrr_size accordingly
	update code to support larger dqrr_size
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Corrected the ranges table of the IFC node.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The unit-address should be the same as the I2C address of the device.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Optimize board-specific cpo for erratum A-009942 on b4860qds,
ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb,
t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb,
t4qds, t4rdb boards.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Enable ERRATUM_A009942 workaround for B-series and T-series platforms.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This reverts commit c56ae751.

Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
Configuration Register (EVCR), Micron memories expect ALL commands to use
the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer
accepted.

Within the reverted commit, the write_evcr() function is implemented using
the spi_flash_write_common(), which is a shortcut for the
[ spi_flash_cmd_write_enable(), spi_flash_cmd_write(),
spi_flash_cmd_wait_ready() ] sequence.

Since the internal state of the Micron memory has been changed when the
spi_flash_cmd_write() function completes, the later call of the
spi_flash_cmd_wait_ready() function fails.

Indeed the SPI controller driver is not aware of the SPI protocol switch.

Further patches will fix the support of Micron QSPI memories.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
[Rebase on master, use JEDEC_MFR(info) in place of idcode0]
Signed-off-by: NJagan Teki <jagan@openedev.com>

As long as the memory mapped size specifeid in the DT is the same or
bigger than the device size, it will work. So do not force the sizes
to be identical.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

In spi_flash_scan, 'ret' is initialled to -1, but 'ret' is not always
used to store a return value, in that case, even when the function
succeed, an error (-1) will be returned.
Lets just return 0 if we hit the end of the function.
Signed-off-by: NFabien Parent <fparent@baylibre.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Move the code to read the "sram-size" property into the other code
that reads properties from the node, rather than the SF subnode.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

The Cadence QSPI controller has specified overheads for the various CS
times that are in addition to those programmed in to the Device Delay
register. The overheads are different for the delays.

In addition, the existing code does not handle the case when the delay
is less than a SCLK period.

This change accurately calculates the additional delays in Ref clocks.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.

Whilst doing so, also remove the unnecessary brackets around the
constants.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.

Whislt at it, fix the names of the "Rd Data Capture" register defs.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Show what the output clock rate actually is.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

With the existing code, when the requested SPI clock rate is near
to the lowest that can be achieved by the hardware (max divider
of the ref clock is 32), the generated clock rate is wrong.
For example, with a 50MHz ref clock, when asked for anything less
than a 1.5MHz SPI clock, the code sets up the divider to generate
25MHz.

This change fixes the calculation.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Or'ing together bit positions is clearly wrong.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

At present an invalid bus width prints a message but does not return an
error. This is the opposite of the correct behaviour. Adjust it to avoid
code bloat in the common case, and avoid hard-to-debug failure in the
uncommon case.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Unlike Linux kernel, U-Boot depends on "spi-flash" compatible to probe
m25p80 spi-nor devices. Hence, add "spi-flash" compatible string to
m25p80 node. Without this patch, flash device DT data is not parsed and
QSPI operates in unsupported mode leading to data corruption.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

It depends on qemu v2.8.0-rc3 which includes device loader property.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Despite I leave Samsung by the end of the year, I'm going to maintain DFU
in u-boot.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>

Since I leave Samsung by the end of the year, I will not have access to
OneNAND devices anymore.

Hence the custodian position has been marked as "Orphaned".
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>

Enable hush parser in Armada-7040 and Armada-8040 DB default
configurations.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Enable PCIe bus support in Armada-7040 DB default configuration
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add missing L3 cache flush functionality which absence prevents
Linux kernel from normal boot in case the L3 cache is enabled
by ATF.
The L3 cache is named the "last level" cache in order to keep
the terminology similar to the ATF code.
This cache should not be disabled by u-boot since the Linux
kernel cannot activate it, so it is activates at ATF stage.
However the cache flush is required for preventing data corruption
after disabling the MMU and the data cache before passing control
to the loaded Linux image.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Enable mvebu pin control support in the default configuration
files for Armada-7040 and Armada-8040 development boards
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Enable mvebu "bubt" command support in the default configuration
file for Armada-7040 and Armada-8040 development boards
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add pin control nodes to APN806, CP-master, CP-slave and
Armada-7040 and Armada-8040 boards DTS files
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>