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提交 fe982255 编写于 作者: T Tom Rini
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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

上级 170397f1 6c498835
展开全部 隐藏空白更改
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Showing with 2697 addition and 1857 deletion
arch/arm/Kconfig
浏览文件 @ fe982255
......@@ -829,7 +829,6 @@ config TARGET_COLIBRI_PXA270
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select BLK
select CLK_UNIPHIER
select DM
select DM_GPIO
......
arch/arm/dts/uniphier-common32.dtsi 已删除 100644 → 0
浏览文件 @ 170397f1
/*
* Device Tree Source commonly used by UniPhier ARM SoCs
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton.dtsi"
/ {
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks {
refclk: ref {
#clock-cells = <0>;
compatible = "fixed-clock";
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
};
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
u-boot,dm-pre-reloc;
mio_clk: clock {
#clock-cells = <1>;
};
mio_rst: reset {
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
#clock-cells = <1>;
};
peri_rst: reset {
#reset-cells = <1>;
};
};
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x104>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x104>;
clocks = <&arm_timer_clk>;
};
intc: interrupt-controller@60001000 {
compatible = "arm,cortex-a9-gic";
reg = <0x60001000 0x1000>,
<0x60000100 0x100>;
#interrupt-cells = <3>;
interrupt-controller;
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
/* specify compatible in each SoC DTSI */
u-boot,dm-pre-reloc;
};
};
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
sys_clk: clock {
#clock-cells = <1>;
};
sys_rst: reset {
#reset-cells = <1>;
};
};
nand: nand@68000000 {
compatible = "denali,denali-nand-dt";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
arch/arm/dts/uniphier-ld11.dtsi
浏览文件 @ fe982255
......@@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/memreserve/ 0x80000000 0x00080000;
/ {
compatible = "socionext,uniphier-ld11";
......@@ -34,31 +34,66 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
};
cluster0_opp: opp_table {
compatible = "operating-points-v2";
opp-shared;
opp@245000000 {
opp-hz = /bits/ 64 <245000000>;
clock-latency-ns = <300>;
};
opp@250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp@490000000 {
opp-hz = /bits/ 64 <490000000>;
clock-latency-ns = <300>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp@653334000 {
opp-hz = /bits/ 64 <653334000>;
clock-latency-ns = <300>;
};
opp@666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp@980000000 {
opp-hz = /bits/ 64 <980000000>;
clock-latency-ns = <300>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
timer {
......@@ -129,7 +164,7 @@
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
......@@ -142,7 +177,7 @@
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
......@@ -152,7 +187,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 6>;
clock-frequency = <400000>;
};
......@@ -165,7 +200,7 @@
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
......@@ -178,7 +213,7 @@
interrupts = <0 45 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 8>;
clock-frequency = <100000>;
};
......@@ -188,7 +223,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 9>;
clock-frequency = <400000>;
};
......@@ -207,8 +242,19 @@
reg = <0x59801000 0x400>;
};
sdctrl@59810000 {
compatible = "socionext,uniphier-ld11-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
sd_rst: reset {
compatible = "socionext,uniphier-ld11-sd-reset";
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
compatible = "socionext,uniphier-ld11-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
......@@ -223,6 +269,19 @@
};
};
emmc: sdhc@5a000000 {
compatible = "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_1v8>;
clocks = <&sys_clk 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
/* mmc-hs400-1_8v; support depends on board design */
};
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
......@@ -277,7 +336,7 @@
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-soc-glue",
compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
......@@ -305,7 +364,7 @@
sysctrl@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-ld11-clock";
......@@ -317,6 +376,18 @@
#reset-cells = <1>;
};
};
nand: nand@68000000 {
compatible = "socionext,denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
......
arch/arm/dts/uniphier-ld20.dtsi
浏览文件 @ fe982255
......@@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/memreserve/ 0x80000000 0x00080000;
/ {
compatible = "socionext,uniphier-ld20";
......@@ -43,47 +43,126 @@
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp>;
};
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp@250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp@275000000 {
opp-hz = /bits/ 64 <275000000>;
clock-latency-ns = <300>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp@550000000 {
opp-hz = /bits/ 64 <550000000>;
clock-latency-ns = <300>;
};
opp@666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp@733334000 {
opp-hz = /bits/ 64 <733334000>;
clock-latency-ns = <300>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <300>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
clock-latency-ns = <300>;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp@250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp@275000000 {
opp-hz = /bits/ 64 <275000000>;
clock-latency-ns = <300>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp@550000000 {
opp-hz = /bits/ 64 <550000000>;
clock-latency-ns = <300>;
};
opp@666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp@733334000 {
opp-hz = /bits/ 64 <733334000>;
clock-latency-ns = <300>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <300>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
clock-latency-ns = <300>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
timer {
......@@ -154,7 +233,7 @@
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
......@@ -167,7 +246,7 @@
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
......@@ -177,7 +256,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 6>;
clock-frequency = <400000>;
};
......@@ -190,7 +269,7 @@
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
......@@ -203,7 +282,7 @@
interrupts = <0 45 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 8>;
clock-frequency = <100000>;
};
......@@ -213,7 +292,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 9>;
clock-frequency = <400000>;
};
......@@ -232,24 +311,24 @@
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl",
sdctrl@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
mio_clk: clock {
compatible = "socionext,uniphier-ld20-mio-clock";
sd_clk: clock {
compatible = "socionext,uniphier-ld20-sd-clock";
#clock-cells = <1>;
};
mio_rst: reset {
compatible = "socionext,uniphier-ld20-mio-reset";
sd_rst: reset {
compatible = "socionext,uniphier-ld20-sd-reset";
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
compatible = "socionext,uniphier-ld20-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
......@@ -264,6 +343,19 @@
};
};
emmc: sdhc@5a000000 {
compatible = "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_1v8>;
clocks = <&sys_clk 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
/* mmc-hs400-1_8v; support depends on board design */
};
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
......@@ -271,14 +363,15 @@
interrupts = <0 76 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd>;
clocks = <&mio_clk 0>;
clocks = <&sd_clk 0>;
reset-names = "host";
resets = <&mio_rst 0>;
resets = <&sd_rst 0>;
bus-width = <4>;
cap-sd-highspeed;
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-soc-glue",
compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
......@@ -304,9 +397,9 @@
};
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl",
compatible = "socionext,uniphier-ld20-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-ld20-clock";
......@@ -318,6 +411,35 @@
#reset-cells = <1>;
};
};
usb: usb@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3";
reg = <0x65b00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
<&pinctrl_usb2>, <&pinctrl_usb3>;
dwc3@65a00000 {
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
tx-fifo-resize;
};
};
nand: nand@68000000 {
compatible = "socionext,denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
......
arch/arm/dts/uniphier-ld4.dtsi
浏览文件 @ fe982255
......@@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "uniphier-common32.dtsi"
/include/ "skeleton.dtsi"
/ {
compatible = "socionext,uniphier-ld4";
......@@ -25,313 +25,438 @@
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks {
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
refclk: ref {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
clock-frequency = <24576000>;
};
iobus_clk: iobus_clk {
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-frequency = <50000000>;
};
};
};
&soc {
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <(512 * 1024)>;
cache-sets = <256>;
cache-line-size = <128>;
cache-level = <2>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <(512 * 1024)>;
cache-sets = <256>;
cache-line-size = <128>;
cache-level = <2>;
};
port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <36864000>;
};
port1x: gpio@55000010 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000010 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <36864000>;
};
port2x: gpio@55000018 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000018 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <36864000>;
};
port3x: gpio@55000020 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000020 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 29 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <36864000>;
};
port4: gpio@55000028 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000028 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port5x: gpio@55000030 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000030 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port1x: gpio@55000010 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000010 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port6x: gpio@55000038 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000038 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port2x: gpio@55000018 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000018 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port7x: gpio@55000040 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000040 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port3x: gpio@55000020 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000020 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port8x: gpio@55000048 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000048 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port4: gpio@55000028 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000028 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port9x: gpio@55000050 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000050 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port5x: gpio@55000030 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000030 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port10x: gpio@55000058 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000058 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port6x: gpio@55000038 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000038 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port11x: gpio@55000060 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000060 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port7x: gpio@55000040 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000040 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port12x: gpio@55000068 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000068 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port8x: gpio@55000048 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000048 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port13x: gpio@55000070 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000070 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port9x: gpio@55000050 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000050 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port14x: gpio@55000078 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000078 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port10x: gpio@55000058 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000058 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port16x: gpio@55000088 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000088 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port11x: gpio@55000060 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000060 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
i2c0: i2c@58400000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&iobus_clk>;
clock-frequency = <100000>;
};
port12x: gpio@55000068 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000068 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
i2c1: i2c@58480000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58480000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&iobus_clk>;
clock-frequency = <100000>;
};
port13x: gpio@55000070 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000070 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
/* chip-internal connection for DMD */
i2c2: i2c@58500000 {
compatible = "socionext,uniphier-i2c";
reg = <0x58500000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&iobus_clk>;
clock-frequency = <400000>;
};
port14x: gpio@55000078 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000078 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
i2c3: i2c@58580000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58580000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&iobus_clk>;
clock-frequency = <100000>;
};
port16x: gpio@55000088 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000088 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a400000 0x200>;
interrupts = <0 76 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>;
};
i2c0: i2c@58400000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
emmc: sdhc@5a500000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a500000 0x200>;
interrupts = <0 78 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw-reset";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
bus-width = <8>;
non-removable;
};
i2c1: i2c@58480000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58480000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
};
/* chip-internal connection for DMD */
i2c2: i2c@58500000 {
compatible = "socionext,uniphier-i2c";
reg = <0x58500000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
clock-frequency = <400000>;
};
usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
};
i2c3: i2c@58580000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
reg = <0x58580000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
};
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
aidet@61830000 {
compatible = "simple-mfd", "syscon";
reg = <0x61830000 0x200>;
};
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
&refclk {
clock-frequency = <24576000>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-ld4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
&serial0 {
clock-frequency = <36864000>;
};
mio_clk: clock {
compatible = "socionext,uniphier-ld4-mio-clock";
#clock-cells = <1>;
};
&serial1 {
clock-frequency = <36864000>;
};
mio_rst: reset {
compatible = "socionext,uniphier-ld4-mio-reset";
#reset-cells = <1>;
};
};
&serial2 {
clock-frequency = <36864000>;
};
perictrl@59820000 {
compatible = "socionext,uniphier-ld4-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
&serial3 {
interrupts = <0 29 4>;
clock-frequency = <36864000>;
};
peri_clk: clock {
compatible = "socionext,uniphier-ld4-peri-clock";
#clock-cells = <1>;
};
&mio_clk {
compatible = "socionext,uniphier-ld4-mio-clock";
};
peri_rst: reset {
compatible = "socionext,uniphier-ld4-peri-reset";
#reset-cells = <1>;
};
};
&mio_rst {
compatible = "socionext,uniphier-ld4-mio-reset";
};
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a400000 0x200>;
interrupts = <0 76 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
};
&peri_clk {
compatible = "socionext,uniphier-ld4-peri-clock";
};
emmc: sdhc@5a500000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a500000 0x200>;
interrupts = <0 78 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>;
reset-names = "host", "bridge";
resets = <&mio_rst 1>, <&mio_rst 4>;
bus-width = <8>;
non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
};
&peri_rst {
compatible = "socionext,uniphier-ld4-peri-reset";
};
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
};
&pinctrl {
compatible = "socionext,uniphier-ld4-pinctrl";
};
usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
};
&sys_clk {
compatible = "socionext,uniphier-ld4-clock";
};
usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-ld4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld4-pinctrl";
u-boot,dm-pre-reloc;
};
};
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x104>;
clocks = <&arm_timer_clk>;
};
&sys_rst {
compatible = "socionext,uniphier-ld4-reset";
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x104>;
clocks = <&arm_timer_clk>;
};
intc: interrupt-controller@60001000 {
compatible = "arm,cortex-a9-gic";
reg = <0x60001000 0x1000>,
<0x60000100 0x100>;
#interrupt-cells = <3>;
interrupt-controller;
};
aidet@61830000 {
compatible = "simple-mfd", "syscon";
reg = <0x61830000 0x200>;
};
sysctrl@61840000 {
compatible = "socionext,uniphier-ld4-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-ld4-clock";
#clock-cells = <1>;
};
sys_rst: reset {
compatible = "socionext,uniphier-ld4-reset";
#reset-cells = <1>;
};
};
nand: nand@68000000 {
compatible = "socionext,denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
arch/arm/dts/uniphier-pro4-ref.dts
浏览文件 @ fe982255
......@@ -68,15 +68,19 @@
status = "okay";
};
&usb0 {
&usb2 {
status = "okay";
};
&usb2 {
&usb3 {
status = "okay";
};
&usb3 {
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
......
arch/arm/dts/uniphier-pro4.dtsi
浏览文件 @ fe982255
此差异已折叠。
arch/arm/dts/uniphier-pro5.dtsi
浏览文件 @ fe982255
此差异已折叠。
arch/arm/dts/uniphier-pxs2-gentil.dts
浏览文件 @ fe982255
......@@ -71,7 +71,7 @@
u-boot,dm-pre-reloc;
};
&mio_clk {
&sd_clk {
u-boot,dm-pre-reloc;
};
......
arch/arm/dts/uniphier-pxs2-vodka.dts
浏览文件 @ fe982255
......@@ -55,7 +55,7 @@
u-boot,dm-pre-reloc;
};
&mio_clk {
&sd_clk {
u-boot,dm-pre-reloc;
};
......
arch/arm/dts/uniphier-pxs2.dtsi
浏览文件 @ fe982255
此差异已折叠。
arch/arm/dts/uniphier-sld3.dtsi
浏览文件 @ fe982255
......@@ -50,12 +50,6 @@
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
iobus_clk: iobus_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
};
soc {
......@@ -251,7 +245,7 @@
interrupts = <0 41 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
......@@ -262,7 +256,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 1>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
......@@ -273,7 +267,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 1>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
......@@ -284,7 +278,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 1>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <100000>;
};
......@@ -295,7 +289,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 1>;
clocks = <&iobus_clk>;
clocks = <&sys_clk 1>;
clock-frequency = <400000>;
};
......@@ -339,9 +333,12 @@
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>;
reset-names = "host", "bridge";
resets = <&mio_rst 1>, <&mio_rst 4>;
bus-width = <8>;
non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
};
sd: sdhc@5a500000 {
......@@ -353,8 +350,13 @@
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
};
usb0: usb@5a800100 {
......@@ -406,7 +408,8 @@
};
soc-glue@5f800000 {
compatible = "simple-mfd", "syscon";
compatible = "socionext,uniphier-sld3-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
......@@ -422,7 +425,7 @@
};
sysctrl@f1840000 {
compatible = "socionext,uniphier-sysctrl",
compatible = "socionext,uniphier-sld3-sysctrl",
"simple-mfd", "syscon";
reg = <0xf1840000 0x4000>;
......@@ -438,9 +441,13 @@
};
nand: nand@f8000000 {
compatible = "denali,denali-nand-dt";
reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
compatible = "socionext,denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
interrupts = <0 65 4>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
......
arch/arm/dts/uniphier-sld8.dtsi
浏览文件 @ fe982255
此差异已折叠。
arch/arm/mach-uniphier/dram/umc-ld20.c
浏览文件 @ fe982255
/*
* Copyright (C) 2016 Socionext Inc.
*
* based on commit a7a36122aa072fe1bb06e02b73b3634b7a6c555a of Diag
* based on commit 5e1cb0f1caeabc6c99469dd997cb6b4f46834443 of Diag
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -264,8 +264,8 @@ static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
unsigned int bit)
{
WARN_ON(lane >= (1 << PHY_LANE_SEL_LANE_WIDTH));
WARN_ON(bit >= (1 << PHY_LANE_SEL_BIT_WIDTH));
WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH);
WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH);
writel((bit << PHY_LANE_SEL_BIT_SHIFT) |
(lane << PHY_LANE_SEL_LANE_SHIFT),
......
arch/arm/mach-uniphier/memconf/memconf.c
浏览文件 @ fe982255
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -14,7 +16,7 @@
int memconf_init(const struct uniphier_board_data *bd)
{
u32 tmp = 0;
u32 tmp;
unsigned long size_per_word;
tmp = readl(SG_MEMCONF);
......
configs/uniphier_ld11_defconfig
浏览文件 @ fe982255
......@@ -6,6 +6,7 @@ CONFIG_ARCH_UNIPHIER_LD11=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
......
configs/uniphier_ld20_defconfig
浏览文件 @ fe982255
......@@ -6,6 +6,7 @@ CONFIG_ARCH_UNIPHIER_LD20=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
......
configs/uniphier_ld4_sld8_defconfig
浏览文件 @ fe982255
......@@ -8,6 +8,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
......
configs/uniphier_pro4_defconfig
浏览文件 @ fe982255
......@@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
......
configs/uniphier_pxs2_ld6b_defconfig
浏览文件 @ fe982255
......@@ -8,6 +8,7 @@ CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
......
configs/uniphier_sld3_defconfig
浏览文件 @ fe982255
......@@ -8,6 +8,7 @@ CONFIG_ARCH_UNIPHIER_SLD3=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
......
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