DRAM region 0x3f000000 - 0x3fffffff is reserved for OP-TEE. Touching
0x3f000000 memory location from unsecure world causes the board
to hang.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Use DM for the pl01x serial driver on hikey. Also allow UART0 or
UART3 to be chosen via Kconfig.

By default we now output to UART3 as the latest version of ATF outputs
to this UART. Also UART3 comes out on the LS connector, as opposed to
UART0 which goes to a unpopulated header.

As part of this change we also enable CONFIG_BOARD_EARLY_INIT_F and
call the pinmux configuration code for the UART. Before we were
relying on ATF having already configured the pin configuration.

NB: Upstream Linux kernel doesn't yet support UART3, so serial console
will still be output on UART0 when booting a upstream kernel.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Most platforms enable these options from Kconfig rather
than the configs header file.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This causes exceptions and other strange behaviour
when enabling CONFIG_SYS_MALLOC_F_LEN which is required to
migrate the serial driver over to DM_SERIAL.

As GD_FLG_FULL_MALLOC_INIT flag gets reset, after relocation
we don't end up using the full malloc which ultimately ends up
causing a synchronus abort.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Use the #defines in linux/sizes for malloc size as it is
more readable.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Rather than relying on an external URL in the README
include the Makefile in the hikey directory.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>

The README had a few mistakes, and one of the URL's
had changed. Also update the boot log with the latest
boot trace from ATF, which now includes the mcuimage.bin.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>

The gd->malloc_ptr and the gd->malloc_limit are offsets to gd->malloc_base.
But the addr variable contains the absolute address. The new_ptr must be:
addr + bytes - gd->malloc_base.
Signed-off-by: NPhilipp Rosenberger <ilu@linutronix.de>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>

When AM437x EVM is connected to Gigabit switch, it takes
more time to finish auto-negotiation than on a 10/100 switch.

The default 4 second limit times-out more often than not. This is
observed when testing with a D-Link DGS-1008A desktop switch.

Increase the auto-negotiation time-out for AM437x EVM to handle
this case.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Fix typo in CONFIG_FIT description - remove the accidentially added
redundand 'the'.
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The config option has been removed by one of the syncs with the Linux
mainline MTD subsystem:
ff94bc40 (mtd, ubi, ubifs: resync with Linux-3.14)
It has been left inside the config files. Currently does not look to
serve any purpose, so remove it now from all the configs.
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Cc: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: NStefan Roese <sr@denx.de>

Some boards' defconfigs are disordered. Reorder them.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, the USB boot mode is supported by an external loader and
U-boot proper image is put on the section 0.  This commit allows
access there.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, console=ttyS0 is hard-coded in CONFIG_EXTRA_ENV_SETTINGS
and it replaces the bootargs in the chosen node of the device tree
passed to the kernel.  This is not preferable because I am going to
add some boards whose console is not ttyS0.

Drop bootargs settings from U-Boot's environment and use the one in
device tree by default.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Move init code of low-level debug into a single file.
This is helpful to create an image that runs on multiple SoCs.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, IECTRL is enabled after pin-mux settings for the low-level
debugging for PH1-LD4 and PH1-sLD8.  While IECTRL is disabled, input
signals are pulled-down, i.e. glitch signal (Low to High transition)
problem occurs if pin-mux is set up first.  As a result, one invalid
character is input to the UART block and the auto-boot counting is
terminated immediately.

The correct initialization procedure is:
 [1] Enable IECTRL (if IECTRL exists for the pins)
 [2] Set up pin-muxing
 [3] Deassert the reset of the hardware block

Currently, the low-level debugging is working for PH1-sLD3 and
PH1-Pro4, but just in case, follow the sequence for all the SoCs.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The UART I/O ports for PH1-Pro4 has no input enable controlling.
This code is useless.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify
they belong to UniPhier SoC family.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Without this, build fails if CONFIG_MICRO_SUPPORT_CARD is disabled.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally.
Move them to a C file as local macros.  Also, rename the C file.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The macro, led_write(), is now only used in C sources.  There is no
more reason to keep the tricky assembly macro.  Replace it with a
new C function led_puts().

Also, rename board.h to micro-support-card.h.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The wrapper functions, uniphier_board_*, are just making function
calls complex.  Remove them.

Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD
is disabled, so that prototype checking works.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This has been unused since commit f4e190e3 ("ARM: uniphier:
enable SPL_OF_CONTROL").
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Device tree specifies the available memory ranges in its "/memory"
node.  Use it to simplify the CONFIG defines.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

To achieve the complete run-time configuration by device trees, ifdef
conditionals in header files are not preferable.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
 0x00000000 - 0x0fffffff
 0x40000000 - 0x4fffffff
are both mapped to the external bus (also called system bus),
so either was OK.

In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is
assigned for the serial NOR interface.

Going forward, use the latter for the external bus.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This command will be used in the next commit to calculate
base-offseted addresses.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Historically (for compatibility with very old platforms), two
different types of micro support cards have been used with the
UniPhier SoC development boards.  It has been painful to maintain
both.  Having one of them is enough.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

These input enable settings are handled by the pinctrl drivers.

Because the external bus pins are input-enabled by default, on-board
devices such as LED still work fine even with this delayed input
enabling.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

As the UniPhier serial driver had already switched to Drive Model
and the pinctrl drivers are now enabled, these pin-muxing settings
are properly handled by the pinctrl drivers.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Now, UniPhier SoCs are ready to enable pinctrl drivers.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add "u-boot,dm-pre-reloc" for device nodes we want in SPL DTB
(spl/u-boot-spl.dtb).

The "soc" node (this is simple-bus node) also needs the property
to bind the pinctrl node located under it.

I am collecting this U-Boot specific hack to the bottom of board
DTS rather than inserting "u-boot,dm-pre-reloc" into SoC DTSI.
My goal is to sync DTSI with Linux for easier maintenance.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>