mpc8313erdb.dts 6.1 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11
/*
 * MPC8313E RDB Device Tree Source
 *
 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

12 13
/dts-v1/;

14 15
/ {
	model = "MPC8313ERDB";
16
	compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
17 18 19
	#address-cells = <1>;
	#size-cells = <1>;

20 21 22 23 24 25 26 27
	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

28 29 30 31 32 33
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8313@0 {
			device_type = "cpu";
34 35 36 37 38
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <16384>;
			i-cache-size = <16384>;
39 40 41 42 43 44 45 46
			timebase-frequency = <0>;	// from bootloader
			bus-frequency = <0>;		// from bootloader
			clock-frequency = <0>;		// from bootloader
		};
	};

	memory {
		device_type = "memory";
47
		reg = <0x00000000 0x08000000>;	// 128MB at 0
48 49
	};

50 51 52 53
	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
54 55
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
56 57 58 59 60
		interrupt-parent = <&ipic>;

		// CS0 and CS1 are swapped when
		// booting from nand, but the
		// addresses are the same.
61 62 63 64
		ranges = <0x0 0x0 0xfe000000 0x00800000
		          0x1 0x0 0xe2800000 0x00008000
		          0x2 0x0 0xf0000000 0x00020000
		          0x3 0x0 0xfa000000 0x00008000>;
65

66 67 68 69
		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
70
			reg = <0x0 0x0 0x800000>;
71 72 73 74
			bank-width = <2>;
			device-width = <1>;
		};

75 76 77 78 79
		nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8313-fcm-nand",
			             "fsl,elbc-fcm-nand";
80
			reg = <0x1 0x0 0x2000>;
81 82

			u-boot@0 {
83
				reg = <0x0 0x100000>;
84 85 86 87
				read-only;
			};

			kernel@100000 {
88
				reg = <0x100000 0x300000>;
89 90 91
			};

			fs@400000 {
92
				reg = <0x400000 0x1c00000>;
93 94 95 96
			};
		};
	};

97 98 99 100
	soc8313@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
101
		compatible = "simple-bus";
102 103
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
104 105 106 107 108
		bus-frequency = <0>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
109
			reg = <0x200 0x100>;
110 111 112
		};

		i2c@3000 {
113 114 115
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
116
			compatible = "fsl-i2c";
117 118 119
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
120 121 122 123
			dfsrr;
		};

		i2c@3100 {
124 125 126
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
127
			compatible = "fsl-i2c";
128 129 130
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
131 132 133 134
			dfsrr;
		};

		spi@7000 {
135 136
			cell-index = <0>;
			compatible = "fsl,spi";
137 138 139
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
140
			mode = "cpu";
141 142 143 144 145
		};

		/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
		usb@23000 {
			compatible = "fsl-usb2-dr";
146
			reg = <0x23000 0x1000>;
147 148
			#address-cells = <1>;
			#size-cells = <0>;
149 150
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
151 152 153 154 155 156
			phy_type = "utmi_wide";
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
157
			compatible = "fsl,gianfar-mdio";
158
			reg = <0x24520 0x20>;
159
			phy1: ethernet-phy@1 {
160 161 162
				interrupt-parent = <&ipic>;
				interrupts = <19 0x8>;
				reg = <0x1>;
163 164
				device_type = "ethernet-phy";
			};
165
			phy4: ethernet-phy@4 {
166 167 168
				interrupt-parent = <&ipic>;
				interrupts = <20 0x8>;
				reg = <0x4>;
169 170 171 172
				device_type = "ethernet-phy";
			};
		};

173 174
		enet0: ethernet@24000 {
			cell-index = <0>;
175 176 177
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
178
			reg = <0x24000 0x1000>;
179
			local-mac-address = [ 00 00 00 00 00 00 ];
180 181
			interrupts = <37 0x8 36 0x8 35 0x8>;
			interrupt-parent = <&ipic>;
182
			phy-handle = < &phy1 >;
183 184
		};

185 186
		enet1: ethernet@25000 {
			cell-index = <1>;
187 188 189
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
190
			reg = <0x25000 0x1000>;
191
			local-mac-address = [ 00 00 00 00 00 00 ];
192 193
			interrupts = <34 0x8 33 0x8 32 0x8>;
			interrupt-parent = <&ipic>;
194
			phy-handle = < &phy4 >;
195 196
		};

197 198
		serial0: serial@4500 {
			cell-index = <0>;
199 200
			device_type = "serial";
			compatible = "ns16550";
201
			reg = <0x4500 0x100>;
202
			clock-frequency = <0>;
203 204
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
205 206
		};

207 208
		serial1: serial@4600 {
			cell-index = <1>;
209 210
			device_type = "serial";
			compatible = "ns16550";
211
			reg = <0x4600 0x100>;
212
			clock-frequency = <0>;
213 214
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
215 216 217 218 219 220
		};

		crypto@30000 {
			device_type = "crypto";
			model = "SEC2";
			compatible = "talitos";
221 222 223
			reg = <0x30000 0x7000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
224 225
			/* Rev. 2.2 */
			num-channels = <1>;
226 227 228
			channel-fifo-len = <24>;
			exec-units-mask = <0x0000004c>;
			descriptor-types-mask = <0x0122003f>;
229 230 231 232 233 234 235 236
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
237
		ipic: pic@700 {
238 239 240
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
241
			reg = <0x700 0x100>;
242 243 244
			device_type = "ipic";
		};
	};
245

246 247
	pci0: pci@e0008500 {
		cell-index = <1>;
248
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
249 250 251
		interrupt-map = <

				/* IDSEL 0x0E -mini PCI */
252 253 254 255
				 0x7000 0x0 0x0 0x1 &ipic 18 0x8
				 0x7000 0x0 0x0 0x2 &ipic 18 0x8
				 0x7000 0x0 0x0 0x3 &ipic 18 0x8
				 0x7000 0x0 0x0 0x4 &ipic 18 0x8
256 257

				/* IDSEL 0x0F - PCI slot */
258 259 260 261 262 263 264 265 266 267 268
				 0x7800 0x0 0x0 0x1 &ipic 17 0x8
				 0x7800 0x0 0x0 0x2 &ipic 18 0x8
				 0x7800 0x0 0x0 0x3 &ipic 17 0x8
				 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		clock-frequency = <66666666>;
269 270 271
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
272
		reg = <0xe0008500 0x100>;
273 274 275
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};
276
};