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  1. 11 3月, 2008 1 次提交
  3. 07 3月, 2008 1 次提交
  5. 21 2月, 2008 1 次提交
  7. 07 2月, 2008 1 次提交
  9. 06 2月, 2008 3 次提交
    • J
      [POWERPC] arch/powerpc/sysdev: Add missing of_node_put · b1725c93
      由 Julia Lawall 提交于 
      The functions of_find_compatible_node and of_find_node_by_type both
call of_node_get on their result.  So any error handling code
thereafter should call of_node_put(np).  This is taken care of in the
case where there is a goto out, but not when there is a direct return.

The function irq_alloc_host puts np into the returned structure, which is
stored in the global variable mpc8xx_pic_host, so the reference count
should be set for the lifetime of that variable.  The current solution ups
the reference count again in the argument to irq_alloc_host so that it can
be decremented on the way out.  This seems a bit unnecessary, and also
doesn't work in the case where irq_alloc_host fails, because then the
reference count only goes does by one, whereas it should go down by two.  A
better solution is to not increment the reference count in the argument to
irq_alloc_host and only decrement it on the way out in an error case.

The problem was found using the following semantic match.
(http://www.emn.fr/x-info/coccinelle/)

// <smpl>
@@
type T,T1,T2;
identifier E;
statement S;
expression x1,x2,x3;
int ret;
@@

  T E;
  ...
* E = \(of_get_parent\|of_find_compatible_node\)(...);
  if (E == NULL) S
  ... when != of_node_put(...,(T1)E,...)
      when != if (E != NULL) { ... of_node_put(...,(T1)E,...); ...}
      when != x1 = (T1)E
      when != E = x3;
      when any
  if (...) {
    ... when != of_node_put(...,(T2)E,...)
        when != if (E != NULL) { ... of_node_put(...,(T2)E,...); ...}
        when != x2 = (T2)E
(
*   return;
|
*   return ret;
)
  }
// </smpl>
Signed-off-by: NJulia Lawall <julia@diku.dk>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Kumar Gala <galak@gate.crashing.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      b1725c93
    • A
      [POWERPC] qe_lib: fix few fluffy negligences · d8985fd2
      由 Anton Vorontsov 提交于 
      One is intoduced by me (of_node_put() absence) and another was
present already (not checking for NULL).

Found by Stephen Rothwell.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      d8985fd2
    • K
      [POWERPC] FSL: fix mpc83xx_spi device registration · dc4e4207
      由 Kim Phillips 提交于 
      calling platform_device_register after platform_device_alloc causes
this:

kobject (c3841a70): tried to init an initialized object, something is seriously wrong.
Call Trace:
[c381fe20] [c0007bb8] show_stack+0x3c/0x194 (unreliable)
[c381fe50] [c01322a8] kobject_init+0xb8/0xbc
[c381fe60] [c01591cc] device_initialize+0x30/0x9c
[c381fe80] [c015ee34] platform_device_register+0x1c/0x34
[c381fea0] [c02f1fe0] of_fsl_spi_probe+0x21c/0x22c
[c381ff30] [c02f2044] fsl_spi_init+0x54/0x160
[c381ff60] [c02f3924] __machine_initcall_mpc832x_rdb_mpc832x_spi_init+0x120/0x138
[c381ff70] [c02e61b4] kernel_init+0x98/0x284
[c381fff0] [c000f740] kernel_thread+0x44/0x60

fixed by calling platform_device_add (second half of
platform_device_register) instead.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      dc4e4207
  11. 28 1月, 2008 8 次提交
  13. 27 1月, 2008 1 次提交
  15. 26 1月, 2008 1 次提交
  17. 25 1月, 2008 2 次提交
  19. 24 1月, 2008 10 次提交
  21. 17 1月, 2008 1 次提交
  23. 09 1月, 2008 1 次提交
  25. 08 1月, 2008 1 次提交
  27. 28 12月, 2007 2 次提交
    • O
      [POWERPC] pasemi: Distribute interrupts evenly across cpus · d87bf3be
      由 Olof Johansson 提交于 
      By default the OpenPIC on PWRficient will bias to one core (since that
will improve changes of the other core being able to stay idle/powered
down). However, this conflicts with most irq load balancing schemes,
since setting an interrupt to be delivered to either core doesn't really
result in the load being shared. It also doesn't work well with the
soft irq disable feature of PPC, since EE will stay on until the first
interrupt is taken while soft disabled.

Set the gconf0 config bit that enables even distribution of interrupts
among the two cores.
Signed-off-by: NOlof Johansson <olof@lixom.net>
      d87bf3be
    • O
      [POWERPC] pasemi: Implement NMI support · f365355e
      由 Olof Johansson 提交于 
      Some PWRficient-based boards have a NMI button that's wired up to a GPIO
as interrupt source. By configuring the openpic accordingly, these get
delivered as a machine check with high priority, instead of as an external
interrupt.

The device tree contains a property "nmi-source" in the openpic node
for these systems, and it's the (hwirq) source for the input.

Also, for these interrupts, the IACK is read from another register than
the regular (MCACK instead), but they are EOI'd as usual. So implement
said function for the mpic driver.

Finally, move a couple of external function defines to include/ instead
of local under sysdev. Being able to mask/unmask and eoi directly saves
us from setting up a dummy irq handler that will never be called.
Signed-off-by: NOlof Johansson <olof@lixom.net>
      f365355e
  29. 24 12月, 2007 6 次提交
    • S
      [POWERPC] 4xx: Set ibpre for 405EX in 4xx PCIe driver · 55aaf6ec
      由 Stefan Roese 提交于 
      This patch sets the ibpre flag (Inbound Presence) for the 405EX
in the 4xx PCIe driver.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      55aaf6ec
    • V
      [POWERPC] 4xx: rework UIC cascade irq handling · 5aac48dc
      由 Valentine Barshak 提交于 
      This is a UIC cascade handler rework to use set_irq_chained_handler() for
cascade, just like othe ppc platforms do. With current implementation we have
additional redirection for irq handler and we call generic_handle_irq twice
(once for the primary uic and the other time for handling cascade interrupt).
This causes Ingo's realtime support patch to stop working on 4xx.

Not sure of any other possible problems though, but with
set_irq_chained_handler() we can abolish "struct irqaction cascade" from the
chip descriptor and call generic_handle_irq() once, directly for cascade irq.
Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      5aac48dc
    • V
      [POWERPC] 4xx: make UIC use generic level irq handler · c8090563
      由 Valentine Barshak 提交于 
      This patch makes PowerPC 4xx UIC use generic level irq handler instead
of a custom handle_uic_irq() function. We ack only edge irqs in mask_ack
callback, since acking a level irq on UIC has no effect if the interrupt
is still asserted by the device, even if the interrupt is already masked.
So, to really de-assert the interrupt we need to de-assert the external
source first *and* ack it on UIC then. The handle_level_irq() function
masks and ack's the interrupt with mask_ack callback prior to calling
the actual ISR and unmasks it at the end. So, to use it with UIC interrupts
we need to ack level irqs in the unmask callback instead, after the ISR
has de-asserted the external interrupt source. Even if we ack the interrupt
that we didn't handle (unmask/ack it at the end of the handler, while
next irq is already pending) it will not de-assert the irq, untill we
de-assert its exteral source.
Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      c8090563
    • S
      [POWERPC] 4xx: Add 440SPe revA runtime detection to PCIe · accf5ef2
      由 Stefan Roese 提交于 
      This patch adds runtime detection of the 440SPe revision A chips. These
chips are equipped with a slighly different PCIe core and need special/
different initialization. The compatible node is changed to
"plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that
can be equipped with both PPC revisions like the AMCC Yucca.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      accf5ef2
    • B
      [POWERPC] 4xx: PCI-E Link setup improvements · 035ee428
      由 Benjamin Herrenschmidt 提交于 
      This improves the way the 4xx PCI-E code handles checking for a link
and adds explicit testing of CRS result codes on config space accesses.

This should make it more reliable.

Also, bridges with no link are now still created, though config space
accesses beyond the root complex are filtered. This is one step toward
eventually supporting hotplug.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      035ee428
    • B
      [POWERPC] 4xx: PLB to PCI Express support · a2d2e1ec
      由 Benjamin Herrenschmidt 提交于 
      This adds to the previous 2 patches the support for the 4xx PCI Express
cells as found in the 440SPe revA, revB and 405EX.

Unfortunately, due to significant differences between these, and other
interesting "features" of those pieces of HW, the code isn't as simple
as it is for PCI and PCI-X and some of the functions differ significantly
between the 3 implementations. Thus, not only this code can only support
those 3 implementations for now and will refuse to operate on any other,
but there are added ifdef's to avoid the bloat of building a fairly large
amount of code on platforms that don't need it.

Also, this code currently only supports fully initializing root complex
nodes, not endpoint. Some more code will have to be lifted from the
arch/ppc implementation to add the endpoint support, though it's mostly
differences in memory mapping, and the question on how to represent
endpoint mode PCI in the device-tree is thus open.

Many thanks to Stefan Roese for testing & fixing up the 405EX bits !
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      a2d2e1ec