The NVIDIA bootloader, nvtboot, expects the "chosen" node to be present
in the device-tree blob and if it is not then it fails to boot the kernel.
Add the chosen node so we can boot the kernel on Tegra132 Norrin with the
nvtboot bootloader.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Norrin is a Tegra132-based FFD used as reference platform within NVIDIA.

Based on work by Allen Martin <amartin@nvidia.com>

Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the device-tree node for the GK20A GPU and leave it disabled.
It is the responsibility of the bootloader to enable it if the
VPR registers have been programmed such that the GPU can operate.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>

The VDD_LED supply's output is a fixed 3.3 V. Record that in the min-
and max-microvolt properties.
Signed-off-by: NThierry Reding <treding@nvidia.com>

eMMC is soldered on to the board, and as such isn't removable. Mark it
as non-removable so that operating systems can treat it appropriately.
Signed-off-by: NThierry Reding <treding@nvidia.com>

There are general changes pending to make the /aliases/serial* entries
number the serial ports on the system. On Tegra, so far the ports have
been just numbered dynamically as they are configured so that makes them
change.

To avoid this, add specific aliases per board to keep the old numbers.
This allows us to change the numbering by default on future SoCs while
keeping the numbering on existing boards.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The defined mechanism for programming the Tegra pinmux is to perform all
of the following at once in order, before using any I/O controller that
is affected by the pinmux:

- Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit.
- Set up any GPIO pins to their "initial" state.
- Program all pinmux settings in one go.

Other methods such as:

- Not setting CLAMP_INPUTS_WHEN_TRISTATED.
- Not setting GPIOs to their "initial" state before programming the
  pinmux settings of the related pin, in particular the mux function.
- Not programming the entire pinmux at once, in order to avoid
  possible conflicting settings.

... are not qualified or supported by NVIDIA ASIC/syseng. They could
cause glitches or undesired output levels on some pins, or controller
malfunction.

While we've been getting away with doing something different on many
Tegra boards without issue, I believe we've just been getting lucky.
I'd like to switch all Tegra124 systems to the correct scheme now so
they provide the right example to follow, and require that any new
boards we support upstream work in the same fashion.

While it would be nice to update boards containing older SoCs for
consistency, I don't anticipate doing so. It's too much churn to change
at this time. At least with all Tegra124 boards converted, the most
recent boards provide the correct example.

Since the bootloader needs to reprogram the pinmux to access certain
peripherals, it must program the entire pinmux due to the supported
rules above. As such, there is no need to program any part of the pinmux
from the kernel, unless dynamic pinmuxing is used. Given this, we couuld
simply remove the pinmux "default" state from the DT entirely. However,
some bootloaders parse the DT to perform their initial pinmux setup, so
it's useful to keep the pinmux data in DT. To allow this while avoiding
redundant work in the kernel, rename the "default" state to "boot". The
kernel won't apply this, but bootloaders can still look for this state
name and apply it. Note however that the DT provides zero information
about the required initial GPIO setup, so bootloaders using this approach
are not likely to operate correctly without an additional GPIO
initialization table somewhere. Previous discussions on the DT mailing
list have rejected adding such a table to DT...

The following U-Boot commits fully initialize the pinmux:

Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1
Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates
Both are part of U-Boot v2014.07 and later.

Without those commits, the only fallout I see from this change is that
HDMI on Venice2 no longer works. Given the very small user-base of this
platform, I feel that requiring a bootloader update is reasonable.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

These labels will be used by other boards in addition to Venice2, move
them to tegra124.dtsi so they are defined in a common place.
Signed-off-by: NDylan Reid <dgreid@chromium.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Venice2 contains an Atmel MXT touchpad. Add an I2C node for it to DT.
The Linux driver doesn't quite work on this platform yet, but adding
the DT node causes no issues, and will allow the device to work once
the driver is fixed.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The property for enabling external rail control on the AS3722 is
ams,ext-control, not ams,external-control. Since the external rail
control property was previously being ignored, LP1 suspend on these
boards wasn't actually turning the CPU rail off at all.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Turn on the HDA controller in Venice2, it is used for HDMI audio.
Signed-off-by: NDylan Reid <dgreid@chromium.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This adds the EC i2c tunnel (and devices under it) to the
tegra124-venice2 device tree.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NAndrew Bresticker <abrestic@chromium.org>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Venice2 can detect write-protect on the SD card. Add the required
DT entries to allow this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
[swarren: fixed GPIO polarity per Thierry's testing]
Tested-by: NThierry Reding <treding@nvidia.com>

Add HDMI +5V, VDD and PLL regulators and enable the DDC I2C controller.
Enable the HDMI device, provide the power supplies as well as the DDC
adapter and use the standard pin (PN7) for hotplug detection.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

VDDIO_SDMMC3 is the VQMMC (I/O) supply, not the VMMC (core) supply,
for the SD slot on Venice2.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This regulator supplies power to pretty much everything on the board, so
it doesn't make sense to allow it to turn off. Mark it boot-on and
always-on so it doesn't get turned off. Without this, I see issues with
the eMMC device; it can't be correctly detected during boot.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Neither Tegra114 nor Tegra124 allow "low power mode" to be configured
on SDIO1 or SDIO3 drive groups. Remove the attempt to configure that
option from the Dalmore and Venice2 DTs.

The Venice2 DT contained duplicate configurations for most sdmmc1_*
pins. Remove the duplicate pins from one of the nodes, and fix the
configuration since the remaining clk pin is output-only.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Tegra124 can support 4GB of RAM. With that much RAM (plus some memory-
mapped IO peripherals), more than 32-bits of physical address space is
required. Hence, convert all Tegra124 DTs to use 2 DT cells for address
space.

(I think this was suggested by Olof Johansson, but I'm not 100% sure)
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Device tree node name should reflect the kind of device rather than the
specific name of the device.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Equal signs should always be preceded and followed by a single space in
device tree files.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

USB1 and USB3 are routed to two external connectors, while USB2 is used
for the integrated webcam.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Venice2 has a 12.9" (2560x1700) panel connected to the eDP output of the
Tegra124. The panel has an EDID to describe the video timings but needs
a few extra nodes to get the backlight to come up.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The SDMMC3 interface is supplied with 1.8V by the PMICs LDO6.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Some of the regulators and the relationships to other regulators are
wrong. This commit attempts to rectify this by making them more similar
to what the schematics contain. This starts by adding a +VDD_MUX supply
that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS
supplies from that. The majority of the other regulators derive from one
of those three.

While at it, rename the regulators to match the names in the schematics
to make them easier to match up.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Both USB_VBUS_EN0 and USB_VBUS_EN1 are configured the same way, so they
can be combined into a single node. While at it, don't configure them as
pull-up since they already have external pull-ups. Also U-Boot doesn't
configure them as pull-up either.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Venice2 contains an SPI Flash chip, which contains the bootloader.
Add this to the DT, so the kernel can access it.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add system-power-controller property to system PMIC, ams AS3722,
node to enable power off functionality through PMIC.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Contrary to the rest of the keyboard, which is connected to the ChromeOS
embedded controller, the power key is hooked up to a GPIO. Add a device
tree node to handle it.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The keyboard on Venice2 is attached to the ChromeOS embedded controller.
Add the corresponding device tree nodes and use the MATRIX_KEY define to
encode keycodes.
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add ams AS3722 entry for gpio/pincontrol and regulators
to venice2 DT.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Compare the initial population of default pinmux configuration of Venice2
with the chrome branch and add/fix the missing configurations.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This pin needs to be configured in pull-down, non-tristate mode in order
for the backlight to work correctly.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Other boards use PULL_NONE for their debug UART pins, and without this
change, the board doesn't accept any serial input.

Don't set the I2S port pins to tristate mode, or no audio signal will
be sent out.

Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2")
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the default pinmux configuration for the Tegra124 based
Venice2 platform.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Subsequent patches will need to reference a PWM channel for backlight
support, so enable the PWM device and assign a label to it.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers,
and a combo headphones/microphone jack. Add a top-level sound card node
to represent this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Enable all the I2C controllers that are wired up on Venice2. I don't
know the correct I2C bus clock rates, so set them all to a conservative
100KHz for now.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Tegra124 has 4 MMC controllers just like previous versions of the SoC.
Note that there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW.

Also enable the relevant controllers in the Venice2 board DT.

power-gpios property suggested by Thierry Reding.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NThierry Reding <treding@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>