- 02 2月, 2016 1 次提交
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由 Jon Hunter 提交于
The NVIDIA bootloader, nvtboot, expects the "chosen" node to be present in the device-tree blob and if it is not then it fails to boot the kernel. Add the chosen node so we can boot the kernel on Tegra132 Norrin with the nvtboot bootloader. Signed-off-by: NJon Hunter <jonathanh@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 24 11月, 2015 10 次提交
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由 Thierry Reding 提交于
The Jetson TX1 Development Kit is the successor of the Jetson TK1. The Jetson TX1 is composed of the Jetson TX1 module (P2180) that connects to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel connected via the P2597's display connector. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The NVIDIA P2597 I/O board is a carrier board for the Jetson TX1 module and together they are also known as the Jetson TX1 Developer Kit. The I/O board provides an RJ45 connector routed to the network adapter that is part of the Jetson TX1 module. It exposes many other connectors such as SATA, USB 3.0, HDMI, JTAG and PCIe, among others, as well. Dedicated connectors allow display and camera modules to be attached. A full-size SD slot is provided to extend storage beyond the 32 GiB of eMMC found on the Jetson TX1 module. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials. It is typically connected to some I/O board (such as the P2597) that has the connectors needed to hook it up to the outside world. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The NVIDIA P2571 is an internal reference design that's very similar to the P2371, but targetting different use-cases. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The NVIDIA P2371 is an internal reference design that uses a P2530 processor module hooked up to a P2595 I/O board and an optional display module for a 1200x1920 MIPI DSI panel. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The NVIDIA P2595 I/O board is used in several reference designs and has the connectors to connect the P2530 compute module to the outside world. It features a USB 3.0 network adapter, a USB 3.0 port, an HDMI port, a SATA port, an audio codec, a microSD card slot and a display connector, among others. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The NVIDIA P2530 is a processor module used in several reference designs that features a Tegra210 SoC, 4 GiB of LPDDR4 RAM, 16 GiB eMMC and other essentials. It is typically connected to some I/O board that provides the connectors needed to hook it up to the outside world. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Norrin is a Tegra132-based FFD used as reference platform within NVIDIA. Based on work by Allen Martin <amartin@nvidia.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
NVIDIA Tegra132 (also known as Tegra K1 64-bit) is a variant of Tegra124 but with 2 Denver CPUs instead of the 4+1 Cortex-A15. This adds the DTSI file for the SoC, which is mostly similar to the one for Tegra124. Based on work by Allen Martin <amartin@nvidia.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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