The NVIDIA bootloader, nvtboot, expects the "chosen" node to be present
in the device-tree blob and if it is not then it fails to boot the kernel.
Add the chosen node so we can boot the kernel on Tegra132 Norrin with the
nvtboot bootloader.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The DMA-330 has an "irq_abort" interrupt line on which it signals faults
separately from the "irq[n:0]" channel interrupts. On Juno, this is
wired up to SPI 92; add it to the DT so that DMAC faults are correctly
reported for the driver to reset the thing, rather than leaving it
locked up and waiting to time out.

CC: Liviu Dudau <liviu.dudau@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NRobin Murphy <robin.murphy@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

This patch replace the assoication between dsaf and enet from string
matching to object reference. It requires the DTS to be updated within
BIOS. Thanks god it can be done for all released boards.
Signed-off-by: NKejian Yan <yankejian@huawei.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NYisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When linux start up, we get the log below:
"Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl
mdio_bus mdio@803c0000: mdio sys ctl reg has not maped"

The source code about the subctrl is dealt syscon, but dts doesn't.
It cause such fault, so this patch adds the syscon info on dts files to
fixes it.
Signed-off-by: NKejian Yan <yankejian@huawei.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This reverts commit 59dfafd0

Mark Brown reports that the dts file should not be accepted at this time
as it is not following the convention that has been agreed on for the
ion drivers.
Reported-by: NMark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Chen Feng <puck.chen@hisilicon.com>
Cc: Yu Dongbin <yudongbin@hisilicon.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This patch updates the LS2080a DTSI (DTS Include) file to add
support for eight SP805 Watchdog units which can be used to
reset the eight Cortex-A57 cores available on LS2080A.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

X-Gene v2 I2C0 and I2C1 controllers share the same clock
enable register field. This patch remove clock node for I2C1
and leave I2C1 clock always on as having it toggled on/off
will affect I2C0 operation.
Signed-off-by: NDuc Dang <dhdang@apm.com>

X-Gene v1 I2C0 and I2C1 controllers share the same clock
enable register field. This patch remove clock node for I2C0
and leave I2C0 clock always on as having it toggled on/off
will affect I2C1 operation.
Signed-off-by: NDuc Dang <dhdang@apm.com>

Use devicetree standard node name for I2C (i2c@...),
GFC GPIO (gpio@...), DW GPIO (gpio@...), Standby GPIO (gpio@...).

The DT node name of USB (dwusb@...) still needs to be kept to
maintain backward compatibility with old firmware.
Signed-off-by: NDuc Dang <dhdang@apm.com>

Add label properties to provide a way to identify UARTs based on their
board or connector name. This follows naming convention in 96boards CE
spec. Ports without external connections are not labelled.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add label properties to provide a way to identify UART, I2C and SPI
ports based on their connector names. This follows naming convention in
96boards CE spec. Ports without external connections are not labelled.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Andy Gross <agross@codeaurora.org>
Acked-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The LS UART0 is not used by anything else and should be enabled for
expansion boards.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Andy Gross <agross@codeaurora.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds idle-states bindings data collected through a set of
benchmarking experiments (latency and energy consumption) on Juno
boards. Latencies data represents the worst case scenarios as required
by the DT idle-states bindings.
Signed-off-by: NJon Medhurst <tixy@linaro.org>
Acked-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Added sys-reboot node to the FSL's LS2080A SoC DT to leverage
the ARM-generic reboot mechanism for this SoC. This mechanism
is enabled through CONFIG_POWER_RESET_SYSCON.
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NWenbin Song <Wenbin.Song@freescale.com>
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks are
similar to LS1021a which also complies to Freescale Chassis 2.1 spec.

Created LS1043a SoC DTSI file to be included by board level DTS files.
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NWenbin Song <Wenbin.Song@freescale.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This is the first ARMv8 SoC from Socionext Inc.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add ION node to enable ION on hi6220 SoC platform
Signed-off-by: NChen Feng <puck.chen@hisilicon.com>
Signed-off-by: NYu Dongbin <yudongbin@hisilicon.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

SATA clock is 815, not 915.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This enables SATA device in r8a7795-salvator-x.dts.
Signed-off-by: NKouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This adds SATA device node to r8a7795.dtsi.
Signed-off-by: NKouei Abe <kouei.abe.cp@renesas.com>
[uli: adjusted for new MSTP clock scheme]
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Enabling the performance monitor unit on r8a7795.
Signed-off-by: NMasaru Nagai <masaru.nagai.vx@renesas.com>
Signed-off-by: NYoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: NDirk Behme <dirk.behme@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Sigend-off-by: NDirk Behme <dirk.behme@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add PSCI node for r8a7795 SoC, and cpu node enable-method property is
set to "psci".
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NDirk Behme <dirk.behme@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds the PM8916 regulator nodes found on MSM8916 platforms.
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Acked-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>

Add support for the SMD and RPM devices found on MSM8916 platforms.
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Acked-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>

This patch adds the nodes necessary to support the SMEM driver on MSM8916
platforms.
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Acked-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>

2mA drive strength is not enough when we connect multiple i2c devices
on the bus with different pull up resistors.

This issue was detected when multiple i2c devices connected on the other side
of level shifters on Linaro sensor board. Maxing up to 16mA made i2c much stable.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch fixes the i2c bus number aliasing so that it matches with the
schematics bus naming.

Without this patch the user might would get bus numbers depending on
the order the devices are probed.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Currently the rates of the xo and sleep clocks are hard-coded in the
GCC driver, but this is a board layout description that actually should
be in the DT. Moving them into DT also allows us to insert the RPM
controlled clocks between the DT and GCC clocks.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

Add an alias for pm8916 on msm8916 based SoCs so that the newly
updated dtbTool can find the pmic compatible string and add the
pmic-id element to the QCDT header.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

This compatible string isn't compliant with the format for
subtypes. Replace it with a compliant compatible type.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

GPIO can be used as interrupt-controller. Add the missing properties to
the GPIO node.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is a need of a broadcast timer in this case to ensure proper
wakeup when the cpus are in sleep mode and a timer expires.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The GPIO block for ls2080a platform has little endian registers,
the GPIO driver needs this property to read/write registers by
right interface.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Add the "little-endian" property to fix the issue that eSDHC
is not working and dumping out "mmc0: Controller never released
inhibit bit(s)." error messages constantly.

Fixes: 5461597f ("dts/ls2080a: Update DTSI to add support of various peripherals")
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

The card detect pin is currently called sdmcc-cd.
This patch fixes the typo and renames the pin to sdmmc-cd.
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

In general, the logic voltage is affected by ddr frequency factors.
We should fix the correct voltage range since assuemd that we have the
ddr frequency driver in mainline.

AFAIK, the 1.8v voltage is used by the SD3.0 card.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add DMA channels definitions for UART1 and UART2 controllers.
Signed-off-by: NIvan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>