Add support for single PWM channel on Low-Power Timer, that can be
found on some STM32 platforms.
Signed-off-by: NFabrice Gasnier <fabrice.gasnier@st.com>
Acked-by: NThierry Reding <thierry.reding@gmail.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

include/linux/i2c is not for client devices. Move the header file to a
more appropriate location.
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NMark Brown <broonie@kernel.org>
Acked-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: NJonathan Cameron <jic23@kernel.org>
Acked-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
Acked-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: NThierry Reding <thierry.reding@gmail.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NDaniel Thompson <daniel.thompson@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Fix suspend/resume support:

- add disabled_mask to struct samsung_pwm_chip to track PWM
  disabled state information in pwm_samsung_{disable,enable}()

- rename pwm_samsung_config() to __pwm_samsung_config() and
  add extra force_period parameter to be used during resume
  (to force tin_ns and tcnt recalculation)

- add pwm_samsung_config() wrapper for preserving old behavior

- properly restore PWM configuration in pwm_samsung_resume()

- remove no longer needed pwm_samsung_suspend()

- update Copyrights
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

If the requested period_ns and duty_ns values are identical to the last
programmed ones pwm_samsung_config() returns early and skips the
hardware configuration. The same checks are now done by the PWM core so
the driver specific ones can be removed.
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Make sure to disable the PWM clock if the PWM cannot be configured due
to the clock divider exceeding the maximum value.

While at it, replace the hardcoded maximum clock divider with a defined
constant to improve code readability.
Signed-off-by: NZhi Mao <zhi.mao@mediatek.com>
Acked-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

In order to save some power, do not prepare the top and main clocks
during mtk_pwm_probe(). Instead, prepare the clocks only when necessary
and also make sure to enable the clocks to match the semantics of the
common clock framework.

While at it, don't explicitly disable all PWM channels in ->remove()
because all users should have done that already.
Signed-off-by: NZhi Mao <zhi.mao@mediatek.com>
Acked-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

In original code, the PWM output frequency is not correct when set
bit<3>=1 to PWMCON register.
Signed-off-by: NZhi Mao <zhi.mao@mediatek.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Fix a copy/paste error that sneaked into the Kconfig description of the
Mediatek PWM driver.
Signed-off-by: NZhi Mao <zhi.mao@mediatek.com>
Acked-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Commit a53e35db ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.

No functional changes.

Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-pwm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Commit a53e35db ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.

No functional changes.

Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-pwm@vger.kernel.org
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Runtime PM callbacks can be run right after runtime PM is enabled, so
make sure to set the driver data before that. This is unlikely to ever
happen with the current driver, but it doesn't hurt to follow best
practices anyway.
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

I noticed most of these while reviewing another patch and thought I'd
fix them while at it. These are mostly changes to make variable types
more strict and whitespace fixups.
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Runtime PM callbacks can be run right after runtime PM is enabled, so
make sure to set the driver data before that. This is unlikely to ever
happen with the current driver, but it doesn't hurt to follow best
practices anyway.
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

I noticed most of these while reviewing another patch and thought I'd
fix them while at it. These are mostly changes to make variable types
more strict and whitespace fixups.
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Make sure to unprepare the clock before returning on late probe errors.

Fixes: b388f15f ("pwm: pwm-tiehrpwm: Use clk_enable/disable instead clk_prepare/unprepare.")
Signed-off-by: NJohan Hovold <johan@kernel.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Remove unbalanced RPM put at driver unbind which resulted in a negative
usage count.

Fixes: 19891b20 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM")
Signed-off-by: NJohan Hovold <johan@kernel.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

66AK2G SoC has ECAP subsystem that is used as pwm-backlight provider for
display. Hence, enable pwm-tiecap driver to be built for Keystone
architecture.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

It adds PWM device driver for ZTE ZX family SoCs. The PWM controller
supports 4 devices with polarity configuration.

The driver has been tested with pwm-regulator support to scale core
voltage via cpufreq.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

This adds support for the third (optional) pwm cell to specify the
polarity, which is needed by display backlights for example.
Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The rk3328 SoC supports atomic update, we could lock the configuration
of period and duty at first, after unlock is configured, the period and
duty are effective at the same time.

If the polarity, period and duty need to be configured together,
the way for atomic update is "configure lock and old polarity" ->
"configure period and duty" -> "configure unlock and new polarity".
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Just use the same PWM ops for each IP, and get rid of the ops in struct
rockchip_pwm_data, but still define the three different instances of the
struct to use common interface for each IP.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

It is usually possible to configure the polarity, cycle and duty all at
once, so that the polarity and cycle and duty are applied atomically.
Move it from rockchip_pwm_set_enable() into rockchip_pwm_config(), as
well as prepare for the next atomic update commit.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Drop the custom hook of pwm_enable() and implement pwm_apply_v1() and
pwm_apply_v2() instead.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

It seems the rockchip_pwm_config() always returns the result 0, so
remove the judge.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

New PWM module provides two individual clocks for APB clock and function
clock.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Remove support for the SH7372 (SH-Mobile AP4) from the renesas-tpu
driver.

Commit edf41009 ("ARM: shmobile: sh7372 dtsi: Remove Legacy
file") removed this SoC from the kernel in v4.1.
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Undo preparation of a clock source if vt8500_pwm_probe() is not
successful.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The function
static void pca9685_set_sleep_mode(struct pca9685 *pca, int sleep)
takes the chip in and out of sleep mode, depending on the value of
sleep, which is interpreted as a boolean.

To clarify that 'int sleep' is a boolean and not a sleep delay,
change the function interface to:
static void pca9685_set_sleep_mode(struct pca9685 *pca, bool enable)
Suggested-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NSven Van Asbroeck <thesven73@gmail.com>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: linux-pwm@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-amlogic@lists.infradead.org
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The __cros_ec_pwm_get_duty() routine was transposing the insize and
outsize fields when calling cros_ec_cmd_xfer_status().

The original code worked without error due to size of the two particular
parameter blocks passed to cros_ec_cmd_xfer_status(), so this change is
not fixing an actual runtime problem, just correcting the calling usage.
Signed-off-by: NNick Vaccaro <nvaccaro@chromium.org>
Reviewed-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

When using input clocks with high rates, such as clk81 (166MHz), the
fin_ns = NSEC_PER_SEC / fin_freq can introduce a significant error.

Ex: fin_freq = 166666667, NSEC_PER_SEC = 1000000000
    fin_ns = 5,9999999

which is, of course, rounded down to 5. This introduces an error of ~20%
on the period requested from the PWM.

This patch uses ps instead of ns (and 64 bit integers) to perform the
calculation. This should give a good enough precision.

Fixes: 211ed630 ("pwm: Add support for Meson PWM Controller")
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

squash! pwm: meson: Improve pwm calculation precision

On the gxbb (and gxl) family, the PWMs of the AO domain require a
specific compatible because the possible input clocks are different
from the EE PWMs input clocks.

Since the number of possible input clocks is also different, the
'num_parents' field is added to all the Meson PWM data.
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Remove the legacy callbacks .enable(), .disable(), .set_polarity() and
.config().
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Switch the driver to atomic PWM. This makes it easier to wait a proper
amount of time when changing the duty cycle before disabling the channel
(main use case is switching the duty cycle to 0 before disabling).
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Implement .get_state instead of only reading the polarity at probe time.
This allows to get the proper state, period and duty cycle.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

File size before:
   text	   data	    bss	    dec	    hex	filename
   1510	    296	      0	   1806	    70e	drivers/pwm/pwm-hibvt.o
File size After adding 'const':
   text	   data	    bss	    dec	    hex	filename
   1606	    192	      0	   1798	    706	drivers/pwm/pwm-hibvt.o
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

In of_pwm_get(), if we fail to get the PWM chip due to probe deferal, we
shouldn't print an error message. Just be silent in this case.
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdfSigned-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.

From HW team:

	Before Tegra186, it is 48 MHz.
	In Tegra186, it is 102 MHz.

Add support to limit the clock source frequency to the maximum IP
supported frequency. Provide these values via SoC chipdata.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.

One inherent problem of this new approach is that the pinctrl framework
does not allow us to configure each pin on demand, when the various PWM
channels are requested or released. For instance, the PWM channels can
be configured from sysfs, which would require all PWM pins to be configured
properly beforehand for the PWM function, eventually causing conflicts
with other platform or board drivers.

The proper solution here would be to modify the pwm-jz4740 driver to
handle only one PWM channel, and create an instance of this driver
for each one of the 8 PWM channels. Then, it could use the pinctrl
framework to dynamically configure the PWM pin it controls.

Until this can be done, the only jz4740 board supported upstream
(Qi lb60) can configure all of its connected PWM pins in PWM function
mode, since those are not used by other drivers nor by GPIOs on the
board.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Acked-by: NThierry Reding <thierry.reding@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>