pwm: mediatek: Fix PWM source clock selection

In original code, the PWM output frequency is not correct when set
bit<3>=1 to PWMCON register.
Signed-off-by: NZhi Mao <zhi.mao@mediatek.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

drivers/pwm/pwm-mediatek.c

@@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	if (clkdiv > 7)
 		return -EINVAL;
 
-	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
+	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
 	mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
 	mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);