* To remove the risk of inconvenient register allocation decisions
   by the compiler, these functions are separated out as pure
   assembler.

 * The apcs frame manipulation code is not applicable for Thumb-2
   (and also not easily compatible).  Since it's not essential to
   have a full frame on these leaf assembler functions, the frame
   manipulation is removed, in the interests of simplicity.

 * Split up ldm/stm instructions to be compatible with Thumb-2,
   as well as avoiding instruction forms deprecated on >= ARMv7.
Signed-off-by: NDave Martin <dave.martin@linaro.org>
Reviewed-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add some basic empty infrastructure for DT support on ARM.

v5: - Fix off-by-one error in size calculation of initrd
    - Stop mucking with cmd_line, and load command line from dt into
      boot_command_line instead which matches the behaviour of ATAGS booting
v3: - moved cmd_line export and initrd setup to this patch to make the
      series bisectable.
    - switched to alloc_bootmem_align() for allocation when
      unflattening the device tree.  memblock_alloc() was not the
      right interface.
Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com>
Tested-by: NTony Lindgren <tony@atomide.com>
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

CONFIG_PM is now set whenever we support either runtime PM in addition
to suspend and hibernate.  This causes build errors when runtime PM is
enabled on a platform, but the CPU does not have the appropriate support
for suspend.

So, switch this code to use CONFIG_PM_SLEEP rather than CONFIG_PM to
allow runtime PM to be enabled without causing build errors.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This adds core support for saving and restoring CPU coprocessor
registers for suspend/resume support.  This contains support for suspend
with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
Tested on Assabet and Tegra 2.
Tested-by: NColin Cross <ccross@android.com>
Tested-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide common sched_clock() infrastructure for platforms to use to
create a 64-bit ns based sched_clock() implementation from a counter
running at a non-variable clock rate.

This implementation is based upon maintaining an epoch for the counter
and an epoch for the nanosecond time.  When we desire a sched_clock()
time, we calculate the number of counter ticks since the last epoch
update, convert this to nanoseconds and add to the epoch nanoseconds.

We regularly refresh these epochs within the counter wrap interval.
We perform a similar calculation as above, and store the new epochs.

We read and write the epochs in such a way that sched_clock() can easily
(and locklessly) detect when an update is in progress, and repeat the
loading of these constants when they're known not to be stable.  The
one caveat is that sched_clock() is not called in the middle of an
update.  We achieve that by disabling IRQs.

Finally, if the clock rate is known at compile time, the counter to ns
conversion factors can be specified, allowing sched_clock() to be tightly
optimized.  We ensure that these factors are correct by providing an
initialization function which performs a run-time check.
Acked-by: NPeter Zijlstra <peterz@infradead.org>
Tested-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: NWill Deacon <will.deacon@arm.com>
Tested-by: NMikael Pettersson <mikpe@it.uu.se>
Tested-by: NEric Miao <eric.y.miao@gmail.com>
Tested-by: NOlof Johansson <olof@lixom.net>
Tested-by: NJamie Iles <jamie@jamieiles.com>
Reviewed-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

smp.c is becoming too large, so split out the TLB maintainence
broadcasting into a separate smp_tlb.c file.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

iwmmxt is used in XScale, XScale3, Mohawk and PJ4 core. But the instructions
of accessing CP0 and CP1 is changed in PJ4. Append more files to support
iwmmxt in PJ4 core.
Signed-off-by: NZhou Zhu <zzhu3@marvell.com>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: NNicolas Pitre <nico@fluxnic.net>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

swp_emulate is only used on ARMv7+, and includes ARMv7+ assembly
instructions.  Allow the assembler to accept ARMv7 instructions,
but leave the compiler's code generation options alone.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Cc: Tim Bird <tim.bird@am.sony.com>
[rabin@rab.in: rebase on top of latest code,
	       keep code in ftrace.c instead of separate file,
	       check for ftrace_graph_entry also]
Signed-off-by: NRabin Vincent <rabin@rab.in>

The SWP instruction was deprecated in the ARMv6 architecture,
superseded by the LDREX/STREX family of instructions for
load-linked/store-conditional operations. The ARMv7 multiprocessing
extensions mandate that SWP/SWPB instructions are treated as undefined
from reset, with the ability to enable them through the System Control
Register SW bit.

This patch adds the alternative solution to emulate the SWP and SWPB
instructions using LDREX/STREX sequences, and log statistics to
/proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also
modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when
user RO.
Signed-off-by: NLeif Lindholm <leif.lindholm@arm.com>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Acked-by: NKirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

If we're targetting a v6 or v7 core and have at least software perf events
available, then automatically add support for hardware breakpoints.

Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: S. Karthikeyan <informkarthik@gmail.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This function is used by vmcore code to read a page from the old
kernel memory.
Signed-off-by: NMika Westerberg <ext-mika.1.westerberg@nokia.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This was deprecated in 2001 and announced to live on for 5 years.

For now provide a kernel parameter for those who still need it.
Acked-by: NEric Miao <eric.miao@canonical.com>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch implements support for ARMv6 performance counters in the
Linux performance events subsystem. ARMv6 architectures that have the
performance counters should enable HW_PERF_EVENTS to get hardware
performance events support in addition to the software events.

Note: only ARM Ltd ARM cores are supported.

This implementation also provides an ARM PMU abstraction layer to allow
ARMv7 and others to be supported in the future by adding new a
'struct arm_pmu'.

Cc: Jean Pihet <jpihet@mvista.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: NJamie Iles <jamie.iles@picochip.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

To add support for perf events and to allow the hardware counters to be
shared with oprofile, we need a way to reserve access to the pmu
(performance monitor unit). Platforms with PMU interrupts should
register the interrupts in arch/arm/kernel/pmu.c
Signed-off-by: NJamie Iles <jamie.iles@picochip.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch allows an earlyprintk console if CONFIG_DEBUG_LL is enabled,
using the printch asm function.

The patch is based on the original work by Sascha Hauer.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NPavel Machek <pavel@ucw.cz>

This driver implements support for on-chip Embedded Tracing Macrocell and
Embedded Trace Buffer. It allows to trigger tracing of kernel execution flow
and exporting trace output to userspace via character device and a sysrq
combo.

Trace output can then be decoded by a fairly simple open source tool [1]
which is already sufficient to get the idea of what the kernel is doing.

[1]: http://github.com/virtuoso/etm2humanSigned-off-by: NAlexander Shishkin <virtuoso@slind.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Albin Tonnerre <albin.tonnerre@free-electrons.com> reported:

    Bash 4 filters out variables which contain a dot in them.
    This happends to be the case of CPPFLAGS_vmlinux.lds.
    This is rather unfortunate, as it now causes
    build failures when using SHELL=/bin/bash to compile,
    or when bash happens to be used by make (eg when it's /bin/sh)

Remove the common definition of CPPFLAGS_vmlinux.lds by
pushing relevant stuff to either Makefile.build or the
arch specific kernel/Makefile where we build the linker script.

This is also nice cleanup as we move the information out where
it is used.

Notes for the different architectures touched:

arm - we use an already exported symbol
cris - we use a config symbol aleady available
       [Not build tested]
mips - the jiffies complexity has moved to vmlinux.lds.S where we need it.
       Added a few variables to CPPFLAGS - they are only used by
       the linker script.
       [Not build tested]
powerpc - removed assignment that is not needed
          [not build tested]
sparc - simplified it using $(BITS)
um - introduced a few new exported variables to deal with this
xtensa - added options to CPP invocation
         [not build tested]

Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Mikael Starvik <starvik@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jeff Dike <jdike@addtoit.com>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: NSam Ravnborg <sam@ravnborg.org>

This adds the TCM interface to Linux, when active, it will
detect and report TCM memories and sizes early in boot if
present, introduce generic TCM memory handling, provide a
generic TCM memory pool and select TCM memory for the U300
platform.

See the Documentation/arm/tcm.txt for documentation.
Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

As __builtin_return_address(n) doesn't work for ARM with n > 0, the
kernel needs its own implementation.

This fixes many warnings saying:

	warning: unsupported argument to '__builtin_return_address'

The new methods and walk_stackframe must not be instrumented because
CALLER_ADDRESSx is used in the various tracers and tracing the tracer is
a bad idea.

What's currently missing is an implementation using unwind tables.  This
is not fatal though, it's just that the tracers don't get enough
information to be really useful.

Note that if both ARM_UNWIND and FRAME_POINTER are enabled,
walk_stackframe uses unwind information.  So in this case the same
implementation is used as when FRAME_POINTER is disabled.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NEric Miao <eric.miao@marvell.com>

This patch also makes the frame pointer default to y only if
!ARM_UNWIND. LOCKDEP no longer selects FRAME_POINTER if ARM_UNWIND is
enabled.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add support for detecting non-executable stack binaries, and adjust
permissions to prevent execution from data and stack areas.  Also,
ensure that READ_IMPLIES_EXEC is enabled for older CPUs where that
is true, and for any executable-stack binary.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds the ARCH=arm specific a kgdb backend, originally
written by Deepak Saxena <dsaxena@plexity.net> and George Davis
<gdavis@mvista.com>.  Geoff Levand <geoffrey.levand@am.sony.com>,
Nicolas Pitre, Manish Lachwani, and Jason Wessel have contributed
various fixups here as well.

The KGDB patch makes one change to the core ARM architecture such that
the traps are initialized early for use with the debugger or other
subsystems.

[ mingo@elte.hu: small cleanups. ]
[ ben-linux@fluff.org: fixed early_trap_init ]
Signed-off-by: NJason Wessel <jason.wessel@windriver.com>
Acked-by: NDeepak Saxena <dsaxena@plexity.net>

Core ftrace support for the ARM architecture, which includes support
for dynamic function tracing.
Signed-off-by: NAbhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

This patch adds the detection and handling of the ThumbEE extension on
ARMv7 CPUs.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>

Semaphores are no longer performance-critical, so a generic C
implementation is better for maintainability, debuggability and
extensibility.  Thanks to Peter Zijlstra for fixing the lockdep
warning.  Thanks to Harvey Harrison for pointing out that the
unlikely() was unnecessary.
Signed-off-by: NMatthew Wilcox <willy@linux.intel.com>
Acked-by: NIngo Molnar <mingo@elte.hu>

Currently, the atags used by kexec are fixed to the ones originally used
to boot the kernel. This is less than ideal as changing the commandline,
initrd and other options would be a useful feature.

This patch exports the atags used for the current kernel to userspace
through an "atags" file in procfs. The presence of the file is
controlled by its own Kconfig option and cleans up several ifdef blocks
into a separate file. The tags for the new kernel are assumed to be at
a fixed location before the kernel image itself. The location of the
tags used to boot the original kernel is unimportant and no longer
saved.

Based on a patch from Uli Luckas <u.luckas@road.de>
Signed-off-by: NRichard Purdie <rpurdie@rpsys.net>
Acked-by: NUli Luckas <u.luckas@road.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This is a full implementation of Kprobes including Jprobes and
Kretprobes support.

This ARM implementation does not follow the usual kprobes double-
exception model. The traditional model is where the initial kprobes
breakpoint calls kprobe_handler(), which returns from exception to
execute the instruction in its original context, then immediately
re-enters after a second breakpoint (or single-stepping exception)
into post_kprobe_handler(), each time the probe is hit..  The ARM
implementation only executes one kprobes exception per hit, so no
post_kprobe_handler() phase. All side-effects from the kprobe'd
instruction are resolved before returning from the initial exception.
As a result, all instructions are _always_ effectively boosted
regardless of the type of instruction, and even regardless of whether
or not there is a post-handler for the probe.
Signed-off-by: NAbhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: NQuentin Barnes <qbarnes@gmail.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

This is the code implementing instruction single-stepping for kprobes
on ARM.

To get around the limitation of no Next-PC and no hardware single-
stepping, all kprobe'd instructions are split into three camps:
simulation, emulation, and rejected. "Simulated" instructions are
those instructions which behavior is reproduced by straight C code.
"Emulated" instructions are ones that are copied, slightly altered
and executed directly in the instruction slot to reproduce their
behavior.  "Rejected" instructions are ones that could be simulated,
but work hasn't been put into simulating them. These instructions
should be very rare, if not unencountered, in the kernel. If ever
needed, code could be added to simulate them.

One might wonder why this and the ptrace singlestep facility are not
sharing some code.  Both approaches are fundamentally different because
the ptrace code regains control after the stepped instruction by installing
a breakpoint after the instruction itself, and possibly at the location
where the instruction might be branching to, instead of simulating or
emulating the target instruction.

The ptrace approach isn't suitable for kprobes because the breakpoints
would have to be moved back, and the icache flushed, everytime the
probe is hit to let normal code execution resume, which would have a
significant performance impact. It is also racy on SMP since another
CPU could, with the right timing, sail through the probe point without
being caught.  Because ptrace single-stepping always result in a
different process to be scheduled, the concern for performance is much
less significant.

On the other hand, the kprobes approach isn't (currently) suitable for
ptrace because it has no provision for proper user space memory
protection and translation, and even if that was implemented, the gain
wouldn't be worth the added complexity in the ptrace path compared to
the current approach.

So, until kprobes does support user space, both kprobes and ptrace are
best kept independent and separate.
Signed-off-by: NQuentin Barnes <qbarnes@gmail.com>
Signed-off-by: NAbhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Add support for stacktrace.  Use the new stacktrace code with
oprofile instead of it's version; there's no point having
multiple versions of stacktracing in the kernel.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add kexec support to ARM.

Improvements like commandline handling could be made but this patch gives
basic functional support. It uses the next available syscall number, 347.

Once the syscall number is known, userspace support will be
finalised/submitted to kexec-tools, various patches already exist.

Originally based on a patch by Maxim Syrchin but updated and forward
ported by various people.
Signed-off-by: NRichard Purdie <rpurdie@rpsys.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)

Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch.  Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.

CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.

This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.

These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Acked-by: NDan Williams <dan.j.williams@intel.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add the necessary call to register_isa_ports() so that glibc knows
where these are found on Integrator platforms.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Lennert Buytenhek

This patch makes the iWMMXt context switch hook use the generic
thread notifier infrastructure that was recently merged in commit
d6551e88.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Lennert Buytenhek

Add the necessary kernel bits for crunch task switching.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>