i915_irq.c 118.5 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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static const u32 hpd_ibx[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

static const u32 hpd_cpt[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

static const u32 hpd_mask_i915[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

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static const u32 hpd_status_g4x[] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* For display hotplug interrupt */
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static void
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ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.deimr &= ~mask;
		return;
	}

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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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static void
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ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.deimr |= mask;
		return;
	}

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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
		dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
						interrupt_mask);
		return;
	}

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}

void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	ilk_update_gt_irq(dev_priv, mask, mask);
}

void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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/**
  * snb_update_pm_irq - update GEN6_PMIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
		dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
						     interrupt_mask);
		return;
	}

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
		I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
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		POSTING_READ(GEN6_PMIMR);
	}
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}

void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	snb_update_pm_irq(dev_priv, mask, mask);
}

void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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static bool ivb_can_enable_err_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc;
	enum pipe pipe;

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	assert_spin_locked(&dev_priv->irq_lock);

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	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->cpu_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static bool cpt_can_enable_serr_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe;
	struct intel_crtc *crtc;

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	assert_spin_locked(&dev_priv->irq_lock);

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	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->pch_fifo_underrun_disabled)
			return false;
	}

	return true;
}

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static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg = PIPESTAT(pipe);
	u32 pipestat = I915_READ(reg) & 0x7fff0000;

	assert_spin_locked(&dev_priv->irq_lock);

	I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
	POSTING_READ(reg);
}

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static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
						 enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
					  DE_PIPEB_FIFO_UNDERRUN;

	if (enable)
		ironlake_enable_display_irq(dev_priv, bit);
	else
		ironlake_disable_display_irq(dev_priv, bit);
}

static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
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						  enum pipe pipe, bool enable)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	if (enable) {
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		I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

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		if (!ivb_can_enable_err_int(dev))
			return;

		ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
	} else {
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		bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);

		/* Change the state _after_ we've read out the current one. */
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		ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
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		if (!was_enabled &&
		    (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
			DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
				      pipe_name(pipe));
		}
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	}
}

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static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
						  enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	assert_spin_locked(&dev_priv->irq_lock);

	if (enable)
		dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
	else
		dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
					 uint32_t interrupt_mask,
					 uint32_t enabled_irq_mask)
{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled &&
	    (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
		dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
						 interrupt_mask);
		return;
	}

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
#define ibx_enable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), (bits))
#define ibx_disable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), 0)

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static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum transcoder pch_transcoder,
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					    bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
		       SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
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	if (enable)
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		ibx_enable_display_interrupt(dev_priv, bit);
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	else
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		ibx_disable_display_interrupt(dev_priv, bit);
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}

static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum transcoder pch_transcoder,
					    bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (enable) {
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		I915_WRITE(SERR_INT,
			   SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));

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		if (!cpt_can_enable_serr_int(dev))
			return;

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		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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	} else {
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		uint32_t tmp = I915_READ(SERR_INT);
		bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);

		/* Change the state _after_ we've read out the current one. */
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		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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		if (!was_enabled &&
		    (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
			DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
				      transcoder_name(pch_transcoder));
		}
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	}
}

/**
 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 * @dev: drm device
 * @pipe: pipe
 * @enable: true if we want to report FIFO underrun errors, false otherwise
 *
 * This function makes us disable or enable CPU fifo underruns for a specific
 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 * reporting for one pipe may also disable all the other CPU error interruts for
 * the other pipes, due to the fact that there's just one interrupt mask/enable
 * bit for all the pipes.
 *
 * Returns the previous state of underrun reporting.
 */
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bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
					     enum pipe pipe, bool enable)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	bool ret;

	ret = !intel_crtc->cpu_fifo_underrun_disabled;

	if (enable == ret)
		goto done;

	intel_crtc->cpu_fifo_underrun_disabled = !enable;

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	if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
		i9xx_clear_fifo_underrun(dev, pipe);
	else if (IS_GEN5(dev) || IS_GEN6(dev))
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		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
	else if (IS_GEN7(dev))
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		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
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	else if (IS_GEN8(dev))
		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
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done:
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	return ret;
}

bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
					   enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;
	bool ret;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
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	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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	return ret;
}

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static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
						  enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	return !intel_crtc->cpu_fifo_underrun_disabled;
}

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/**
 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 * @dev: drm device
 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 * @enable: true if we want to report FIFO underrun errors, false otherwise
 *
 * This function makes us disable or enable PCH fifo underruns for a specific
 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 * underrun reporting for one transcoder may also disable all the other PCH
 * error interruts for the other transcoders, due to the fact that there's just
 * one interrupt mask/enable bit for all the transcoders.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
					   enum transcoder pch_transcoder,
					   bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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	unsigned long flags;
	bool ret;

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	/*
	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
	 * has only one pch transcoder A that all pipes can use. To avoid racy
	 * pch transcoder -> pipe lookups from interrupt code simply store the
	 * underrun statistics in crtc A. Since we never expose this anywhere
	 * nor use it outside of the fifo underrun code here using the "wrong"
	 * crtc on LPT won't cause issues.
	 */
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	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	ret = !intel_crtc->pch_fifo_underrun_disabled;

	if (enable == ret)
		goto done;

	intel_crtc->pch_fifo_underrun_disabled = !enable;

	if (HAS_PCH_IBX(dev))
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		ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
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	else
		cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);

done:
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	return ret;
}


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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		       u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
	                 status_mask & ~PIPESTAT_INT_STATUS_MASK))
		return;

	if ((pipestat & enable_mask) == enable_mask)
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		return;

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	dev_priv->pipestat_irq_mask[pipe] |= status_mask;

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	/* Enable the interrupt, clear any pending status */
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	pipestat |= enable_mask | status_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static void
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__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		        u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
	                 status_mask & ~PIPESTAT_INT_STATUS_MASK))
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		return;

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	if ((pipestat & enable_mask) == 0)
		return;

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	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

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	pipestat &= ~enable_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
{
	u32 enable_mask = status_mask << 16;

	/*
	 * On pipe A we don't support the PSR interrupt yet, on pipe B the
	 * same bit MBZ.
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
		return 0;

	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
			 SPRITE0_FLIP_DONE_INT_EN_VLV |
			 SPRITE1_FLIP_DONE_INT_EN_VLV);
	if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;

	return enable_mask;
}

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void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		     u32 status_mask)
{
	u32 enable_mask;

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	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
575 576 577 578 579 580 581 582 583
	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

void
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		      u32 status_mask)
{
	u32 enable_mask;

584 585 586 587 588
	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
589 590 591
	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

592
/**
593
 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
594
 */
595
static void i915_enable_asle_pipestat(struct drm_device *dev)
596
{
597 598 599
	drm_i915_private_t *dev_priv = dev->dev_private;
	unsigned long irqflags;

600 601 602
	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
		return;

603
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
604

605
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
606
	if (INTEL_INFO(dev)->gen >= 4)
607
		i915_enable_pipestat(dev_priv, PIPE_A,
608
				     PIPE_LEGACY_BLC_EVENT_STATUS);
609 610

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
611 612
}

613 614 615 616 617 618 619 620 621 622 623 624 625
/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
626

627 628 629 630
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Locking is horribly broken here, but whatever. */
		struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
631

632 633 634 635
		return intel_crtc->active;
	} else {
		return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
	}
636 637
}

638 639 640 641 642 643
static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
{
	/* Gen2 doesn't have a hardware frame counter */
	return 0;
}

644 645 646
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
647
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
648 649 650 651
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long high_frame;
	unsigned long low_frame;
652
	u32 high1, high2, low, pixel, vbl_start;
653 654

	if (!i915_pipe_enabled(dev, pipe)) {
655
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
656
				"pipe %c\n", pipe_name(pipe));
657 658 659
		return 0;
	}

660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		struct intel_crtc *intel_crtc =
			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		const struct drm_display_mode *mode =
			&intel_crtc->config.adjusted_mode;

		vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
	} else {
		enum transcoder cpu_transcoder =
			intel_pipe_to_cpu_transcoder(dev_priv, pipe);
		u32 htotal;

		htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
		vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;

		vbl_start *= htotal;
	}

678 679
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
680

681 682 683 684 685 686
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
687
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
688
		low   = I915_READ(low_frame);
689
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
690 691
	} while (high1 != high2);

692
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
693
	pixel = low & PIPE_PIXEL_MASK;
694
	low >>= PIPE_FRAME_LOW_SHIFT;
695 696 697 698 699 700

	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
701
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
702 703
}

704
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
705 706
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
707
	int reg = PIPE_FRMCOUNT_GM45(pipe);
708 709

	if (!i915_pipe_enabled(dev, pipe)) {
710
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
711
				 "pipe %c\n", pipe_name(pipe));
712 713 714 715 716 717
		return 0;
	}

	return I915_READ(reg);
}

718 719 720 721
/* raw reads, only for fast reads of display block, no need for forcewake etc. */
#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))

722
static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
723 724 725 726
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t status;

727
	if (INTEL_INFO(dev)->gen < 7) {
728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744
		status = pipe == PIPE_A ?
			DE_PIPEA_VBLANK :
			DE_PIPEB_VBLANK;
	} else {
		switch (pipe) {
		default:
		case PIPE_A:
			status = DE_PIPEA_VBLANK_IVB;
			break;
		case PIPE_B:
			status = DE_PIPEB_VBLANK_IVB;
			break;
		case PIPE_C:
			status = DE_PIPEC_VBLANK_IVB;
			break;
		}
	}
745

746
	return __raw_i915_read32(dev_priv, DEISR) & status;
747 748
}

749
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
750 751
				    unsigned int flags, int *vpos, int *hpos,
				    ktime_t *stime, ktime_t *etime)
752
{
753 754 755 756
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
757
	int position;
758 759 760
	int vbl_start, vbl_end, htotal, vtotal;
	bool in_vbl = true;
	int ret = 0;
761
	unsigned long irqflags;
762

763
	if (!intel_crtc->active) {
764
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
765
				 "pipe %c\n", pipe_name(pipe));
766 767 768
		return 0;
	}

769 770 771 772
	htotal = mode->crtc_htotal;
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
773

774 775 776 777 778 779
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
		vbl_end /= 2;
		vtotal /= 2;
	}

780 781
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

782 783 784 785 786 787 788 789 790 791 792 793 794
	/*
	 * Lock uncore.lock, as we will do multiple timing critical raw
	 * register reads, potentially with preemption disabled, so the
	 * following code must not block on uncore.lock.
	 */
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	
	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */

	/* Get optional system timestamp before query. */
	if (stime)
		*stime = ktime_get();

795
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
796 797 798
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
799
		if (IS_GEN2(dev))
800
			position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
801
		else
802
			position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
803

804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839
		if (HAS_PCH_SPLIT(dev)) {
			/*
			 * The scanline counter increments at the leading edge
			 * of hsync, ie. it completely misses the active portion
			 * of the line. Fix up the counter at both edges of vblank
			 * to get a more accurate picture whether we're in vblank
			 * or not.
			 */
			in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
			if ((in_vbl && position == vbl_start - 1) ||
			    (!in_vbl && position == vbl_end - 1))
				position = (position + 1) % vtotal;
		} else {
			/*
			 * ISR vblank status bits don't work the way we'd want
			 * them to work on non-PCH platforms (for
			 * ilk_pipe_in_vblank_locked()), and there doesn't
			 * appear any other way to determine if we're currently
			 * in vblank.
			 *
			 * Instead let's assume that we're already in vblank if
			 * we got called from the vblank interrupt and the
			 * scanline counter value indicates that we're on the
			 * line just prior to vblank start. This should result
			 * in the correct answer, unless the vblank interrupt
			 * delivery really got delayed for almost exactly one
			 * full frame/field.
			 */
			if (flags & DRM_CALLED_FROM_VBLIRQ &&
			    position == vbl_start - 1) {
				position = (position + 1) % vtotal;

				/* Signal this correction as "applied". */
				ret |= 0x8;
			}
		}
840 841 842 843 844
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
845
		position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
846

847 848 849 850
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
851 852
	}

853 854 855 856 857 858 859 860
	/* Get optional system timestamp after query. */
	if (etime)
		*etime = ktime_get();

	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

861 862 863 864 865 866 867 868 869 870 871 872
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
873

874
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
875 876 877 878 879 880
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
881 882 883 884 885 886 887 888

	/* In vblank? */
	if (in_vbl)
		ret |= DRM_SCANOUTPOS_INVBL;

	return ret;
}

889
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
890 891 892 893
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
894
	struct drm_crtc *crtc;
895

896
	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
897
		DRM_ERROR("Invalid crtc %d\n", pipe);
898 899 900 901
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
902 903 904 905 906 907 908 909 910 911
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

	if (!crtc->enabled) {
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
912 913

	/* Helper routine in DRM core does all the work: */
914 915
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
916 917
						     crtc,
						     &to_intel_crtc(crtc)->config.adjusted_mode);
918 919
}

920 921
static bool intel_hpd_irq_event(struct drm_device *dev,
				struct drm_connector *connector)
922 923 924 925 926 927 928
{
	enum drm_connector_status old_status;

	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
	old_status = connector->status;

	connector->status = connector->funcs->detect(connector, false);
929 930 931 932
	if (old_status == connector->status)
		return false;

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
933 934
		      connector->base.id,
		      drm_get_connector_name(connector),
935 936 937 938
		      drm_get_connector_status_name(old_status),
		      drm_get_connector_status_name(connector->status));

	return true;
939 940
}

941 942 943
/*
 * Handle hotplug events outside the interrupt handler proper.
 */
944 945
#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)

946 947 948 949 950
static void i915_hotplug_work_func(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    hotplug_work);
	struct drm_device *dev = dev_priv->dev;
951
	struct drm_mode_config *mode_config = &dev->mode_config;
952 953 954 955 956
	struct intel_connector *intel_connector;
	struct intel_encoder *intel_encoder;
	struct drm_connector *connector;
	unsigned long irqflags;
	bool hpd_disabled = false;
957
	bool changed = false;
958
	u32 hpd_event_bits;
959

960 961 962 963
	/* HPD irq before everything is fully set up. */
	if (!dev_priv->enable_hotplug_processing)
		return;

964
	mutex_lock(&mode_config->mutex);
965 966
	DRM_DEBUG_KMS("running encoder hotplug functions\n");

967
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
968 969 970

	hpd_event_bits = dev_priv->hpd_event_bits;
	dev_priv->hpd_event_bits = 0;
971 972 973 974 975 976 977 978 979 980 981 982 983 984
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
		intel_encoder = intel_connector->encoder;
		if (intel_encoder->hpd_pin > HPD_NONE &&
		    dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
		    connector->polled == DRM_CONNECTOR_POLL_HPD) {
			DRM_INFO("HPD interrupt storm detected on connector %s: "
				 "switching from hotplug detection to polling\n",
				drm_get_connector_name(connector));
			dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
			connector->polled = DRM_CONNECTOR_POLL_CONNECT
				| DRM_CONNECTOR_POLL_DISCONNECT;
			hpd_disabled = true;
		}
985 986 987 988
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
				      drm_get_connector_name(connector), intel_encoder->hpd_pin);
		}
989 990 991 992
	}
	 /* if there were no outputs to poll, poll was disabled,
	  * therefore make sure it's enabled when disabling HPD on
	  * some connectors */
993
	if (hpd_disabled) {
994
		drm_kms_helper_poll_enable(dev);
995 996 997
		mod_timer(&dev_priv->hotplug_reenable_timer,
			  jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
	}
998 999 1000

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
		intel_encoder = intel_connector->encoder;
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			if (intel_encoder->hot_plug)
				intel_encoder->hot_plug(intel_encoder);
			if (intel_hpd_irq_event(dev, connector))
				changed = true;
		}
	}
1011 1012
	mutex_unlock(&mode_config->mutex);

1013 1014
	if (changed)
		drm_kms_helper_hotplug_event(dev);
1015 1016
}

1017 1018 1019 1020 1021
static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
{
	del_timer_sync(&dev_priv->hotplug_reenable_timer);
}

1022
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1023 1024
{
	drm_i915_private_t *dev_priv = dev->dev_private;
1025
	u32 busy_up, busy_down, max_avg, min_avg;
1026 1027
	u8 new_delay;

1028
	spin_lock(&mchdev_lock);
1029

1030 1031
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

1032
	new_delay = dev_priv->ips.cur_delay;
1033

1034
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1035 1036
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
1037 1038 1039 1040
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
1041
	if (busy_up > max_avg) {
1042 1043 1044 1045
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
1046
	} else if (busy_down < min_avg) {
1047 1048 1049 1050
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
1051 1052
	}

1053
	if (ironlake_set_drps(dev, new_delay))
1054
		dev_priv->ips.cur_delay = new_delay;
1055

1056
	spin_unlock(&mchdev_lock);
1057

1058 1059 1060
	return;
}

1061 1062 1063
static void notify_ring(struct drm_device *dev,
			struct intel_ring_buffer *ring)
{
1064 1065 1066
	if (ring->obj == NULL)
		return;

1067
	trace_i915_gem_request_complete(ring);
1068

1069
	wake_up_all(&ring->irq_queue);
1070
	i915_queue_hangcheck(dev);
1071 1072
}

1073
void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109
			     u32 pm_iir, int new_delay)
{
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
		if (new_delay >= dev_priv->rps.max_delay) {
			/* Mask UP THRESHOLD Interrupts */
			I915_WRITE(GEN6_PMINTRMSK,
				   I915_READ(GEN6_PMINTRMSK) |
				   GEN6_PM_RP_UP_THRESHOLD);
			dev_priv->rps.rp_up_masked = true;
		}
		if (dev_priv->rps.rp_down_masked) {
			/* UnMask DOWN THRESHOLD Interrupts */
			I915_WRITE(GEN6_PMINTRMSK,
				   I915_READ(GEN6_PMINTRMSK) &
				   ~GEN6_PM_RP_DOWN_THRESHOLD);
			dev_priv->rps.rp_down_masked = false;
		}
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (new_delay <= dev_priv->rps.min_delay) {
			/* Mask DOWN THRESHOLD Interrupts */
			I915_WRITE(GEN6_PMINTRMSK,
				   I915_READ(GEN6_PMINTRMSK) |
				   GEN6_PM_RP_DOWN_THRESHOLD);
			dev_priv->rps.rp_down_masked = true;
		}

		if (dev_priv->rps.rp_up_masked) {
			/* UnMask UP THRESHOLD Interrupts */
			I915_WRITE(GEN6_PMINTRMSK,
				   I915_READ(GEN6_PMINTRMSK) &
				   ~GEN6_PM_RP_UP_THRESHOLD);
			dev_priv->rps.rp_up_masked = false;
		}
	}
}

1110
static void gen6_pm_rps_work(struct work_struct *work)
1111
{
1112
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1113
						    rps.work);
P
Paulo Zanoni 已提交
1114
	u32 pm_iir;
1115
	int new_delay, adj;
1116

1117
	spin_lock_irq(&dev_priv->irq_lock);
1118 1119
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
1120
	/* Make sure not to corrupt PMIMR state used by ringbuffer code */
P
Paulo Zanoni 已提交
1121
	snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
1122
	spin_unlock_irq(&dev_priv->irq_lock);
1123

1124 1125 1126
	/* Make sure we didn't queue anything we're not going to process. */
	WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);

1127
	if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
1128 1129
		return;

1130
	mutex_lock(&dev_priv->rps.hw_lock);
1131

1132
	adj = dev_priv->rps.last_adj;
1133
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1134 1135 1136 1137 1138
		if (adj > 0)
			adj *= 2;
		else
			adj = 1;
		new_delay = dev_priv->rps.cur_delay + adj;
1139 1140 1141 1142 1143

		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
1144 1145 1146 1147
		if (new_delay < dev_priv->rps.rpe_delay)
			new_delay = dev_priv->rps.rpe_delay;
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
		if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1148
			new_delay = dev_priv->rps.rpe_delay;
1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160
		else
			new_delay = dev_priv->rps.min_delay;
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
		else
			adj = -1;
		new_delay = dev_priv->rps.cur_delay + adj;
	} else { /* unknown event */
		new_delay = dev_priv->rps.cur_delay;
	}
1161

1162 1163 1164
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
1165 1166
	new_delay = clamp_t(int, new_delay,
			    dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1167 1168

	gen6_set_pm_mask(dev_priv, pm_iir, new_delay);
1169 1170 1171 1172 1173 1174
	dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;

	if (IS_VALLEYVIEW(dev_priv->dev))
		valleyview_set_rps(dev_priv->dev, new_delay);
	else
		gen6_set_rps(dev_priv->dev, new_delay);
1175

1176
	mutex_unlock(&dev_priv->rps.hw_lock);
1177 1178
}

1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1192
						    l3_parity.error_work);
1193
	u32 error_status, row, bank, subbank;
1194
	char *parity_event[6];
1195 1196
	uint32_t misccpctl;
	unsigned long flags;
1197
	uint8_t slice = 0;
1198 1199 1200 1201 1202 1203 1204

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

1205 1206 1207 1208
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1209 1210 1211 1212
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1213 1214
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
		u32 reg;
1215

1216 1217 1218
		slice--;
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
			break;
1219

1220
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1221

1222
		reg = GEN7_L3CDERRST1 + (slice * 0x200);
1223

1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

1239
		kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1240
				   KOBJ_CHANGE, parity_event);
1241

1242 1243
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1244

1245 1246 1247 1248 1249
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1250

1251
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1252

1253 1254 1255 1256 1257 1258 1259
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	mutex_unlock(&dev_priv->dev->struct_mutex);
1260 1261
}

1262
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1263 1264 1265
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

1266
	if (!HAS_L3_DPF(dev))
1267 1268
		return;

1269
	spin_lock(&dev_priv->irq_lock);
1270
	ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1271
	spin_unlock(&dev_priv->irq_lock);
1272

1273 1274 1275 1276 1277 1278 1279
	iir &= GT_PARITY_ERROR(dev);
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1280
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1281 1282
}

1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
}

1294 1295 1296 1297 1298
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

1299 1300
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1301
		notify_ring(dev, &dev_priv->ring[RCS]);
1302
	if (gt_iir & GT_BSD_USER_INTERRUPT)
1303
		notify_ring(dev, &dev_priv->ring[VCS]);
1304
	if (gt_iir & GT_BLT_USER_INTERRUPT)
1305 1306
		notify_ring(dev, &dev_priv->ring[BCS]);

1307 1308 1309
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1310 1311
		i915_handle_error(dev, false, "GT error interrupt 0x%08x",
				  gt_iir);
1312
	}
1313

1314 1315
	if (gt_iir & GT_PARITY_ERROR(dev))
		ivybridge_parity_error_irq_handler(dev, gt_iir);
1316 1317
}

1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367
static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
				       struct drm_i915_private *dev_priv,
				       u32 master_ctl)
{
	u32 rcs, bcs, vcs;
	uint32_t tmp = 0;
	irqreturn_t ret = IRQ_NONE;

	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
		tmp = I915_READ(GEN8_GT_IIR(0));
		if (tmp) {
			ret = IRQ_HANDLED;
			rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
			bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
			if (rcs & GT_RENDER_USER_INTERRUPT)
				notify_ring(dev, &dev_priv->ring[RCS]);
			if (bcs & GT_RENDER_USER_INTERRUPT)
				notify_ring(dev, &dev_priv->ring[BCS]);
			I915_WRITE(GEN8_GT_IIR(0), tmp);
		} else
			DRM_ERROR("The master control interrupt lied (GT0)!\n");
	}

	if (master_ctl & GEN8_GT_VCS1_IRQ) {
		tmp = I915_READ(GEN8_GT_IIR(1));
		if (tmp) {
			ret = IRQ_HANDLED;
			vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
			if (vcs & GT_RENDER_USER_INTERRUPT)
				notify_ring(dev, &dev_priv->ring[VCS]);
			I915_WRITE(GEN8_GT_IIR(1), tmp);
		} else
			DRM_ERROR("The master control interrupt lied (GT1)!\n");
	}

	if (master_ctl & GEN8_GT_VECS_IRQ) {
		tmp = I915_READ(GEN8_GT_IIR(3));
		if (tmp) {
			ret = IRQ_HANDLED;
			vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
			if (vcs & GT_RENDER_USER_INTERRUPT)
				notify_ring(dev, &dev_priv->ring[VECS]);
			I915_WRITE(GEN8_GT_IIR(3), tmp);
		} else
			DRM_ERROR("The master control interrupt lied (GT3)!\n");
	}

	return ret;
}

1368 1369 1370
#define HPD_STORM_DETECT_PERIOD 1000
#define HPD_STORM_THRESHOLD 5

1371
static inline void intel_hpd_irq_handler(struct drm_device *dev,
1372 1373
					 u32 hotplug_trigger,
					 const u32 *hpd)
1374 1375 1376
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;
1377
	bool storm_detected = false;
1378

1379 1380 1381
	if (!hotplug_trigger)
		return;

1382 1383 1384
	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
			  hotplug_trigger);

1385
	spin_lock(&dev_priv->irq_lock);
1386
	for (i = 1; i < HPD_NUM_PINS; i++) {
1387

1388
		WARN_ONCE(hpd[i] & hotplug_trigger &&
1389
			  dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1390 1391
			  "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
			  hotplug_trigger, i, hpd[i]);
1392

1393 1394 1395 1396
		if (!(hpd[i] & hotplug_trigger) ||
		    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
			continue;

1397
		dev_priv->hpd_event_bits |= (1 << i);
1398 1399 1400 1401 1402
		if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
				   dev_priv->hpd_stats[i].hpd_last_jiffies
				   + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
			dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
			dev_priv->hpd_stats[i].hpd_cnt = 0;
1403
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1404 1405
		} else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
			dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1406
			dev_priv->hpd_event_bits &= ~(1 << i);
1407
			DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1408
			storm_detected = true;
1409 1410
		} else {
			dev_priv->hpd_stats[i].hpd_cnt++;
1411 1412
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
				      dev_priv->hpd_stats[i].hpd_cnt);
1413 1414 1415
		}
	}

1416 1417
	if (storm_detected)
		dev_priv->display.hpd_irq_setup(dev);
1418
	spin_unlock(&dev_priv->irq_lock);
1419

1420 1421 1422 1423 1424 1425 1426
	/*
	 * Our hotplug handler can grab modeset locks (by calling down into the
	 * fb helpers). Hence it must not be run on our own dev-priv->wq work
	 * queue for otherwise the flush_work in the pageflip code will
	 * deadlock.
	 */
	schedule_work(&dev_priv->hotplug_work);
1427 1428
}

1429 1430
static void gmbus_irq_handler(struct drm_device *dev)
{
1431 1432 1433
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;

	wake_up_all(&dev_priv->gmbus_wait_queue);
1434 1435
}

1436 1437
static void dp_aux_irq_handler(struct drm_device *dev)
{
1438 1439 1440
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;

	wake_up_all(&dev_priv->gmbus_wait_queue);
1441 1442
}

1443
#if defined(CONFIG_DEBUG_FS)
1444 1445 1446 1447
static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
					 uint32_t crc0, uint32_t crc1,
					 uint32_t crc2, uint32_t crc3,
					 uint32_t crc4)
1448 1449 1450 1451
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1452
	int head, tail;
1453

1454 1455
	spin_lock(&pipe_crc->lock);

1456
	if (!pipe_crc->entries) {
1457
		spin_unlock(&pipe_crc->lock);
1458 1459 1460 1461
		DRM_ERROR("spurious interrupt\n");
		return;
	}

1462 1463
	head = pipe_crc->head;
	tail = pipe_crc->tail;
1464 1465

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1466
		spin_unlock(&pipe_crc->lock);
1467 1468 1469 1470 1471
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1472

1473
	entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1474 1475 1476 1477 1478
	entry->crc[0] = crc0;
	entry->crc[1] = crc1;
	entry->crc[2] = crc2;
	entry->crc[3] = crc3;
	entry->crc[4] = crc4;
1479 1480

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1481 1482 1483
	pipe_crc->head = head;

	spin_unlock(&pipe_crc->lock);
1484 1485

	wake_up_interruptible(&pipe_crc->wq);
1486
}
1487 1488 1489 1490 1491 1492 1493 1494
#else
static inline void
display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
			     uint32_t crc0, uint32_t crc1,
			     uint32_t crc2, uint32_t crc3,
			     uint32_t crc4) {}
#endif

1495

1496
static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
D
Daniel Vetter 已提交
1497 1498 1499
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1500 1501 1502
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     0, 0, 0, 0);
D
Daniel Vetter 已提交
1503 1504
}

1505
static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1506 1507 1508
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1509 1510 1511 1512 1513 1514
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1515
}
1516

1517
static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1518 1519
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530
	uint32_t res1, res2;

	if (INTEL_INFO(dev)->gen >= 3)
		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
	else
		res1 = 0;

	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
	else
		res2 = 0;
1531

1532 1533 1534 1535 1536
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_RED(pipe)),
				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
				     res1, res2);
1537
}
1538

1539 1540 1541 1542
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1543
{
1544
	if (pm_iir & GEN6_PM_RPS_EVENTS) {
1545
		spin_lock(&dev_priv->irq_lock);
1546
		dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1547
		snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1548
		spin_unlock(&dev_priv->irq_lock);
1549 1550

		queue_work(dev_priv->wq, &dev_priv->rps.work);
1551 1552
	}

1553 1554 1555
	if (HAS_VEBOX(dev_priv->dev)) {
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
			notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
B
Ben Widawsky 已提交
1556

1557
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1558 1559 1560
			i915_handle_error(dev_priv->dev, false,
					  "VEBOX CS error interrupt 0x%08x",
					  pm_iir);
1561
		}
B
Ben Widawsky 已提交
1562
	}
1563 1564
}

1565 1566 1567
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1568
	u32 pipe_stats[I915_MAX_PIPES] = { };
1569 1570
	int pipe;

1571
	spin_lock(&dev_priv->irq_lock);
1572
	for_each_pipe(pipe) {
1573
		int reg;
1574
		u32 mask, iir_bit = 0;
1575

1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598
		/*
		 * PIPESTAT bits get signalled even when the interrupt is
		 * disabled with the mask bits, and some of the status bits do
		 * not generate interrupts at all (like the underrun bit). Hence
		 * we need to be careful that we only handle what we want to
		 * handle.
		 */
		mask = 0;
		if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
			mask |= PIPE_FIFO_UNDERRUN_STATUS;

		switch (pipe) {
		case PIPE_A:
			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
			break;
		case PIPE_B:
			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
			break;
		}
		if (iir & iir_bit)
			mask |= dev_priv->pipestat_irq_mask[pipe];

		if (!mask)
1599 1600 1601
			continue;

		reg = PIPESTAT(pipe);
1602 1603
		mask |= PIPESTAT_INT_ENABLE_MASK;
		pipe_stats[pipe] = I915_READ(reg) & mask;
1604 1605 1606 1607

		/*
		 * Clear the PIPE*STAT regs before the IIR
		 */
1608 1609
		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
					PIPESTAT_INT_STATUS_MASK))
1610 1611
			I915_WRITE(reg, pipe_stats[pipe]);
	}
1612
	spin_unlock(&dev_priv->irq_lock);
1613 1614 1615 1616 1617

	for_each_pipe(pipe) {
		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
			drm_handle_vblank(dev, pipe);

1618
		if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip(dev, pipe);
		}

		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
			i9xx_pipe_crc_irq_handler(dev, pipe);

		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
		    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
	}

	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
		gmbus_irq_handler(dev);
}

1635
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;

	while (true) {
		iir = I915_READ(VLV_IIR);
		gt_iir = I915_READ(GTIIR);
		pm_iir = I915_READ(GEN6_PMIIR);

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

1652
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
J
Jesse Barnes 已提交
1653

1654
		valleyview_pipestat_irq_handler(dev, iir);
1655

J
Jesse Barnes 已提交
1656 1657 1658
		/* Consume port.  Then clear IIR or we'll miss events */
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1659
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
J
Jesse Barnes 已提交
1660

1661 1662
			intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);

1663 1664 1665
			if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
				dp_aux_irq_handler(dev);

J
Jesse Barnes 已提交
1666 1667 1668 1669 1670
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}


1671
		if (pm_iir)
1672
			gen6_rps_irq_handler(dev_priv, pm_iir);
J
Jesse Barnes 已提交
1673 1674 1675 1676 1677 1678 1679 1680 1681 1682

		I915_WRITE(GTIIR, gt_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		I915_WRITE(VLV_IIR, iir);
	}

out:
	return ret;
}

1683
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1684 1685
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1686
	int pipe;
1687
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1688

1689 1690
	intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);

1691 1692 1693
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1694
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1695 1696
				 port_name(port));
	}
1697

1698 1699 1700
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

1701
	if (pch_iir & SDE_GMBUS)
1702
		gmbus_irq_handler(dev);
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1713 1714 1715 1716 1717
	if (pch_iir & SDE_FDI_MASK)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1718 1719 1720 1721 1722 1723 1724 1725

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1726 1727
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
							  false))
1728
			DRM_ERROR("PCH transcoder A FIFO underrun\n");
1729 1730 1731 1732

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
							  false))
1733
			DRM_ERROR("PCH transcoder B FIFO underrun\n");
1734 1735 1736 1737 1738 1739
}

static void ivb_err_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 err_int = I915_READ(GEN7_ERR_INT);
D
Daniel Vetter 已提交
1740
	enum pipe pipe;
1741

1742 1743 1744
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

D
Daniel Vetter 已提交
1745 1746 1747 1748
	for_each_pipe(pipe) {
		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
								  false))
1749 1750
				DRM_ERROR("Pipe %c FIFO underrun\n",
					  pipe_name(pipe));
D
Daniel Vetter 已提交
1751
		}
1752

D
Daniel Vetter 已提交
1753 1754
		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
			if (IS_IVYBRIDGE(dev))
1755
				ivb_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1756
			else
1757
				hsw_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1758 1759
		}
	}
1760

1761 1762 1763 1764 1765 1766 1767 1768
	I915_WRITE(GEN7_ERR_INT, err_int);
}

static void cpt_serr_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 serr_int = I915_READ(SERR_INT);

1769 1770 1771
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1772 1773 1774
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
							  false))
1775
			DRM_ERROR("PCH transcoder A FIFO underrun\n");
1776 1777 1778 1779

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
							  false))
1780
			DRM_ERROR("PCH transcoder B FIFO underrun\n");
1781 1782 1783 1784

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
							  false))
1785
			DRM_ERROR("PCH transcoder C FIFO underrun\n");
1786 1787

	I915_WRITE(SERR_INT, serr_int);
1788 1789
}

1790 1791 1792 1793
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
1794
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1795

1796 1797
	intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);

1798 1799 1800 1801 1802 1803
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
1804 1805

	if (pch_iir & SDE_AUX_MASK_CPT)
1806
		dp_aux_irq_handler(dev);
1807 1808

	if (pch_iir & SDE_GMBUS_CPT)
1809
		gmbus_irq_handler(dev);
1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1822 1823 1824

	if (pch_iir & SDE_ERROR_CPT)
		cpt_serr_int_handler(dev);
1825 1826
}

1827 1828 1829
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1830
	enum pipe pipe;
1831 1832 1833 1834 1835 1836 1837 1838 1839 1840

	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE)
		intel_opregion_asle_intr(dev);

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

1841 1842 1843
	for_each_pipe(pipe) {
		if (de_iir & DE_PIPE_VBLANK(pipe))
			drm_handle_vblank(dev, pipe);
1844

1845 1846
		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1847 1848
				DRM_ERROR("Pipe %c FIFO underrun\n",
					  pipe_name(pipe));
1849

1850 1851
		if (de_iir & DE_PIPE_CRC_DONE(pipe))
			i9xx_pipe_crc_irq_handler(dev, pipe);
1852

1853 1854 1855 1856 1857
		/* plane/pipes map 1:1 on ilk+ */
		if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
		}
1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

	if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev);
}

1877 1878 1879
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1880
	enum pipe pipe;
1881 1882 1883 1884 1885 1886 1887 1888 1889 1890

	if (de_iir & DE_ERR_INT_IVB)
		ivb_err_int_handler(dev);

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE_IVB)
		intel_opregion_asle_intr(dev);

1891 1892 1893
	for_each_pipe(pipe) {
		if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
			drm_handle_vblank(dev, pipe);
1894 1895

		/* plane/pipes map 1:1 on ilk+ */
1896 1897 1898
		if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912
		}
	}

	/* check event from PCH */
	if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

1913
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1914 1915 1916
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1917
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1918
	irqreturn_t ret = IRQ_NONE;
1919

1920 1921
	/* We get interrupts on unclaimed registers, so check for this before we
	 * do any I915_{READ,WRITE}. */
1922
	intel_uncore_check_errors(dev);
1923

1924 1925 1926
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1927
	POSTING_READ(DEIER);
1928

1929 1930 1931 1932 1933
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
1934 1935 1936 1937 1938
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
1939

1940
	gt_iir = I915_READ(GTIIR);
1941
	if (gt_iir) {
1942
		if (INTEL_INFO(dev)->gen >= 6)
1943
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
1944 1945
		else
			ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1946 1947
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
1948 1949
	}

1950 1951
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
1952 1953 1954 1955
		if (INTEL_INFO(dev)->gen >= 7)
			ivb_display_irq_handler(dev, de_iir);
		else
			ilk_display_irq_handler(dev, de_iir);
1956 1957
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
1958 1959
	}

1960 1961 1962
	if (INTEL_INFO(dev)->gen >= 6) {
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
1963
			gen6_rps_irq_handler(dev_priv, pm_iir);
1964 1965 1966
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
		}
1967
	}
1968 1969 1970

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
1971 1972 1973 1974
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
1975 1976 1977 1978

	return ret;
}

1979 1980 1981 1982 1983 1984 1985
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl;
	irqreturn_t ret = IRQ_NONE;
	uint32_t tmp = 0;
1986
	enum pipe pipe;
1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

	master_ctl = I915_READ(GEN8_MASTER_IRQ);
	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
	if (!master_ctl)
		return IRQ_NONE;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);

	if (master_ctl & GEN8_DE_MISC_IRQ) {
		tmp = I915_READ(GEN8_DE_MISC_IIR);
		if (tmp & GEN8_DE_MISC_GSE)
			intel_opregion_asle_intr(dev);
		else if (tmp)
			DRM_ERROR("Unexpected DE Misc interrupt\n");
		else
			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");

		if (tmp) {
			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
			ret = IRQ_HANDLED;
		}
	}

2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027
	if (master_ctl & GEN8_DE_PORT_IRQ) {
		tmp = I915_READ(GEN8_DE_PORT_IIR);
		if (tmp & GEN8_AUX_CHANNEL_A)
			dp_aux_irq_handler(dev);
		else if (tmp)
			DRM_ERROR("Unexpected DE Port interrupt\n");
		else
			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");

		if (tmp) {
			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
			ret = IRQ_HANDLED;
		}
	}

2028 2029
	for_each_pipe(pipe) {
		uint32_t pipe_iir;
2030

2031 2032
		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
			continue;
2033

2034 2035 2036
		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (pipe_iir & GEN8_PIPE_VBLANK)
			drm_handle_vblank(dev, pipe);
2037

2038 2039 2040
		if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
2041
		}
2042

2043 2044 2045
		if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
			hsw_pipe_crc_irq_handler(dev, pipe);

2046 2047 2048
		if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
								  false))
2049 2050
				DRM_ERROR("Pipe %c FIFO underrun\n",
					  pipe_name(pipe));
2051 2052
		}

2053 2054 2055 2056 2057
		if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
				  pipe_name(pipe),
				  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
		}
2058 2059 2060 2061 2062

		if (pipe_iir) {
			ret = IRQ_HANDLED;
			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
		} else
2063 2064 2065
			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
	}

2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081
	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
		/*
		 * FIXME(BDW): Assume for now that the new interrupt handling
		 * scheme also closed the SDE interrupt handling race we've seen
		 * on older pch-split platforms. But this needs testing.
		 */
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		if (pch_iir) {
			I915_WRITE(SDEIIR, pch_iir);
			ret = IRQ_HANDLED;
		}
	}

2082 2083 2084 2085 2086 2087
	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return ret;
}

2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
			       bool reset_completed)
{
	struct intel_ring_buffer *ring;
	int i;

	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
	for_each_ring(ring, dev_priv, i)
		wake_up_all(&ring->irq_queue);

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);

	/*
	 * Signal tasks blocked in i915_gem_wait_for_error that the pending
	 * reset state is cleared.
	 */
	if (reset_completed)
		wake_up_all(&dev_priv->gpu_error.reset_queue);
}

2116 2117 2118 2119 2120 2121 2122 2123 2124
/**
 * i915_error_work_func - do process context error handling work
 * @work: work struct
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
static void i915_error_work_func(struct work_struct *work)
{
2125 2126 2127 2128
	struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
						    work);
	drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
						    gpu_error);
2129
	struct drm_device *dev = dev_priv->dev;
2130 2131 2132
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2133
	int ret;
2134

2135
	kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2136

2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2148
		DRM_DEBUG_DRIVER("resetting chip\n");
2149
		kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2150
				   reset_event);
2151

2152 2153 2154 2155 2156 2157
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
2158 2159
		ret = i915_reset(dev);

2160 2161
		intel_display_handle_reset(dev);

2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175
		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
			smp_mb__before_atomic_inc();
			atomic_inc(&dev_priv->gpu_error.reset_counter);

2176
			kobject_uevent_env(&dev->primary->kdev->kobj,
2177
					   KOBJ_CHANGE, reset_done_event);
2178
		} else {
M
Mika Kuoppala 已提交
2179
			atomic_set_mask(I915_WEDGED, &error->reset_counter);
2180
		}
2181

2182 2183 2184 2185 2186
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
		i915_error_wake_up(dev_priv, true);
2187
	}
2188 2189
}

2190
static void i915_report_and_clear_eir(struct drm_device *dev)
2191 2192
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2193
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2194
	u32 eir = I915_READ(EIR);
2195
	int pipe, i;
2196

2197 2198
	if (!eir)
		return;
2199

2200
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2201

2202 2203
	i915_get_extra_instdone(dev, instdone);

2204 2205 2206 2207
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2208 2209
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2210 2211
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2212 2213
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2214
			I915_WRITE(IPEIR_I965, ipeir);
2215
			POSTING_READ(IPEIR_I965);
2216 2217 2218
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2219 2220
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2221
			I915_WRITE(PGTBL_ER, pgtbl_err);
2222
			POSTING_READ(PGTBL_ER);
2223 2224 2225
		}
	}

2226
	if (!IS_GEN2(dev)) {
2227 2228
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2229 2230
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2231
			I915_WRITE(PGTBL_ER, pgtbl_err);
2232
			POSTING_READ(PGTBL_ER);
2233 2234 2235 2236
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2237
		pr_err("memory refresh error:\n");
2238
		for_each_pipe(pipe)
2239
			pr_err("pipe %c stat: 0x%08x\n",
2240
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2241 2242 2243
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2244 2245
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2246 2247
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2248
		if (INTEL_INFO(dev)->gen < 4) {
2249 2250
			u32 ipeir = I915_READ(IPEIR);

2251 2252 2253
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2254
			I915_WRITE(IPEIR, ipeir);
2255
			POSTING_READ(IPEIR);
2256 2257 2258
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2259 2260 2261 2262
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2263
			I915_WRITE(IPEIR_I965, ipeir);
2264
			POSTING_READ(IPEIR_I965);
2265 2266 2267 2268
		}
	}

	I915_WRITE(EIR, eir);
2269
	POSTING_READ(EIR);
2270 2271 2272 2273 2274 2275 2276 2277 2278 2279
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291
}

/**
 * i915_handle_error - handle an error interrupt
 * @dev: drm device
 *
 * Do some basic checking of regsiter state at error interrupt time and
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
2292 2293
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...)
2294 2295
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2296 2297
	va_list args;
	char error_msg[80];
2298

2299 2300 2301 2302 2303
	va_start(args, fmt);
	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
	va_end(args);

	i915_capture_error_state(dev, wedged, error_msg);
2304
	i915_report_and_clear_eir(dev);
2305

2306
	if (wedged) {
2307 2308
		atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
				&dev_priv->gpu_error.reset_counter);
2309

2310
		/*
2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321
		 * Wakeup waiting processes so that the reset work function
		 * i915_error_work_func doesn't deadlock trying to grab various
		 * locks. By bumping the reset counter first, the woken
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
2322
		 */
2323
		i915_error_wake_up(dev_priv, false);
2324 2325
	}

2326 2327 2328 2329 2330 2331 2332
	/*
	 * Our reset work can grab modeset locks (since it needs to reset the
	 * state of outstanding pagelips). Hence it must not be run on our own
	 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
	 * code will deadlock.
	 */
	schedule_work(&dev_priv->gpu_error.work);
2333 2334
}

2335
static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2336 2337 2338 2339
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2340
	struct drm_i915_gem_object *obj;
2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351
	struct intel_unpin_work *work;
	unsigned long flags;
	bool stall_detected;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;

2352 2353 2354
	if (work == NULL ||
	    atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
	    !work->enable_stall_check) {
2355 2356 2357 2358 2359 2360
		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

	/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2361
	obj = work->pending_flip_obj;
2362
	if (INTEL_INFO(dev)->gen >= 4) {
2363
		int dspsurf = DSPSURF(intel_crtc->plane);
2364
		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2365
					i915_gem_obj_ggtt_offset(obj);
2366
	} else {
2367
		int dspaddr = DSPADDR(intel_crtc->plane);
2368
		stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2369
							crtc->y * crtc->fb->pitches[0] +
2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380
							crtc->x * crtc->fb->bits_per_pixel/8);
	}

	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (stall_detected) {
		DRM_DEBUG_DRIVER("Pageflip stall detected\n");
		intel_prepare_page_flip(dev, intel_crtc->plane);
	}
}

2381 2382 2383
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2384
static int i915_enable_vblank(struct drm_device *dev, int pipe)
2385 2386
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2387
	unsigned long irqflags;
2388

2389
	if (!i915_pipe_enabled(dev, pipe))
2390
		return -EINVAL;
2391

2392
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2393
	if (INTEL_INFO(dev)->gen >= 4)
2394
		i915_enable_pipestat(dev_priv, pipe,
2395
				     PIPE_START_VBLANK_INTERRUPT_STATUS);
2396
	else
2397
		i915_enable_pipestat(dev_priv, pipe,
2398
				     PIPE_VBLANK_INTERRUPT_STATUS);
2399 2400

	/* maintain vblank delivery even in deep C-states */
2401
	if (INTEL_INFO(dev)->gen == 3)
2402
		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2403
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2404

2405 2406 2407
	return 0;
}

2408
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2409 2410 2411
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
2412
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2413
						     DE_PIPE_VBLANK(pipe);
2414 2415 2416 2417 2418

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2419
	ironlake_enable_display_irq(dev_priv, bit);
2420 2421 2422 2423 2424
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
2425 2426 2427 2428 2429 2430 2431 2432 2433
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2434
	i915_enable_pipestat(dev_priv, pipe,
2435
			     PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2436 2437 2438 2439 2440
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2441 2442 2443 2444 2445 2446 2447 2448 2449
static int gen8_enable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2450 2451 2452
	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2453 2454 2455 2456
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
	return 0;
}

2457 2458 2459
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2460
static void i915_disable_vblank(struct drm_device *dev, int pipe)
2461 2462
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2463
	unsigned long irqflags;
2464

2465
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2466
	if (INTEL_INFO(dev)->gen == 3)
2467
		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2468

2469
	i915_disable_pipestat(dev_priv, pipe,
2470 2471
			      PIPE_VBLANK_INTERRUPT_STATUS |
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
2472 2473 2474
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2475
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2476 2477 2478
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
2479
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2480
						     DE_PIPE_VBLANK(pipe);
2481 2482

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2483
	ironlake_disable_display_irq(dev_priv, bit);
2484 2485 2486
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
2487 2488 2489 2490 2491 2492
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2493
	i915_disable_pipestat(dev_priv, pipe,
2494
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2495 2496 2497
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2498 2499 2500 2501 2502 2503 2504 2505 2506
static void gen8_disable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2507 2508 2509
	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2510 2511 2512
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2513 2514
static u32
ring_last_seqno(struct intel_ring_buffer *ring)
2515
{
2516 2517 2518 2519
	return list_entry(ring->request_list.prev,
			  struct drm_i915_gem_request, list)->seqno;
}

2520 2521 2522 2523 2524
static bool
ring_idle(struct intel_ring_buffer *ring, u32 seqno)
{
	return (list_empty(&ring->request_list) ||
		i915_seqno_passed(seqno, ring_last_seqno(ring)));
B
Ben Gamari 已提交
2525 2526
}

2527 2528
static struct intel_ring_buffer *
semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2529 2530
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2531
	u32 cmd, ipehr, acthd, acthd_min;
2532 2533 2534 2535

	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
	if ((ipehr & ~(0x3 << 16)) !=
	    (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2536
		return NULL;
2537 2538 2539 2540

	/* ACTHD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX.
	 */
2541
	acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2542 2543 2544 2545 2546 2547 2548 2549
	acthd_min = max((int)acthd - 3 * 4, 0);
	do {
		cmd = ioread32(ring->virtual_start + acthd);
		if (cmd == ipehr)
			break;

		acthd -= 4;
		if (acthd < acthd_min)
2550
			return NULL;
2551 2552
	} while (1);

2553 2554
	*seqno = ioread32(ring->virtual_start+acthd+4)+1;
	return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2555 2556
}

2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585
static int semaphore_passed(struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	struct intel_ring_buffer *signaller;
	u32 seqno, ctl;

	ring->hangcheck.deadlock = true;

	signaller = semaphore_waits_for(ring, &seqno);
	if (signaller == NULL || signaller->hangcheck.deadlock)
		return -1;

	/* cursory check for an unkickable deadlock */
	ctl = I915_READ_CTL(signaller);
	if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
		return -1;

	return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
	struct intel_ring_buffer *ring;
	int i;

	for_each_ring(ring, dev_priv, i)
		ring->hangcheck.deadlock = false;
}

2586 2587
static enum intel_ring_hangcheck_action
ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2588 2589 2590
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2591 2592
	u32 tmp;

2593
	if (ring->hangcheck.acthd != acthd)
2594
		return HANGCHECK_ACTIVE;
2595

2596
	if (IS_GEN2(dev))
2597
		return HANGCHECK_HUNG;
2598 2599 2600 2601 2602 2603 2604

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
	tmp = I915_READ_CTL(ring);
2605
	if (tmp & RING_WAIT) {
2606 2607 2608
		i915_handle_error(dev, false,
				  "Kicking stuck wait on %s",
				  ring->name);
2609
		I915_WRITE_CTL(ring, tmp);
2610
		return HANGCHECK_KICK;
2611 2612 2613 2614 2615
	}

	if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
		switch (semaphore_passed(ring)) {
		default:
2616
			return HANGCHECK_HUNG;
2617
		case 1:
2618 2619 2620
			i915_handle_error(dev, false,
					  "Kicking stuck semaphore on %s",
					  ring->name);
2621
			I915_WRITE_CTL(ring, tmp);
2622
			return HANGCHECK_KICK;
2623
		case 0:
2624
			return HANGCHECK_WAIT;
2625
		}
2626
	}
2627

2628
	return HANGCHECK_HUNG;
2629 2630
}

B
Ben Gamari 已提交
2631 2632
/**
 * This is called when the chip hasn't reported back with completed
2633 2634 2635 2636 2637
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
2638
 */
2639
static void i915_hangcheck_elapsed(unsigned long data)
B
Ben Gamari 已提交
2640 2641 2642
{
	struct drm_device *dev = (struct drm_device *)data;
	drm_i915_private_t *dev_priv = dev->dev_private;
2643 2644
	struct intel_ring_buffer *ring;
	int i;
2645
	int busy_count = 0, rings_hung = 0;
2646 2647 2648 2649
	bool stuck[I915_NUM_RINGS] = { 0 };
#define BUSY 1
#define KICK 5
#define HUNG 20
2650

2651
	if (!i915.enable_hangcheck)
2652 2653
		return;

2654
	for_each_ring(ring, dev_priv, i) {
2655
		u32 seqno, acthd;
2656
		bool busy = true;
2657

2658 2659
		semaphore_clear_deadlocks(dev_priv);

2660 2661
		seqno = ring->get_seqno(ring, false);
		acthd = intel_ring_get_active_head(ring);
2662

2663 2664
		if (ring->hangcheck.seqno == seqno) {
			if (ring_idle(ring, seqno)) {
2665 2666
				ring->hangcheck.action = HANGCHECK_IDLE;

2667 2668
				if (waitqueue_active(&ring->irq_queue)) {
					/* Issue a wake-up to catch stuck h/w. */
2669
					if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2670 2671 2672 2673 2674 2675
						if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
							DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
								  ring->name);
						else
							DRM_INFO("Fake missed irq on %s\n",
								 ring->name);
2676 2677 2678 2679
						wake_up_all(&ring->irq_queue);
					}
					/* Safeguard against driver failure */
					ring->hangcheck.score += BUSY;
2680 2681
				} else
					busy = false;
2682
			} else {
2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
2698 2699 2700 2701
				ring->hangcheck.action = ring_stuck(ring,
								    acthd);

				switch (ring->hangcheck.action) {
2702
				case HANGCHECK_IDLE:
2703
				case HANGCHECK_WAIT:
2704
					break;
2705
				case HANGCHECK_ACTIVE:
2706
					ring->hangcheck.score += BUSY;
2707
					break;
2708
				case HANGCHECK_KICK:
2709
					ring->hangcheck.score += KICK;
2710
					break;
2711
				case HANGCHECK_HUNG:
2712
					ring->hangcheck.score += HUNG;
2713 2714 2715
					stuck[i] = true;
					break;
				}
2716
			}
2717
		} else {
2718 2719
			ring->hangcheck.action = HANGCHECK_ACTIVE;

2720 2721 2722 2723 2724
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
			if (ring->hangcheck.score > 0)
				ring->hangcheck.score--;
2725 2726
		}

2727 2728
		ring->hangcheck.seqno = seqno;
		ring->hangcheck.acthd = acthd;
2729
		busy_count += busy;
2730
	}
2731

2732
	for_each_ring(ring, dev_priv, i) {
2733
		if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2734 2735 2736
			DRM_INFO("%s on %s\n",
				 stuck[i] ? "stuck" : "no progress",
				 ring->name);
2737
			rings_hung++;
2738 2739 2740
		}
	}

2741
	if (rings_hung)
2742
		return i915_handle_error(dev, true, "Ring hung");
B
Ben Gamari 已提交
2743

2744 2745 2746
	if (busy_count)
		/* Reset timer case chip hangs without another request
		 * being added */
2747 2748 2749 2750 2751 2752
		i915_queue_hangcheck(dev);
}

void i915_queue_hangcheck(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2753
	if (!i915.enable_hangcheck)
2754 2755 2756 2757
		return;

	mod_timer(&dev_priv->gpu_error.hangcheck_timer,
		  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
2758 2759
}

P
Paulo Zanoni 已提交
2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778
static void ibx_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

	/* south display irq */
	I915_WRITE(SDEIMR, 0xffffffff);
	/*
	 * SDEIER is also touched by the interrupt handler to work around missed
	 * PCH interrupts. Hence we can't update it after the interrupt handler
	 * is enabled - instead we unconditionally enable all PCH interrupt
	 * sources here, but then only unmask them as needed with SDEIMR.
	 */
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795
static void gen5_gt_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* and GT */
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	POSTING_READ(GTIER);

	if (INTEL_INFO(dev)->gen >= 6) {
		/* and PM */
		I915_WRITE(GEN6_PMIMR, 0xffffffff);
		I915_WRITE(GEN6_PMIER, 0x0);
		POSTING_READ(GEN6_PMIER);
	}
}

L
Linus Torvalds 已提交
2796 2797
/* drm_dma.h hooks
*/
2798
static void ironlake_irq_preinstall(struct drm_device *dev)
2799 2800 2801 2802
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	I915_WRITE(HWSTAM, 0xeffe);
2803

2804 2805
	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
2806
	POSTING_READ(DEIER);
2807

2808
	gen5_gt_irq_preinstall(dev);
2809

P
Paulo Zanoni 已提交
2810
	ibx_irq_preinstall(dev);
2811 2812
}

J
Jesse Barnes 已提交
2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826
static void valleyview_irq_preinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

	/* and GT */
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIIR, I915_READ(GTIIR));
2827 2828

	gen5_gt_irq_preinstall(dev);
J
Jesse Barnes 已提交
2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841

	I915_WRITE(DPINVGTT, 0xff);

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884
static void gen8_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

	/* IIR can theoretically queue up two events. Be paranoid */
#define GEN8_IRQ_INIT_NDX(type, which) do { \
		I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
		POSTING_READ(GEN8_##type##_IMR(which)); \
		I915_WRITE(GEN8_##type##_IER(which), 0); \
		I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
		POSTING_READ(GEN8_##type##_IIR(which)); \
		I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	} while (0)

#define GEN8_IRQ_INIT(type) do { \
		I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
		POSTING_READ(GEN8_##type##_IMR); \
		I915_WRITE(GEN8_##type##_IER, 0); \
		I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
		POSTING_READ(GEN8_##type##_IIR); \
		I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
	} while (0)

	GEN8_IRQ_INIT_NDX(GT, 0);
	GEN8_IRQ_INIT_NDX(GT, 1);
	GEN8_IRQ_INIT_NDX(GT, 2);
	GEN8_IRQ_INIT_NDX(GT, 3);

	for_each_pipe(pipe) {
		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
	}

	GEN8_IRQ_INIT(DE_PORT);
	GEN8_IRQ_INIT(DE_MISC);
	GEN8_IRQ_INIT(PCU);
#undef GEN8_IRQ_INIT
#undef GEN8_IRQ_INIT_NDX

	POSTING_READ(GEN8_PCU_IIR);
2885 2886

	ibx_irq_preinstall(dev);
2887 2888
}

2889
static void ibx_hpd_irq_setup(struct drm_device *dev)
2890 2891
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2892 2893
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *intel_encoder;
2894
	u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2895 2896

	if (HAS_PCH_IBX(dev)) {
2897
		hotplug_irqs = SDE_HOTPLUG_MASK;
2898
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2899
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2900
				enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2901
	} else {
2902
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2903
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2904
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2905
				enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2906
	}
2907

2908
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2909 2910 2911 2912 2913 2914 2915

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
	 *
	 * This register is the same on all known PCH chips.
	 */
2916 2917 2918 2919 2920 2921 2922 2923
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

P
Paulo Zanoni 已提交
2924 2925 2926
static void ibx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2927
	u32 mask;
2928

D
Daniel Vetter 已提交
2929 2930 2931
	if (HAS_PCH_NOP(dev))
		return;

2932 2933
	if (HAS_PCH_IBX(dev)) {
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2934
		       SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2935 2936 2937 2938 2939
	} else {
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;

		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
	}
2940

P
Paulo Zanoni 已提交
2941 2942 2943 2944
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
	I915_WRITE(SDEIMR, ~mask);
}

2945 2946 2947 2948 2949 2950 2951 2952
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
2953
	if (HAS_L3_DPF(dev)) {
2954
		/* L3 parity interrupt is always unmasked. */
2955 2956
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
		gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
			   ILK_BSD_USER_INTERRUPT;
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	I915_WRITE(GTIER, gt_irqs);
	POSTING_READ(GTIER);

	if (INTEL_INFO(dev)->gen >= 6) {
		pm_irqs |= GEN6_PM_RPS_EVENTS;

		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

2978
		dev_priv->pm_irq_mask = 0xffffffff;
2979
		I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2980
		I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2981 2982 2983 2984 2985
		I915_WRITE(GEN6_PMIER, pm_irqs);
		POSTING_READ(GEN6_PMIER);
	}
}

2986
static int ironlake_irq_postinstall(struct drm_device *dev)
2987
{
2988
	unsigned long irqflags;
2989
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
				DE_ERR_INT_IVB);
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
			      DE_PIPEA_VBLANK_IVB);

		I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3005 3006 3007 3008
				DE_AUX_CHANNEL_A |
				DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
				DE_POISON);
3009 3010
		extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
	}
3011

3012
	dev_priv->irq_mask = ~display_mask;
3013 3014 3015

	/* should always can generate irq */
	I915_WRITE(DEIIR, I915_READ(DEIIR));
3016
	I915_WRITE(DEIMR, dev_priv->irq_mask);
3017
	I915_WRITE(DEIER, display_mask | extra_mask);
3018
	POSTING_READ(DEIER);
3019

3020
	gen5_gt_irq_postinstall(dev);
3021

P
Paulo Zanoni 已提交
3022
	ibx_irq_postinstall(dev);
3023

3024
	if (IS_IRONLAKE_M(dev)) {
3025 3026 3027
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
3028 3029 3030
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3031
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3032
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3033 3034
	}

3035 3036 3037
	return 0;
}

3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124
static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;

	I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
	I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
	POSTING_READ(PIPESTAT(PIPE_A));

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

	i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
					       PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
	dev_priv->irq_mask &= ~iir_mask;

	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
	POSTING_READ(VLV_IER);
}

static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;

	dev_priv->irq_mask |= iir_mask;
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	POSTING_READ(VLV_IIR);

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

	i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
					        PIPE_GMBUS_INTERRUPT_STATUS);
	i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;
	I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
	I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
	POSTING_READ(PIPESTAT(PIPE_A));
}

void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = true;

	if (dev_priv->dev->irq_enabled)
		valleyview_display_irqs_install(dev_priv);
}

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (!dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = false;

	if (dev_priv->dev->irq_enabled)
		valleyview_display_irqs_uninstall(dev_priv);
}

J
Jesse Barnes 已提交
3125 3126 3127
static int valleyview_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3128
	unsigned long irqflags;
J
Jesse Barnes 已提交
3129

3130
	dev_priv->irq_mask = ~0;
J
Jesse Barnes 已提交
3131

3132 3133 3134
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
3135
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3136
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
J
Jesse Barnes 已提交
3137 3138 3139
	I915_WRITE(VLV_IIR, 0xffffffff);
	POSTING_READ(VLV_IER);

3140 3141 3142
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3143 3144
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_install(dev_priv);
3145
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3146

J
Jesse Barnes 已提交
3147 3148 3149
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IIR, 0xffffffff);

3150
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
3151 3152 3153 3154 3155 3156 3157 3158

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3159 3160 3161 3162

	return 0;
}

3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
	int i;

	/* These are interrupts we'll toggle with the ring mask register */
	uint32_t gt_interrupts[] = {
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
		0,
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
		};

	for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
		u32 tmp = I915_READ(GEN8_GT_IIR(i));
		if (tmp)
			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
				  i, tmp);
		I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
		I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
	}
	POSTING_READ(GEN8_GT_IER(0));
}

static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
3192 3193 3194 3195 3196
	uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
		GEN8_PIPE_CDCLK_CRC_DONE |
		GEN8_PIPE_FIFO_UNDERRUN |
		GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
	uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
3197
	int pipe;
3198 3199 3200
	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211

	for_each_pipe(pipe) {
		u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (tmp)
			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
				  pipe, tmp);
		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
		I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
	}
	POSTING_READ(GEN8_DE_PIPE_ISR(0));

3212 3213
	I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
	I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271
	POSTING_READ(GEN8_DE_PORT_IER);
}

static int gen8_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	gen8_gt_irq_postinstall(dev_priv);
	gen8_de_irq_postinstall(dev_priv);

	ibx_irq_postinstall(dev);

	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

static void gen8_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

	I915_WRITE(GEN8_MASTER_IRQ, 0);

#define GEN8_IRQ_FINI_NDX(type, which) do { \
		I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
		I915_WRITE(GEN8_##type##_IER(which), 0); \
		I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	} while (0)

#define GEN8_IRQ_FINI(type) do { \
		I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
		I915_WRITE(GEN8_##type##_IER, 0); \
		I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
	} while (0)

	GEN8_IRQ_FINI_NDX(GT, 0);
	GEN8_IRQ_FINI_NDX(GT, 1);
	GEN8_IRQ_FINI_NDX(GT, 2);
	GEN8_IRQ_FINI_NDX(GT, 3);

	for_each_pipe(pipe) {
		GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
	}

	GEN8_IRQ_FINI(DE_PORT);
	GEN8_IRQ_FINI(DE_MISC);
	GEN8_IRQ_FINI(PCU);
#undef GEN8_IRQ_FINI
#undef GEN8_IRQ_FINI_NDX

	POSTING_READ(GEN8_PCU_IIR);
}

J
Jesse Barnes 已提交
3272 3273 3274
static void valleyview_irq_uninstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3275
	unsigned long irqflags;
J
Jesse Barnes 已提交
3276 3277 3278 3279 3280
	int pipe;

	if (!dev_priv)
		return;

3281
	intel_hpd_irq_uninstall(dev_priv);
3282

J
Jesse Barnes 已提交
3283 3284 3285 3286 3287 3288
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	I915_WRITE(HWSTAM, 0xffffffff);
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3289 3290 3291 3292 3293 3294 3295 3296

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_uninstall(dev_priv);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	dev_priv->irq_mask = 0;

J
Jesse Barnes 已提交
3297 3298 3299 3300 3301 3302
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

3303
static void ironlake_irq_uninstall(struct drm_device *dev)
3304 3305
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3306 3307 3308 3309

	if (!dev_priv)
		return;

3310
	intel_hpd_irq_uninstall(dev_priv);
3311

3312 3313 3314 3315 3316
	I915_WRITE(HWSTAM, 0xffffffff);

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
	I915_WRITE(DEIIR, I915_READ(DEIIR));
3317 3318
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3319 3320 3321 3322

	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	I915_WRITE(GTIIR, I915_READ(GTIIR));
3323

3324 3325 3326
	if (HAS_PCH_NOP(dev))
		return;

3327 3328 3329
	I915_WRITE(SDEIMR, 0xffffffff);
	I915_WRITE(SDEIER, 0x0);
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3330 3331
	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3332 3333
}

3334
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
3335 3336
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3337
	int pipe;
3338

3339 3340
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
3341 3342 3343
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
3344 3345 3346 3347 3348
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3349
	unsigned long irqflags;
C
Chris Wilson 已提交
3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

3370 3371 3372
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3373 3374
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3375 3376
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

C
Chris Wilson 已提交
3377 3378 3379
	return 0;
}

3380 3381 3382 3383
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
3384
			       int plane, int pipe, u32 iir)
3385 3386
{
	drm_i915_private_t *dev_priv = dev->dev_private;
3387
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3388 3389 3390 3391 3392 3393 3394

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

3395
	intel_prepare_page_flip(dev, plane);
3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

3411
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u16 iir, new_iir;
	u32 pipe_stats[2];
	unsigned long irqflags;
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3435 3436 3437
			i915_handle_error(dev, false,
					  "Command parser error, iir 0x%08x",
					  iir);
C
Chris Wilson 已提交
3438 3439 3440 3441 3442 3443 3444 3445

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
3446
			if (pipe_stats[pipe] & 0x8000ffff)
C
Chris Wilson 已提交
3447 3448 3449 3450 3451 3452 3453
				I915_WRITE(reg, pipe_stats[pipe]);
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

3454
		i915_update_dri1_breadcrumb(dev);
C
Chris Wilson 已提交
3455 3456 3457 3458

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

3459
		for_each_pipe(pipe) {
3460
			int plane = pipe;
3461
			if (HAS_FBC(dev))
3462 3463
				plane = !plane;

3464
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3465 3466
			    i8xx_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
C
Chris Wilson 已提交
3467

3468
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3469
				i9xx_pipe_crc_irq_handler(dev, pipe);
3470 3471 3472

			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3473
				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3474
		}
C
Chris Wilson 已提交
3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

3497 3498 3499 3500 3501 3502 3503 3504 3505 3506
static void i915_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3507
	I915_WRITE16(HWSTAM, 0xeffe);
3508 3509 3510 3511 3512 3513 3514 3515 3516 3517
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3518
	u32 enable_mask;
3519
	unsigned long irqflags;
3520

3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		I915_USER_INTERRUPT;

3539
	if (I915_HAS_HOTPLUG(dev)) {
3540 3541 3542
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);

3543 3544 3545 3546 3547 3548 3549 3550 3551 3552
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3553
	i915_enable_asle_pipestat(dev);
3554

3555 3556 3557
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3558 3559
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3560 3561
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

3562 3563 3564
	return 0;
}

3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

	intel_prepare_page_flip(dev, plane);

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

3596
static irqreturn_t i915_irq_handler(int irq, void *arg)
3597 3598 3599
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3600
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3601
	unsigned long irqflags;
3602 3603 3604 3605
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
3606 3607

	iir = I915_READ(IIR);
3608 3609
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
3610
		bool blc_event = false;
3611 3612 3613 3614 3615 3616 3617 3618

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3619 3620 3621
			i915_handle_error(dev, false,
					  "Command parser error, iir 0x%08x",
					  iir);
3622 3623 3624 3625 3626

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

3627
			/* Clear the PIPE*STAT regs before the IIR */
3628 3629
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
3630
				irq_received = true;
3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
		if ((I915_HAS_HOTPLUG(dev)) &&
		    (iir & I915_DISPLAY_PORT_INTERRUPT)) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3642
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3643

3644 3645
			intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);

3646
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3647
			POSTING_READ(PORT_HOTPLUG_STAT);
3648 3649
		}

3650
		I915_WRITE(IIR, iir & ~flip_mask);
3651 3652 3653 3654 3655 3656
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		for_each_pipe(pipe) {
3657
			int plane = pipe;
3658
			if (HAS_FBC(dev))
3659
				plane = !plane;
3660

3661
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3662 3663
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3664 3665 3666

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
3667 3668

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3669
				i9xx_pipe_crc_irq_handler(dev, pipe);
3670 3671 3672

			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3673
				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
3694
		ret = IRQ_HANDLED;
3695
		iir = new_iir;
3696
	} while (iir & ~flip_mask);
3697

3698
	i915_update_dri1_breadcrumb(dev);
3699

3700 3701 3702 3703 3704 3705 3706 3707
	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

3708
	intel_hpd_irq_uninstall(dev_priv);
3709

3710 3711 3712 3713 3714
	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3715
	I915_WRITE16(HWSTAM, 0xffff);
3716 3717
	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
3718
		I915_WRITE(PIPESTAT(pipe), 0);
3719 3720
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

3732 3733
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745

	I915_WRITE(HWSTAM, 0xeffe);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3746
	u32 enable_mask;
3747
	u32 error_mask;
3748
	unsigned long irqflags;
3749 3750

	/* Unmask the interrupts that we always want on. */
3751
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3752
			       I915_DISPLAY_PORT_INTERRUPT |
3753 3754 3755 3756 3757 3758 3759
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
3760 3761
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3762 3763 3764 3765
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
3766

3767 3768 3769
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3770 3771 3772
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3773
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3794 3795 3796
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

3797
	i915_enable_asle_pipestat(dev);
3798 3799 3800 3801

	return 0;
}

3802
static void i915_hpd_irq_setup(struct drm_device *dev)
3803 3804
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3805
	struct drm_mode_config *mode_config = &dev->mode_config;
3806
	struct intel_encoder *intel_encoder;
3807 3808
	u32 hotplug_en;

3809 3810
	assert_spin_locked(&dev_priv->irq_lock);

3811 3812 3813 3814
	if (I915_HAS_HOTPLUG(dev)) {
		hotplug_en = I915_READ(PORT_HOTPLUG_EN);
		hotplug_en &= ~HOTPLUG_INT_EN_MASK;
		/* Note HDMI and DP share hotplug bits */
3815
		/* enable bits are the same for all generations */
3816 3817 3818
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
				hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3819 3820 3821 3822 3823 3824
		/* Programming the CRT detection parameters tends
		   to generate a spurious hotplug event about three
		   seconds later.  So just do it once.
		*/
		if (IS_G4X(dev))
			hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3825
		hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3826
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3827

3828 3829 3830
		/* Ignore TV since it's buggy */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}
3831 3832
}

3833
static irqreturn_t i965_irq_handler(int irq, void *arg)
3834 3835 3836 3837 3838 3839 3840
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	unsigned long irqflags;
	int ret = IRQ_NONE, pipe;
3841 3842 3843
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3844 3845 3846 3847

	iir = I915_READ(IIR);

	for (;;) {
3848
		bool irq_received = (iir & ~flip_mask) != 0;
3849 3850
		bool blc_event = false;

3851 3852 3853 3854 3855 3856 3857
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3858 3859 3860
			i915_handle_error(dev, false,
					  "Command parser error, iir 0x%08x",
					  iir);
3861 3862 3863 3864 3865 3866 3867 3868 3869 3870

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
3871
				irq_received = true;
3872 3873 3874 3875 3876 3877 3878 3879 3880 3881
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
3882
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3883
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3884 3885
			u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
								  HOTPLUG_INT_STATUS_G4X :
3886
								  HOTPLUG_INT_STATUS_I915);
3887

3888
			intel_hpd_irq_handler(dev, hotplug_trigger,
3889
					      IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3890

3891 3892 3893 3894
			if (IS_G4X(dev) &&
			    (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
				dp_aux_irq_handler(dev);

3895 3896 3897 3898
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}

3899
		I915_WRITE(IIR, iir & ~flip_mask);
3900 3901 3902 3903 3904 3905 3906 3907
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
		if (iir & I915_BSD_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[VCS]);

		for_each_pipe(pipe) {
3908
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3909 3910
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3911 3912 3913

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
3914 3915

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3916
				i9xx_pipe_crc_irq_handler(dev, pipe);
3917

3918 3919
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3920
				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3921
		}
3922 3923 3924 3925

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

3926 3927 3928
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

3947
	i915_update_dri1_breadcrumb(dev);
3948

3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959
	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

3960
	intel_hpd_irq_uninstall(dev_priv);
3961

3962 3963
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976

	I915_WRITE(HWSTAM, 0xffffffff);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

3977
static void intel_hpd_irq_reenable(unsigned long data)
3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
	struct drm_device *dev = dev_priv->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	unsigned long irqflags;
	int i;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
		struct drm_connector *connector;

		if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
			continue;

		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;

		list_for_each_entry(connector, &mode_config->connector_list, head) {
			struct intel_connector *intel_connector = to_intel_connector(connector);

			if (intel_connector->encoder->hpd_pin == i) {
				if (connector->polled != intel_connector->polled)
					DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
							 drm_get_connector_name(connector));
				connector->polled = intel_connector->polled;
				if (!connector->polled)
					connector->polled = DRM_CONNECTOR_POLL_HPD;
			}
		}
	}
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

4012 4013
void intel_irq_init(struct drm_device *dev)
{
4014 4015 4016
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4017
	INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4018
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4019
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4020

4021 4022
	setup_timer(&dev_priv->gpu_error.hangcheck_timer,
		    i915_hangcheck_elapsed,
4023
		    (unsigned long) dev);
4024
	setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4025
		    (unsigned long) dev_priv);
4026

4027
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4028

4029 4030 4031 4032
	if (IS_GEN2(dev)) {
		dev->max_vblank_count = 0;
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
	} else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4033 4034
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4035 4036 4037
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4038 4039
	}

4040
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4041
		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4042 4043
		dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
	}
4044

J
Jesse Barnes 已提交
4045 4046 4047 4048 4049 4050 4051
	if (IS_VALLEYVIEW(dev)) {
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
4052
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4053 4054 4055 4056 4057 4058 4059 4060
	} else if (IS_GEN8(dev)) {
		dev->driver->irq_handler = gen8_irq_handler;
		dev->driver->irq_preinstall = gen8_irq_preinstall;
		dev->driver->irq_postinstall = gen8_irq_postinstall;
		dev->driver->irq_uninstall = gen8_irq_uninstall;
		dev->driver->enable_vblank = gen8_enable_vblank;
		dev->driver->disable_vblank = gen8_disable_vblank;
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4061 4062 4063 4064 4065 4066 4067
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
4068
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4069
	} else {
C
Chris Wilson 已提交
4070 4071 4072 4073 4074
		if (INTEL_INFO(dev)->gen == 2) {
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
4075 4076 4077 4078 4079
		} else if (INTEL_INFO(dev)->gen == 3) {
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
4080
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
4081
		} else {
4082 4083 4084 4085
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
4086
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
4087
		}
4088 4089 4090 4091
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
4092 4093 4094 4095

void intel_hpd_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4096 4097
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_connector *connector;
4098
	unsigned long irqflags;
4099
	int i;
4100

4101 4102 4103 4104 4105 4106 4107 4108 4109 4110
	for (i = 1; i < HPD_NUM_PINS; i++) {
		dev_priv->hpd_stats[i].hpd_cnt = 0;
		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
	}
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		struct intel_connector *intel_connector = to_intel_connector(connector);
		connector->polled = intel_connector->polled;
		if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
			connector->polled = DRM_CONNECTOR_POLL_HPD;
	}
4111 4112 4113 4114

	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked checks happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4115 4116
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
4117
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4118
}
4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133

/* Disable interrupts so we can allow Package C8+. */
void hsw_pc8_disable_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

	dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
	dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
	dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
	dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
	dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);

4134 4135
	ironlake_disable_display_irq(dev_priv, 0xffffffff);
	ibx_disable_display_interrupt(dev_priv, 0xffffffff);
4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148
	ilk_disable_gt_irq(dev_priv, 0xffffffff);
	snb_disable_pm_irq(dev_priv, 0xffffffff);

	dev_priv->pc8.irqs_disabled = true;

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

/* Restore interrupts so we can recover from Package C8+. */
void hsw_pc8_restore_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;
4149
	uint32_t val;
4150 4151 4152 4153

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

	val = I915_READ(DEIMR);
4154
	WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
4155

4156 4157
	val = I915_READ(SDEIMR);
	WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
4158 4159

	val = I915_READ(GTIMR);
4160
	WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
4161 4162

	val = I915_READ(GEN6_PMIMR);
4163
	WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
4164 4165 4166 4167

	dev_priv->pc8.irqs_disabled = false;

	ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
4168
	ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
4169 4170 4171 4172 4173 4174
	ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
	snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
	I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}