spi-imx.c 32.8 KB
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/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2008 Juergen Beisert
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the
 * Free Software Foundation
 * 51 Franklin Street, Fifth Floor
 * Boston, MA  02110-1301, USA.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
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#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
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#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/types.h>
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#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/platform_data/spi-imx.h>
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#define DRIVER_NAME "spi_imx"

#define MXC_CSPIRXDATA		0x00
#define MXC_CSPITXDATA		0x04
#define MXC_CSPICTRL		0x08
#define MXC_CSPIINT		0x0c
#define MXC_RESET		0x1c

/* generic defines to abstract from the different register layouts */
#define MXC_INT_RR	(1 << 0) /* Receive data ready interrupt */
#define MXC_INT_TE	(1 << 1) /* Transmit FIFO empty interrupt */

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/* The maximum  bytes that a sdma BD can transfer.*/
#define MAX_SDMA_BD_BYTES  (1 << 15)
#define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000))
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struct spi_imx_config {
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	unsigned int speed_hz;
	unsigned int bpw;
	unsigned int mode;
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	u8 cs;
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};

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enum spi_imx_devtype {
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	IMX1_CSPI,
	IMX21_CSPI,
	IMX27_CSPI,
	IMX31_CSPI,
	IMX35_CSPI,	/* CSPI on all i.mx except above */
	IMX51_ECSPI,	/* ECSPI on i.mx51 and later */
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};

struct spi_imx_data;

struct spi_imx_devtype_data {
	void (*intctrl)(struct spi_imx_data *, int);
	int (*config)(struct spi_imx_data *, struct spi_imx_config *);
	void (*trigger)(struct spi_imx_data *);
	int (*rx_available)(struct spi_imx_data *);
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	void (*reset)(struct spi_imx_data *);
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	enum spi_imx_devtype devtype;
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};

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struct spi_imx_data {
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	struct spi_bitbang bitbang;

	struct completion xfer_done;
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	void __iomem *base;
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	struct clk *clk_per;
	struct clk *clk_ipg;
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	unsigned long spi_clk;

	unsigned int count;
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	void (*tx)(struct spi_imx_data *);
	void (*rx)(struct spi_imx_data *);
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	void *rx_buf;
	const void *tx_buf;
	unsigned int txfifo; /* number of words pushed in tx FIFO */

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	/* DMA */
	unsigned int dma_is_inited;
	unsigned int dma_finished;
	bool usedma;
	u32 rx_wml;
	u32 tx_wml;
	u32 rxt_wml;
	struct completion dma_rx_completion;
	struct completion dma_tx_completion;

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	const struct spi_imx_devtype_data *devtype_data;
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	int chipselect[0];
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};

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static inline int is_imx27_cspi(struct spi_imx_data *d)
{
	return d->devtype_data->devtype == IMX27_CSPI;
}

static inline int is_imx35_cspi(struct spi_imx_data *d)
{
	return d->devtype_data->devtype == IMX35_CSPI;
}

static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
{
	return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
}

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#define MXC_SPI_BUF_RX(type)						\
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static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)		\
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{									\
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	unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);	\
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									\
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	if (spi_imx->rx_buf) {						\
		*(type *)spi_imx->rx_buf = val;				\
		spi_imx->rx_buf += sizeof(type);			\
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	}								\
}

#define MXC_SPI_BUF_TX(type)						\
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static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)		\
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{									\
	type val = 0;							\
									\
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	if (spi_imx->tx_buf) {						\
		val = *(type *)spi_imx->tx_buf;				\
		spi_imx->tx_buf += sizeof(type);			\
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	}								\
									\
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	spi_imx->count -= sizeof(type);					\
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									\
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	writel(val, spi_imx->base + MXC_CSPITXDATA);			\
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}

MXC_SPI_BUF_RX(u8)
MXC_SPI_BUF_TX(u8)
MXC_SPI_BUF_RX(u16)
MXC_SPI_BUF_TX(u16)
MXC_SPI_BUF_RX(u32)
MXC_SPI_BUF_TX(u32)

/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 * (which is currently not the case in this driver)
 */
static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
	256, 384, 512, 768, 1024};

/* MX21, MX27 */
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static unsigned int spi_imx_clkdiv_1(unsigned int fin,
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		unsigned int fspi, unsigned int max)
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{
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	int i;
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	for (i = 2; i < max; i++)
		if (fspi * mxc_clkdivs[i] >= fin)
			return i;

	return max;
}

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/* MX1, MX31, MX35, MX51 CSPI */
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static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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		unsigned int fspi)
{
	int i, div = 4;

	for (i = 0; i < 7; i++) {
		if (fspi * div >= fin)
			return i;
		div <<= 1;
	}

	return 7;
}

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static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
			 struct spi_transfer *transfer)
{
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);

	if (spi_imx->dma_is_inited && (transfer->len > spi_imx->rx_wml)
	    && (transfer->len > spi_imx->tx_wml))
		return true;
	return false;
}

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#define MX51_ECSPI_CTRL		0x08
#define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)
#define MX51_ECSPI_CTRL_XCH		(1 <<  2)
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#define MX51_ECSPI_CTRL_SMC		(1 << 3)
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#define MX51_ECSPI_CTRL_MODE_MASK	(0xf << 4)
#define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8
#define MX51_ECSPI_CTRL_PREDIV_OFFSET	12
#define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)
#define MX51_ECSPI_CTRL_BL_OFFSET	20

#define MX51_ECSPI_CONFIG	0x0c
#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
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#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
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#define MX51_ECSPI_INT		0x10
#define MX51_ECSPI_INT_TEEN		(1 <<  0)
#define MX51_ECSPI_INT_RREN		(1 <<  3)

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#define MX51_ECSPI_DMA      0x14
#define MX51_ECSPI_DMA_TX_WML_OFFSET	0
#define MX51_ECSPI_DMA_TX_WML_MASK	0x3F
#define MX51_ECSPI_DMA_RX_WML_OFFSET	16
#define MX51_ECSPI_DMA_RX_WML_MASK	(0x3F << 16)
#define MX51_ECSPI_DMA_RXT_WML_OFFSET	24
#define MX51_ECSPI_DMA_RXT_WML_MASK	(0x3F << 24)

#define MX51_ECSPI_DMA_TEDEN_OFFSET	7
#define MX51_ECSPI_DMA_RXDEN_OFFSET	23
#define MX51_ECSPI_DMA_RXTDEN_OFFSET	31

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#define MX51_ECSPI_STAT		0x18
#define MX51_ECSPI_STAT_RR		(1 <<  3)
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/* MX51 eCSPI */
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static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
				      unsigned int *fres)
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{
	/*
	 * there are two 4-bit dividers, the pre-divider divides by
	 * $pre, the post-divider by 2^$post
	 */
	unsigned int pre, post;

	if (unlikely(fspi > fin))
		return 0;

	post = fls(fin) - fls(fspi);
	if (fin > fspi << post)
		post++;

	/* now we have: (fin <= fspi << post) with post being minimal */

	post = max(4U, post) - 4;
	if (unlikely(post > 0xf)) {
		pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
				__func__, fspi, fin);
		return 0xff;
	}

	pre = DIV_ROUND_UP(fin, fspi << post) - 1;

	pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
			__func__, fin, fspi, post, pre);
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	/* Resulting frequency for the SCLK line. */
	*fres = (fin / (pre + 1)) >> post;

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	return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
		(post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
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}

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static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
	unsigned val = 0;

	if (enable & MXC_INT_TE)
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		val |= MX51_ECSPI_INT_TEEN;
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	if (enable & MXC_INT_RR)
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		val |= MX51_ECSPI_INT_RREN;
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	writel(val, spi_imx->base + MX51_ECSPI_INT);
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}

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static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
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{
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	u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);

	if (!spi_imx->usedma)
		reg |= MX51_ECSPI_CTRL_XCH;
	else if (!spi_imx->dma_finished)
		reg |= MX51_ECSPI_CTRL_SMC;
	else
		reg &= ~MX51_ECSPI_CTRL_SMC;
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	writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
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}

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static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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		struct spi_imx_config *config)
{
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	u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
	u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
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	u32 clk = config->speed_hz, delay;
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	/*
	 * The hardware seems to have a race condition when changing modes. The
	 * current assumption is that the selection of the channel arrives
	 * earlier in the hardware than the mode bits when they are written at
	 * the same time.
	 * So set master mode for all channels as we do not support slave mode.
	 */
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	ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
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	/* set clock speed */
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	ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
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	/* set chip select to use */
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	ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
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	ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
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	cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
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	if (config->mode & SPI_CPHA)
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		cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
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	if (config->mode & SPI_CPOL) {
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		cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
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		cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
	}
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	if (config->mode & SPI_CS_HIGH)
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		cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
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	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
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	/*
	 * Wait until the changes in the configuration register CONFIGREG
	 * propagate into the hardware. It takes exactly one tick of the
	 * SCLK clock, but we will wait two SCLK clock just to be sure. The
	 * effect of the delay it takes for the hardware to apply changes
	 * is noticable if the SCLK clock run very slow. In such a case, if
	 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
	 * be asserted before the SCLK polarity changes, which would disrupt
	 * the SPI communication as the device on the other end would consider
	 * the change of SCLK polarity as a clock tick already.
	 */
	delay = (2 * 1000000) / clk;
	if (likely(delay < 10))	/* SCLK is faster than 100 kHz */
		udelay(delay);
	else			/* SCLK is _very_ slow */
		usleep_range(delay, delay + 10);

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	/*
	 * Configure the DMA register: setup the watermark
	 * and enable DMA request.
	 */
	if (spi_imx->dma_is_inited) {
		dma = readl(spi_imx->base + MX51_ECSPI_DMA);

		spi_imx->tx_wml = spi_imx_get_fifosize(spi_imx) / 2;
		spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
		spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2;
		rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
		tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
		rxt_wml_cfg = spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
		dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
			   & ~MX51_ECSPI_DMA_RX_WML_MASK
			   & ~MX51_ECSPI_DMA_RXT_WML_MASK)
			   | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
			   |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
			   |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
			   |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);

		writel(dma, spi_imx->base + MX51_ECSPI_DMA);
	}

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	return 0;
}

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static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
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{
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	return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
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}

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static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
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{
	/* drain receive buffer */
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	while (mx51_ecspi_rx_available(spi_imx))
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		readl(spi_imx->base + MXC_CSPIRXDATA);
}

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#define MX31_INTREG_TEEN	(1 << 0)
#define MX31_INTREG_RREN	(1 << 3)

#define MX31_CSPICTRL_ENABLE	(1 << 0)
#define MX31_CSPICTRL_MASTER	(1 << 1)
#define MX31_CSPICTRL_XCH	(1 << 2)
#define MX31_CSPICTRL_POL	(1 << 4)
#define MX31_CSPICTRL_PHA	(1 << 5)
#define MX31_CSPICTRL_SSCTL	(1 << 6)
#define MX31_CSPICTRL_SSPOL	(1 << 7)
#define MX31_CSPICTRL_BC_SHIFT	8
#define MX35_CSPICTRL_BL_SHIFT	20
#define MX31_CSPICTRL_CS_SHIFT	24
#define MX35_CSPICTRL_CS_SHIFT	12
#define MX31_CSPICTRL_DR_SHIFT	16

#define MX31_CSPISTATUS		0x14
#define MX31_STATUS_RR		(1 << 3)

/* These functions also work for the i.MX35, but be aware that
 * the i.MX35 has a slightly different register layout for bits
 * we do not use here.
 */
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static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
	unsigned int val = 0;

	if (enable & MXC_INT_TE)
		val |= MX31_INTREG_TEEN;
	if (enable & MXC_INT_RR)
		val |= MX31_INTREG_RREN;

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	writel(val, spi_imx->base + MXC_CSPIINT);
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}

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static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
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{
	unsigned int reg;

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	reg = readl(spi_imx->base + MXC_CSPICTRL);
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	reg |= MX31_CSPICTRL_XCH;
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	writel(reg, spi_imx->base + MXC_CSPICTRL);
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}

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static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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		struct spi_imx_config *config)
{
	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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	int cs = spi_imx->chipselect[config->cs];
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	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
		MX31_CSPICTRL_DR_SHIFT;

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	if (is_imx35_cspi(spi_imx)) {
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		reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
		reg |= MX31_CSPICTRL_SSCTL;
	} else {
		reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
	}
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	if (config->mode & SPI_CPHA)
		reg |= MX31_CSPICTRL_PHA;
	if (config->mode & SPI_CPOL)
		reg |= MX31_CSPICTRL_POL;
	if (config->mode & SPI_CS_HIGH)
		reg |= MX31_CSPICTRL_SSPOL;
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	if (cs < 0)
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		reg |= (cs + 32) <<
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			(is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
						  MX31_CSPICTRL_CS_SHIFT);
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	writel(reg, spi_imx->base + MXC_CSPICTRL);

	return 0;
}

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static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
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{
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	return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
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}

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static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
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{
	/* drain receive buffer */
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	while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
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		readl(spi_imx->base + MXC_CSPIRXDATA);
}

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#define MX21_INTREG_RR		(1 << 4)
#define MX21_INTREG_TEEN	(1 << 9)
#define MX21_INTREG_RREN	(1 << 13)

#define MX21_CSPICTRL_POL	(1 << 5)
#define MX21_CSPICTRL_PHA	(1 << 6)
#define MX21_CSPICTRL_SSPOL	(1 << 8)
#define MX21_CSPICTRL_XCH	(1 << 9)
#define MX21_CSPICTRL_ENABLE	(1 << 10)
#define MX21_CSPICTRL_MASTER	(1 << 11)
#define MX21_CSPICTRL_DR_SHIFT	14
#define MX21_CSPICTRL_CS_SHIFT	19

static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
	unsigned int val = 0;

	if (enable & MXC_INT_TE)
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		val |= MX21_INTREG_TEEN;
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	if (enable & MXC_INT_RR)
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		val |= MX21_INTREG_RREN;
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	writel(val, spi_imx->base + MXC_CSPIINT);
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}

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static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
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{
	unsigned int reg;

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	reg = readl(spi_imx->base + MXC_CSPICTRL);
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	reg |= MX21_CSPICTRL_XCH;
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	writel(reg, spi_imx->base + MXC_CSPICTRL);
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}

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static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
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		struct spi_imx_config *config)
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{
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	unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
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	int cs = spi_imx->chipselect[config->cs];
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	unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
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	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
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		MX21_CSPICTRL_DR_SHIFT;
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	reg |= config->bpw - 1;

	if (config->mode & SPI_CPHA)
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		reg |= MX21_CSPICTRL_PHA;
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	if (config->mode & SPI_CPOL)
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		reg |= MX21_CSPICTRL_POL;
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	if (config->mode & SPI_CS_HIGH)
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		reg |= MX21_CSPICTRL_SSPOL;
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	if (cs < 0)
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		reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
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	writel(reg, spi_imx->base + MXC_CSPICTRL);
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	return 0;
}

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static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
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{
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	return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
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}

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static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
558 559 560 561
{
	writel(1, spi_imx->base + MXC_RESET);
}

562 563 564 565 566 567 568 569 570 571 572
#define MX1_INTREG_RR		(1 << 3)
#define MX1_INTREG_TEEN		(1 << 8)
#define MX1_INTREG_RREN		(1 << 11)

#define MX1_CSPICTRL_POL	(1 << 4)
#define MX1_CSPICTRL_PHA	(1 << 5)
#define MX1_CSPICTRL_XCH	(1 << 8)
#define MX1_CSPICTRL_ENABLE	(1 << 9)
#define MX1_CSPICTRL_MASTER	(1 << 10)
#define MX1_CSPICTRL_DR_SHIFT	13

573
static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
574 575 576 577 578 579 580 581
{
	unsigned int val = 0;

	if (enable & MXC_INT_TE)
		val |= MX1_INTREG_TEEN;
	if (enable & MXC_INT_RR)
		val |= MX1_INTREG_RREN;

582
	writel(val, spi_imx->base + MXC_CSPIINT);
583 584
}

585
static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
586 587 588
{
	unsigned int reg;

589
	reg = readl(spi_imx->base + MXC_CSPICTRL);
590
	reg |= MX1_CSPICTRL_XCH;
591
	writel(reg, spi_imx->base + MXC_CSPICTRL);
592 593
}

594
static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
595
		struct spi_imx_config *config)
596 597 598
{
	unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;

599
	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
600 601 602 603 604 605 606 607
		MX1_CSPICTRL_DR_SHIFT;
	reg |= config->bpw - 1;

	if (config->mode & SPI_CPHA)
		reg |= MX1_CSPICTRL_PHA;
	if (config->mode & SPI_CPOL)
		reg |= MX1_CSPICTRL_POL;

608
	writel(reg, spi_imx->base + MXC_CSPICTRL);
609 610 611 612

	return 0;
}

613
static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
614
{
615
	return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
616 617
}

618 619 620 621 622
static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
{
	writel(1, spi_imx->base + MXC_RESET);
}

623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
	.intctrl = mx1_intctrl,
	.config = mx1_config,
	.trigger = mx1_trigger,
	.rx_available = mx1_rx_available,
	.reset = mx1_reset,
	.devtype = IMX1_CSPI,
};

static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
	.intctrl = mx21_intctrl,
	.config = mx21_config,
	.trigger = mx21_trigger,
	.rx_available = mx21_rx_available,
	.reset = mx21_reset,
	.devtype = IMX21_CSPI,
};

static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
	/* i.mx27 cspi shares the functions with i.mx21 one */
	.intctrl = mx21_intctrl,
	.config = mx21_config,
	.trigger = mx21_trigger,
	.rx_available = mx21_rx_available,
	.reset = mx21_reset,
	.devtype = IMX27_CSPI,
};

static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
	.intctrl = mx31_intctrl,
	.config = mx31_config,
	.trigger = mx31_trigger,
	.rx_available = mx31_rx_available,
	.reset = mx31_reset,
	.devtype = IMX31_CSPI,
};

static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
	/* i.mx35 and later cspi shares the functions with i.mx31 one */
	.intctrl = mx31_intctrl,
	.config = mx31_config,
	.trigger = mx31_trigger,
	.rx_available = mx31_rx_available,
	.reset = mx31_reset,
	.devtype = IMX35_CSPI,
};

static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
	.intctrl = mx51_ecspi_intctrl,
	.config = mx51_ecspi_config,
	.trigger = mx51_ecspi_trigger,
	.rx_available = mx51_ecspi_rx_available,
	.reset = mx51_ecspi_reset,
	.devtype = IMX51_ECSPI,
};

static struct platform_device_id spi_imx_devtype[] = {
	{
		.name = "imx1-cspi",
		.driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
	}, {
		.name = "imx21-cspi",
		.driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
	}, {
		.name = "imx27-cspi",
		.driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
	}, {
		.name = "imx31-cspi",
		.driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
	}, {
		.name = "imx35-cspi",
		.driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
	}, {
		.name = "imx51-ecspi",
		.driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
	}, {
		/* sentinel */
	}
701 702
};

703 704 705 706 707 708 709 710 711
static const struct of_device_id spi_imx_dt_ids[] = {
	{ .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
	{ .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
	{ .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
	{ .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
	{ .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
	{ .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
	{ /* sentinel */ }
};
712
MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
713

714
static void spi_imx_chipselect(struct spi_device *spi, int is_active)
715
{
716 717
	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
	int gpio = spi_imx->chipselect[spi->chip_select];
718 719
	int active = is_active != BITBANG_CS_INACTIVE;
	int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
720

721
	if (!gpio_is_valid(gpio))
722 723
		return;

724
	gpio_set_value(gpio, dev_is_lowactive ^ active);
725 726
}

727
static void spi_imx_push(struct spi_imx_data *spi_imx)
728
{
729
	while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
730
		if (!spi_imx->count)
731
			break;
732 733
		spi_imx->tx(spi_imx);
		spi_imx->txfifo++;
734 735
	}

736
	spi_imx->devtype_data->trigger(spi_imx);
737 738
}

739
static irqreturn_t spi_imx_isr(int irq, void *dev_id)
740
{
741
	struct spi_imx_data *spi_imx = dev_id;
742

743
	while (spi_imx->devtype_data->rx_available(spi_imx)) {
744 745
		spi_imx->rx(spi_imx);
		spi_imx->txfifo--;
746 747
	}

748 749
	if (spi_imx->count) {
		spi_imx_push(spi_imx);
750 751 752
		return IRQ_HANDLED;
	}

753
	if (spi_imx->txfifo) {
754 755 756
		/* No data left to push, but still waiting for rx data,
		 * enable receive data available interrupt.
		 */
757
		spi_imx->devtype_data->intctrl(
758
				spi_imx, MXC_INT_RR);
759 760 761
		return IRQ_HANDLED;
	}

762
	spi_imx->devtype_data->intctrl(spi_imx, 0);
763
	complete(&spi_imx->xfer_done);
764 765 766 767

	return IRQ_HANDLED;
}

768
static int spi_imx_setupxfer(struct spi_device *spi,
769 770
				 struct spi_transfer *t)
{
771 772
	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
	struct spi_imx_config config;
773 774 775 776

	config.bpw = t ? t->bits_per_word : spi->bits_per_word;
	config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
	config.mode = spi->mode;
777
	config.cs = spi->chip_select;
778

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	if (!config.speed_hz)
		config.speed_hz = spi->max_speed_hz;
	if (!config.bpw)
		config.bpw = spi->bits_per_word;

784 785 786 787 788 789 790
	/* Initialize the functions for transfer */
	if (config.bpw <= 8) {
		spi_imx->rx = spi_imx_buf_rx_u8;
		spi_imx->tx = spi_imx_buf_tx_u8;
	} else if (config.bpw <= 16) {
		spi_imx->rx = spi_imx_buf_rx_u16;
		spi_imx->tx = spi_imx_buf_tx_u16;
791
	} else {
792 793
		spi_imx->rx = spi_imx_buf_rx_u32;
		spi_imx->tx = spi_imx_buf_tx_u32;
794
	}
795

796
	spi_imx->devtype_data->config(spi_imx, &config);
797 798 799 800

	return 0;
}

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static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
{
	struct spi_master *master = spi_imx->bitbang.master;

	if (master->dma_rx) {
		dma_release_channel(master->dma_rx);
		master->dma_rx = NULL;
	}

	if (master->dma_tx) {
		dma_release_channel(master->dma_tx);
		master->dma_tx = NULL;
	}

	spi_imx->dma_is_inited = 0;
}

static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
			     struct spi_master *master,
			     const struct resource *res)
{
	struct dma_slave_config slave_config = {};
	int ret;

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	/* use pio mode for i.mx6dl chip TKT238285 */
	if (of_machine_is_compatible("fsl,imx6dl"))
		return 0;

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	/* Prepare for TX DMA: */
	master->dma_tx = dma_request_slave_channel(dev, "tx");
	if (!master->dma_tx) {
		dev_err(dev, "cannot get the TX DMA channel!\n");
		ret = -EINVAL;
		goto err;
	}

	slave_config.direction = DMA_MEM_TO_DEV;
	slave_config.dst_addr = res->start + MXC_CSPITXDATA;
	slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	slave_config.dst_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
	ret = dmaengine_slave_config(master->dma_tx, &slave_config);
	if (ret) {
		dev_err(dev, "error in TX dma configuration.\n");
		goto err;
	}

	/* Prepare for RX : */
	master->dma_rx = dma_request_slave_channel(dev, "rx");
	if (!master->dma_rx) {
		dev_dbg(dev, "cannot get the DMA channel.\n");
		ret = -EINVAL;
		goto err;
	}

	slave_config.direction = DMA_DEV_TO_MEM;
	slave_config.src_addr = res->start + MXC_CSPIRXDATA;
	slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	slave_config.src_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
	ret = dmaengine_slave_config(master->dma_rx, &slave_config);
	if (ret) {
		dev_err(dev, "error in RX dma configuration.\n");
		goto err;
	}

	init_completion(&spi_imx->dma_rx_completion);
	init_completion(&spi_imx->dma_tx_completion);
	master->can_dma = spi_imx_can_dma;
	master->max_dma_len = MAX_SDMA_BD_BYTES;
	spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
					 SPI_MASTER_MUST_TX;
	spi_imx->dma_is_inited = 1;

	return 0;
err:
	spi_imx_sdma_exit(spi_imx);
	return ret;
}

static void spi_imx_dma_rx_callback(void *cookie)
{
	struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;

	complete(&spi_imx->dma_rx_completion);
}

static void spi_imx_dma_tx_callback(void *cookie)
{
	struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;

	complete(&spi_imx->dma_tx_completion);
}

static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
				struct spi_transfer *transfer)
{
	struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
	int ret;
898
	unsigned long timeout;
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	u32 dma;
	int left;
	struct spi_master *master = spi_imx->bitbang.master;
	struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;

	if (tx) {
		desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
					tx->sgl, tx->nents, DMA_TO_DEVICE,
					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
		if (!desc_tx)
			goto no_dma;

		desc_tx->callback = spi_imx_dma_tx_callback;
		desc_tx->callback_param = (void *)spi_imx;
		dmaengine_submit(desc_tx);
	}

	if (rx) {
		desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
					rx->sgl, rx->nents, DMA_FROM_DEVICE,
					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
		if (!desc_rx)
			goto no_dma;

		desc_rx->callback = spi_imx_dma_rx_callback;
		desc_rx->callback_param = (void *)spi_imx;
		dmaengine_submit(desc_rx);
	}

	reinit_completion(&spi_imx->dma_rx_completion);
	reinit_completion(&spi_imx->dma_tx_completion);

	/* Trigger the cspi module. */
	spi_imx->dma_finished = 0;

	dma = readl(spi_imx->base + MX51_ECSPI_DMA);
	dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK);
	/* Change RX_DMA_LENGTH trigger dma fetch tail data */
	left = transfer->len % spi_imx->rxt_wml;
	if (left)
		writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET),
				spi_imx->base + MX51_ECSPI_DMA);
	spi_imx->devtype_data->trigger(spi_imx);

	dma_async_issue_pending(master->dma_tx);
	dma_async_issue_pending(master->dma_rx);
	/* Wait SDMA to finish the data transfer.*/
946
	timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
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						IMX_DMA_TIMEOUT);
948
	if (!timeout) {
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		pr_warn("%s %s: I/O Error in DMA TX\n",
			dev_driver_string(&master->dev),
			dev_name(&master->dev));
		dmaengine_terminate_all(master->dma_tx);
	} else {
954 955 956
		timeout = wait_for_completion_timeout(
				&spi_imx->dma_rx_completion, IMX_DMA_TIMEOUT);
		if (!timeout) {
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			pr_warn("%s %s: I/O Error in DMA RX\n",
				dev_driver_string(&master->dev),
				dev_name(&master->dev));
			spi_imx->devtype_data->reset(spi_imx);
			dmaengine_terminate_all(master->dma_rx);
		}
		writel(dma |
		       spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET,
		       spi_imx->base + MX51_ECSPI_DMA);
	}

	spi_imx->dma_finished = 1;
	spi_imx->devtype_data->trigger(spi_imx);

971
	if (!timeout)
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		ret = -ETIMEDOUT;
973
	else
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		ret = transfer->len;

	return ret;

no_dma:
	pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
		     dev_driver_string(&master->dev),
		     dev_name(&master->dev));
	return -EAGAIN;
}

static int spi_imx_pio_transfer(struct spi_device *spi,
986 987
				struct spi_transfer *transfer)
{
988
	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
989

990 991 992 993
	spi_imx->tx_buf = transfer->tx_buf;
	spi_imx->rx_buf = transfer->rx_buf;
	spi_imx->count = transfer->len;
	spi_imx->txfifo = 0;
994

995
	reinit_completion(&spi_imx->xfer_done);
996

997
	spi_imx_push(spi_imx);
998

999
	spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1000

1001
	wait_for_completion(&spi_imx->xfer_done);
1002 1003 1004 1005

	return transfer->len;
}

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static int spi_imx_transfer(struct spi_device *spi,
				struct spi_transfer *transfer)
{
	int ret;
	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);

	if (spi_imx->bitbang.master->can_dma &&
	    spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
		spi_imx->usedma = true;
		ret = spi_imx_dma_transfer(spi_imx, transfer);
		if (ret != -EAGAIN)
			return ret;
	}
	spi_imx->usedma = false;

	return spi_imx_pio_transfer(spi, transfer);
}

1024
static int spi_imx_setup(struct spi_device *spi)
1025
{
1026 1027 1028
	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
	int gpio = spi_imx->chipselect[spi->chip_select];

1029
	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1030 1031
		 spi->mode, spi->bits_per_word, spi->max_speed_hz);

1032
	if (gpio_is_valid(gpio))
1033 1034
		gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);

1035
	spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1036 1037 1038 1039

	return 0;
}

1040
static void spi_imx_cleanup(struct spi_device *spi)
1041 1042 1043
{
}

1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072
static int
spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
{
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
	int ret;

	ret = clk_enable(spi_imx->clk_per);
	if (ret)
		return ret;

	ret = clk_enable(spi_imx->clk_ipg);
	if (ret) {
		clk_disable(spi_imx->clk_per);
		return ret;
	}

	return 0;
}

static int
spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
{
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);

	clk_disable(spi_imx->clk_ipg);
	clk_disable(spi_imx->clk_per);
	return 0;
}

1073
static int spi_imx_probe(struct platform_device *pdev)
1074
{
1075 1076 1077 1078 1079
	struct device_node *np = pdev->dev.of_node;
	const struct of_device_id *of_id =
			of_match_device(spi_imx_dt_ids, &pdev->dev);
	struct spi_imx_master *mxc_platform_info =
			dev_get_platdata(&pdev->dev);
1080
	struct spi_master *master;
1081
	struct spi_imx_data *spi_imx;
1082
	struct resource *res;
1083
	int i, ret, num_cs, irq;
1084

1085
	if (!np && !mxc_platform_info) {
1086 1087 1088 1089
		dev_err(&pdev->dev, "can't get the platform data\n");
		return -EINVAL;
	}

1090
	ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
1091 1092 1093 1094 1095 1096
	if (ret < 0) {
		if (mxc_platform_info)
			num_cs = mxc_platform_info->num_chipselect;
		else
			return ret;
	}
1097

1098 1099
	master = spi_alloc_master(&pdev->dev,
			sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
1100 1101 1102 1103 1104
	if (!master)
		return -ENOMEM;

	platform_set_drvdata(pdev, master);

1105
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1106
	master->bus_num = pdev->id;
1107
	master->num_chipselect = num_cs;
1108

1109
	spi_imx = spi_master_get_devdata(master);
1110
	spi_imx->bitbang.master = master;
1111 1112

	for (i = 0; i < master->num_chipselect; i++) {
1113
		int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
1114
		if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
1115
			cs_gpio = mxc_platform_info->chipselect[i];
1116 1117

		spi_imx->chipselect[i] = cs_gpio;
1118
		if (!gpio_is_valid(cs_gpio))
1119
			continue;
1120

F
Fabio Estevam 已提交
1121 1122
		ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
					DRIVER_NAME);
1123
		if (ret) {
1124
			dev_err(&pdev->dev, "can't get cs gpios\n");
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1125
			goto out_master_put;
1126 1127 1128
		}
	}

1129 1130 1131 1132 1133
	spi_imx->bitbang.chipselect = spi_imx_chipselect;
	spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
	spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
	spi_imx->bitbang.master->setup = spi_imx_setup;
	spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1134 1135
	spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
	spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1136
	spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1137

1138
	init_completion(&spi_imx->xfer_done);
1139

1140
	spi_imx->devtype_data = of_id ? of_id->data :
1141
		(struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
1142

1143
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
F
Fabio Estevam 已提交
1144 1145 1146 1147
	spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(spi_imx->base)) {
		ret = PTR_ERR(spi_imx->base);
		goto out_master_put;
1148 1149
	}

1150 1151 1152
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = irq;
F
Fabio Estevam 已提交
1153
		goto out_master_put;
1154 1155
	}

1156
	ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1157
			       dev_name(&pdev->dev), spi_imx);
1158
	if (ret) {
1159
		dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
F
Fabio Estevam 已提交
1160
		goto out_master_put;
1161 1162
	}

1163 1164 1165
	spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(spi_imx->clk_ipg)) {
		ret = PTR_ERR(spi_imx->clk_ipg);
F
Fabio Estevam 已提交
1166
		goto out_master_put;
1167 1168
	}

1169 1170 1171
	spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(spi_imx->clk_per)) {
		ret = PTR_ERR(spi_imx->clk_per);
F
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1172
		goto out_master_put;
1173 1174
	}

1175 1176 1177 1178 1179 1180 1181
	ret = clk_prepare_enable(spi_imx->clk_per);
	if (ret)
		goto out_master_put;

	ret = clk_prepare_enable(spi_imx->clk_ipg);
	if (ret)
		goto out_put_per;
1182 1183

	spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
R
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1184 1185 1186 1187 1188 1189 1190
	/*
	 * Only validated on i.mx6 now, can remove the constrain if validated on
	 * other chips.
	 */
	if (spi_imx->devtype_data == &imx51_ecspi_devtype_data
	    && spi_imx_sdma_init(&pdev->dev, spi_imx, master, res))
		dev_err(&pdev->dev, "dma setup error,use pio instead\n");
1191

1192
	spi_imx->devtype_data->reset(spi_imx);
1193

1194
	spi_imx->devtype_data->intctrl(spi_imx, 0);
1195

1196
	master->dev.of_node = pdev->dev.of_node;
1197
	ret = spi_bitbang_start(&spi_imx->bitbang);
1198 1199 1200 1201 1202 1203 1204
	if (ret) {
		dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
		goto out_clk_put;
	}

	dev_info(&pdev->dev, "probed\n");

1205 1206
	clk_disable(spi_imx->clk_ipg);
	clk_disable(spi_imx->clk_per);
1207 1208 1209
	return ret;

out_clk_put:
1210
	clk_disable_unprepare(spi_imx->clk_ipg);
1211 1212
out_put_per:
	clk_disable_unprepare(spi_imx->clk_per);
F
Fabio Estevam 已提交
1213
out_master_put:
1214
	spi_master_put(master);
F
Fabio Estevam 已提交
1215

1216 1217 1218
	return ret;
}

1219
static int spi_imx_remove(struct platform_device *pdev)
1220 1221
{
	struct spi_master *master = platform_get_drvdata(pdev);
1222
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1223

1224
	spi_bitbang_stop(&spi_imx->bitbang);
1225

1226
	writel(0, spi_imx->base + MXC_CSPICTRL);
1227 1228
	clk_unprepare(spi_imx->clk_ipg);
	clk_unprepare(spi_imx->clk_per);
R
Robin Gong 已提交
1229
	spi_imx_sdma_exit(spi_imx);
1230 1231 1232 1233 1234
	spi_master_put(master);

	return 0;
}

1235
static struct platform_driver spi_imx_driver = {
1236 1237
	.driver = {
		   .name = DRIVER_NAME,
1238
		   .of_match_table = spi_imx_dt_ids,
1239
		   },
1240
	.id_table = spi_imx_devtype,
1241
	.probe = spi_imx_probe,
1242
	.remove = spi_imx_remove,
1243
};
1244
module_platform_driver(spi_imx_driver);
1245 1246 1247 1248

MODULE_DESCRIPTION("SPI Master Controller driver");
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
MODULE_LICENSE("GPL");
F
Fabio Estevam 已提交
1249
MODULE_ALIAS("platform:" DRIVER_NAME);