stmmac_main.c 87.1 KB
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/*******************************************************************************
  This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
  ST Ethernet IPs are built around a Synopsys IP Core.

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	Copyright(C) 2007-2011 STMicroelectronics Ltd
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  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>

  Documentation available at:
	http://www.stlinux.com
  Support available at:
	https://bugzilla.stlinux.com/
*******************************************************************************/

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#include <linux/clk.h>
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#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/if_ether.h>
#include <linux/crc32.h>
#include <linux/mii.h>
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#include <linux/if.h>
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#include <linux/if_vlan.h>
#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/prefetch.h>
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#include <linux/pinctrl/consumer.h>
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
#include <linux/seq_file.h>
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#endif /* CONFIG_DEBUG_FS */
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#include <linux/net_tstamp.h>
#include "stmmac_ptp.h"
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#include "stmmac.h"
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#include <linux/reset.h>
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#define STMMAC_ALIGN(x)	L1_CACHE_ALIGN(x)

/* Module parameters */
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#define TX_TIMEO	5000
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static int watchdog = TX_TIMEO;
module_param(watchdog, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
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static int debug = -1;
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module_param(debug, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
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static int phyaddr = -1;
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module_param(phyaddr, int, S_IRUGO);
MODULE_PARM_DESC(phyaddr, "Physical device address");

#define DMA_TX_SIZE 256
static int dma_txsize = DMA_TX_SIZE;
module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");

#define DMA_RX_SIZE 256
static int dma_rxsize = DMA_RX_SIZE;
module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");

static int flow_ctrl = FLOW_OFF;
module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");

static int pause = PAUSE_TIME;
module_param(pause, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(pause, "Flow Control Pause Time");

#define TC_DEFAULT 64
static int tc = TC_DEFAULT;
module_param(tc, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(tc, "DMA threshold control value");

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#define	DEFAULT_BUFSIZE	1536
static int buf_sz = DEFAULT_BUFSIZE;
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module_param(buf_sz, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(buf_sz, "DMA buffer size");

static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
				      NETIF_MSG_LINK | NETIF_MSG_IFUP |
				      NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);

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#define STMMAC_DEFAULT_LPI_TIMER	1000
static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
module_param(eee_timer, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
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#define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
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/* By default the driver will use the ring mode to manage tx and rx descriptors
 * but passing this value so user can force to use the chain instead of the ring
 */
static unsigned int chain_mode;
module_param(chain_mode, int, S_IRUGO);
MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");

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static irqreturn_t stmmac_interrupt(int irq, void *dev_id);

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#ifdef CONFIG_DEBUG_FS
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static int stmmac_init_fs(struct net_device *dev);
static void stmmac_exit_fs(void);
#endif

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#define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))

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/**
 * stmmac_verify_args - verify the driver parameters.
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 * Description: it checks the driver parameters and set a default in case of
 * errors.
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 */
static void stmmac_verify_args(void)
{
	if (unlikely(watchdog < 0))
		watchdog = TX_TIMEO;
	if (unlikely(dma_rxsize < 0))
		dma_rxsize = DMA_RX_SIZE;
	if (unlikely(dma_txsize < 0))
		dma_txsize = DMA_TX_SIZE;
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	if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
		buf_sz = DEFAULT_BUFSIZE;
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	if (unlikely(flow_ctrl > 1))
		flow_ctrl = FLOW_AUTO;
	else if (likely(flow_ctrl < 0))
		flow_ctrl = FLOW_OFF;
	if (unlikely((pause < 0) || (pause > 0xffff)))
		pause = PAUSE_TIME;
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	if (eee_timer < 0)
		eee_timer = STMMAC_DEFAULT_LPI_TIMER;
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}

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/**
 * stmmac_clk_csr_set - dynamically set the MDC clock
 * @priv: driver private structure
 * Description: this is to dynamically set the MDC clock according to the csr
 * clock input.
 * Note:
 *	If a specific clk_csr value is passed from the platform
 *	this means that the CSR Clock Range selection cannot be
 *	changed at run-time and it is fixed (as reported in the driver
 *	documentation). Viceversa the driver will try to set the MDC
 *	clock dynamically according to the actual clock input.
 */
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static void stmmac_clk_csr_set(struct stmmac_priv *priv)
{
	u32 clk_rate;

	clk_rate = clk_get_rate(priv->stmmac_clk);

	/* Platform provided default clk_csr would be assumed valid
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	 * for all other cases except for the below mentioned ones.
	 * For values higher than the IEEE 802.3 specified frequency
	 * we can not estimate the proper divider as it is not known
	 * the frequency of clk_csr_i. So we do not change the default
	 * divider.
	 */
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	if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
		if (clk_rate < CSR_F_35M)
			priv->clk_csr = STMMAC_CSR_20_35M;
		else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
			priv->clk_csr = STMMAC_CSR_35_60M;
		else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
			priv->clk_csr = STMMAC_CSR_60_100M;
		else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
			priv->clk_csr = STMMAC_CSR_100_150M;
		else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
			priv->clk_csr = STMMAC_CSR_150_250M;
		else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
			priv->clk_csr = STMMAC_CSR_250_300M;
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	}
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}

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static void print_pkt(unsigned char *buf, int len)
{
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	pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
	print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
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}

/* minimum number of free TX descriptors required to wake up TX process */
#define STMMAC_TX_THRESH(x)	(x->dma_tx_size/4)

static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
{
	return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
}

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/**
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 * stmmac_hw_fix_mac_speed - callback for speed selection
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 * @priv: driver private structure
 * Description: on some platforms (e.g. ST), some HW system configuraton
 * registers have to be set according to the link speed negotiated.
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 */
static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
{
	struct phy_device *phydev = priv->phydev;

	if (likely(priv->plat->fix_mac_speed))
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		priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
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}

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/**
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 * stmmac_enable_eee_mode - check and enter in LPI mode
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 * @priv: driver private structure
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 * Description: this function is to verify and enter in LPI mode in case of
 * EEE.
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 */
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static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
{
	/* Check and enter in LPI mode */
	if ((priv->dirty_tx == priv->cur_tx) &&
	    (priv->tx_path_in_lpi_mode == false))
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		priv->hw->mac->set_eee_mode(priv->hw);
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}

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/**
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 * stmmac_disable_eee_mode - disable and exit from LPI mode
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 * @priv: driver private structure
 * Description: this function is to exit and disable EEE in case of
 * LPI state is true. This is called by the xmit.
 */
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void stmmac_disable_eee_mode(struct stmmac_priv *priv)
{
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	priv->hw->mac->reset_eee_mode(priv->hw);
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	del_timer_sync(&priv->eee_ctrl_timer);
	priv->tx_path_in_lpi_mode = false;
}

/**
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 * stmmac_eee_ctrl_timer - EEE TX SW timer.
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 * @arg : data hook
 * Description:
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 *  if there is no data transfer and if we are not in LPI state,
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 *  then MAC Transmitter can be moved to LPI state.
 */
static void stmmac_eee_ctrl_timer(unsigned long arg)
{
	struct stmmac_priv *priv = (struct stmmac_priv *)arg;

	stmmac_enable_eee_mode(priv);
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	mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
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}

/**
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 * stmmac_eee_init - init EEE
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 * @priv: driver private structure
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 * Description:
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 *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 *  can also manage EEE, this function enable the LPI state and start related
 *  timer.
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 */
bool stmmac_eee_init(struct stmmac_priv *priv)
{
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	char *phy_bus_name = priv->plat->phy_bus_name;
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	unsigned long flags;
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	bool ret = false;

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	/* Using PCS we cannot dial with the phy registers at this stage
	 * so we do not support extra feature like EEE.
	 */
	if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
	    (priv->pcs == STMMAC_PCS_RTBI))
		goto out;

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	/* Never init EEE in case of a switch is attached */
	if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
		goto out;

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	/* MAC core supports the EEE feature. */
	if (priv->dma_cap.eee) {
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		int tx_lpi_timer = priv->tx_lpi_timer;

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		/* Check if the PHY supports EEE */
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		if (phy_init_eee(priv->phydev, 1)) {
			/* To manage at run-time if the EEE cannot be supported
			 * anymore (for example because the lp caps have been
			 * changed).
			 * In that case the driver disable own timers.
			 */
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			spin_lock_irqsave(&priv->lock, flags);
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			if (priv->eee_active) {
				pr_debug("stmmac: disable EEE\n");
				del_timer_sync(&priv->eee_ctrl_timer);
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				priv->hw->mac->set_eee_timer(priv->hw, 0,
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							     tx_lpi_timer);
			}
			priv->eee_active = 0;
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			spin_unlock_irqrestore(&priv->lock, flags);
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			goto out;
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		}
		/* Activate the EEE and start timers */
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		spin_lock_irqsave(&priv->lock, flags);
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		if (!priv->eee_active) {
			priv->eee_active = 1;
			init_timer(&priv->eee_ctrl_timer);
			priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
			priv->eee_ctrl_timer.data = (unsigned long)priv;
			priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
			add_timer(&priv->eee_ctrl_timer);

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			priv->hw->mac->set_eee_timer(priv->hw,
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						     STMMAC_DEFAULT_LIT_LS,
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						     tx_lpi_timer);
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		}
		/* Set HW EEE according to the speed */
		priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
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		ret = true;
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		spin_unlock_irqrestore(&priv->lock, flags);

		pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
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	}
out:
	return ret;
}

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/* stmmac_get_tx_hwtstamp - get HW TX timestamps
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 * @priv: driver private structure
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 * @entry : descriptor index to be used.
 * @skb : the socket buffer
 * Description :
 * This function will read timestamp from the descriptor & pass it to stack.
 * and also perform some sanity checks.
 */
static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
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				   unsigned int entry, struct sk_buff *skb)
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{
	struct skb_shared_hwtstamps shhwtstamp;
	u64 ns;
	void *desc = NULL;

	if (!priv->hwts_tx_en)
		return;

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	/* exit if skb doesn't support hw tstamp */
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	if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
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		return;

	if (priv->adv_ts)
		desc = (priv->dma_etx + entry);
	else
		desc = (priv->dma_tx + entry);

	/* check tx tstamp status */
	if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
		return;

	/* get the valid tstamp */
	ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);

	memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
	shhwtstamp.hwtstamp = ns_to_ktime(ns);
	/* pass tstamp to stack */
	skb_tstamp_tx(skb, &shhwtstamp);

	return;
}

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/* stmmac_get_rx_hwtstamp - get HW RX timestamps
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 * @priv: driver private structure
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 * @entry : descriptor index to be used.
 * @skb : the socket buffer
 * Description :
 * This function will read received packet's timestamp from the descriptor
 * and pass it to stack. It also perform some sanity checks.
 */
static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
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				   unsigned int entry, struct sk_buff *skb)
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{
	struct skb_shared_hwtstamps *shhwtstamp = NULL;
	u64 ns;
	void *desc = NULL;

	if (!priv->hwts_rx_en)
		return;

	if (priv->adv_ts)
		desc = (priv->dma_erx + entry);
	else
		desc = (priv->dma_rx + entry);

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	/* exit if rx tstamp is not valid */
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	if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
		return;

	/* get valid tstamp */
	ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
	shhwtstamp = skb_hwtstamps(skb);
	memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
	shhwtstamp->hwtstamp = ns_to_ktime(ns);
}

/**
 *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 *  @dev: device pointer.
 *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 *  a proprietary structure used to pass information to the driver.
 *  Description:
 *  This function configures the MAC to enable/disable both outgoing(TX)
 *  and incoming(RX) packets time stamping based on user input.
 *  Return Value:
 *  0 on success and an appropriate -ve integer on failure.
 */
static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	struct hwtstamp_config config;
	struct timespec now;
	u64 temp = 0;
	u32 ptp_v2 = 0;
	u32 tstamp_all = 0;
	u32 ptp_over_ipv4_udp = 0;
	u32 ptp_over_ipv6_udp = 0;
	u32 ptp_over_ethernet = 0;
	u32 snap_type_sel = 0;
	u32 ts_master_en = 0;
	u32 ts_event_en = 0;
	u32 value = 0;

	if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
		netdev_alert(priv->dev, "No support for HW time stamping\n");
		priv->hwts_tx_en = 0;
		priv->hwts_rx_en = 0;

		return -EOPNOTSUPP;
	}

	if (copy_from_user(&config, ifr->ifr_data,
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			   sizeof(struct hwtstamp_config)))
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		return -EFAULT;

	pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
		 __func__, config.flags, config.tx_type, config.rx_filter);

	/* reserved for future extensions */
	if (config.flags)
		return -EINVAL;

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	if (config.tx_type != HWTSTAMP_TX_OFF &&
	    config.tx_type != HWTSTAMP_TX_ON)
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		return -ERANGE;

	if (priv->adv_ts) {
		switch (config.rx_filter) {
		case HWTSTAMP_FILTER_NONE:
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			/* time stamp no incoming packet at all */
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			config.rx_filter = HWTSTAMP_FILTER_NONE;
			break;

		case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
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			/* PTP v1, UDP, any kind of event packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
			/* take time stamp for all event messages */
			snap_type_sel = PTP_TCR_SNAPTYPSEL_1;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
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			/* PTP v1, UDP, Sync packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
			/* take time stamp for SYNC messages only */
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
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			/* PTP v1, UDP, Delay_req packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
			/* take time stamp for Delay_Req messages only */
			ts_master_en = PTP_TCR_TSMSTRENA;
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
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			/* PTP v2, UDP, any kind of event packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for all event messages */
			snap_type_sel = PTP_TCR_SNAPTYPSEL_1;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
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			/* PTP v2, UDP, Sync packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for SYNC messages only */
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
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			/* PTP v2, UDP, Delay_req packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for Delay_Req messages only */
			ts_master_en = PTP_TCR_TSMSTRENA;
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_EVENT:
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			/* PTP v2/802.AS1 any layer, any kind of event packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for all event messages */
			snap_type_sel = PTP_TCR_SNAPTYPSEL_1;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			ptp_over_ethernet = PTP_TCR_TSIPENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_SYNC:
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			/* PTP v2/802.AS1, any layer, Sync packet */
547 548 549 550 551 552 553 554 555 556 557
			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for SYNC messages only */
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			ptp_over_ethernet = PTP_TCR_TSIPENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
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			/* PTP v2/802.AS1, any layer, Delay_req packet */
559 560 561 562 563 564 565 566 567 568 569 570
			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for Delay_Req messages only */
			ts_master_en = PTP_TCR_TSMSTRENA;
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			ptp_over_ethernet = PTP_TCR_TSIPENA;
			break;

		case HWTSTAMP_FILTER_ALL:
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			/* time stamp any incoming packet */
572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590
			config.rx_filter = HWTSTAMP_FILTER_ALL;
			tstamp_all = PTP_TCR_TSENALL;
			break;

		default:
			return -ERANGE;
		}
	} else {
		switch (config.rx_filter) {
		case HWTSTAMP_FILTER_NONE:
			config.rx_filter = HWTSTAMP_FILTER_NONE;
			break;
		default:
			/* PTP v1, UDP, any kind of event packet */
			config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
			break;
		}
	}
	priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
591
	priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
592 593 594 595 596

	if (!priv->hwts_tx_en && !priv->hwts_rx_en)
		priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
	else {
		value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
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597 598 599
			 tstamp_all | ptp_v2 | ptp_over_ethernet |
			 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
			 ts_master_en | snap_type_sel);
600 601 602 603 604 605 606 607 608

		priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);

		/* program Sub Second Increment reg */
		priv->hw->ptp->config_sub_second_increment(priv->ioaddr);

		/* calculate default added value:
		 * formula is :
		 * addend = (2^32)/freq_div_ratio;
609 610 611
		 * where, freq_div_ratio = clk_ptp_ref_i/50MHz
		 * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
		 * NOTE: clk_ptp_ref_i should be >= 50MHz to
612 613 614 615 616
		 *       achive 20ns accuracy.
		 *
		 * 2^x * y == (y << x), hence
		 * 2^32 * 50000000 ==> (50000000 << 32)
		 */
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		temp = (u64) (50000000ULL << 32);
618
		priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
619 620 621 622 623 624 625 626 627 628 629 630 631
		priv->hw->ptp->config_addend(priv->ioaddr,
					     priv->default_addend);

		/* initialize system time */
		getnstimeofday(&now);
		priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
					    now.tv_nsec);
	}

	return copy_to_user(ifr->ifr_data, &config,
			    sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
}

632
/**
633
 * stmmac_init_ptp - init PTP
634
 * @priv: driver private structure
635
 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
636
 * This is done by looking at the HW cap. register.
637
 * This function also registers the ptp driver.
638
 */
639
static int stmmac_init_ptp(struct stmmac_priv *priv)
640
{
641 642 643
	if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
		return -EOPNOTSUPP;

644 645 646 647 648 649 650 651 652 653
	/* Fall-back to main clock in case of no PTP ref is passed */
	priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
	if (IS_ERR(priv->clk_ptp_ref)) {
		priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
		priv->clk_ptp_ref = NULL;
	} else {
		clk_prepare_enable(priv->clk_ptp_ref);
		priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
	}

654 655 656 657 658 659 660 661 662
	priv->adv_ts = 0;
	if (priv->dma_cap.atime_stamp && priv->extend_desc)
		priv->adv_ts = 1;

	if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
		pr_debug("IEEE 1588-2002 Time Stamp supported\n");

	if (netif_msg_hw(priv) && priv->adv_ts)
		pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
663 664 665 666

	priv->hw->ptp = &stmmac_ptp;
	priv->hwts_tx_en = 0;
	priv->hwts_rx_en = 0;
667 668 669 670 671 672

	return stmmac_ptp_register(priv);
}

static void stmmac_release_ptp(struct stmmac_priv *priv)
{
673 674
	if (priv->clk_ptp_ref)
		clk_disable_unprepare(priv->clk_ptp_ref);
675
	stmmac_ptp_unregister(priv);
676 677
}

678
/**
679
 * stmmac_adjust_link - adjusts the link parameters
680
 * @dev: net device structure
681 682 683 684 685
 * Description: this is the helper called by the physical abstraction layer
 * drivers to communicate the phy link status. According the speed and duplex
 * this driver can invoke registered glue-logic as well.
 * It also invoke the eee initialization because it could happen when switch
 * on different networks (that are eee capable).
686 687 688 689 690 691 692 693 694 695 696 697 698
 */
static void stmmac_adjust_link(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phydev;
	unsigned long flags;
	int new_state = 0;
	unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;

	if (phydev == NULL)
		return;

	spin_lock_irqsave(&priv->lock, flags);
699

700
	if (phydev->link) {
701
		u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
702 703 704 705 706 707

		/* Now we make sure that we can be in full duplex mode.
		 * If not, we operate in half-duplex mode. */
		if (phydev->duplex != priv->oldduplex) {
			new_state = 1;
			if (!(phydev->duplex))
708
				ctrl &= ~priv->hw->link.duplex;
709
			else
710
				ctrl |= priv->hw->link.duplex;
711 712 713 714
			priv->oldduplex = phydev->duplex;
		}
		/* Flow Control operation */
		if (phydev->pause)
715
			priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
716
						 fc, pause_time);
717 718 719 720 721

		if (phydev->speed != priv->speed) {
			new_state = 1;
			switch (phydev->speed) {
			case 1000:
722
				if (likely(priv->plat->has_gmac))
723
					ctrl &= ~priv->hw->link.port;
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Giuseppe CAVALLARO 已提交
724
				stmmac_hw_fix_mac_speed(priv);
725 726 727
				break;
			case 100:
			case 10:
728
				if (priv->plat->has_gmac) {
729
					ctrl |= priv->hw->link.port;
730
					if (phydev->speed == SPEED_100) {
731
						ctrl |= priv->hw->link.speed;
732
					} else {
733
						ctrl &= ~(priv->hw->link.speed);
734 735
					}
				} else {
736
					ctrl &= ~priv->hw->link.port;
737
				}
738
				stmmac_hw_fix_mac_speed(priv);
739 740 741
				break;
			default:
				if (netif_msg_link(priv))
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Giuseppe CAVALLARO 已提交
742 743
					pr_warn("%s: Speed (%d) not 10/100\n",
						dev->name, phydev->speed);
744 745 746 747 748 749
				break;
			}

			priv->speed = phydev->speed;
		}

750
		writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
751 752 753 754 755 756 757 758 759 760 761 762 763 764 765

		if (!priv->oldlink) {
			new_state = 1;
			priv->oldlink = 1;
		}
	} else if (priv->oldlink) {
		new_state = 1;
		priv->oldlink = 0;
		priv->speed = 0;
		priv->oldduplex = -1;
	}

	if (new_state && netif_msg_link(priv))
		phy_print_status(phydev);

766 767
	spin_unlock_irqrestore(&priv->lock, flags);

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Giuseppe CAVALLARO 已提交
768 769 770 771
	/* At this stage, it could be needed to setup the EEE or adjust some
	 * MAC related HW registers.
	 */
	priv->eee_enabled = stmmac_eee_init(priv);
772 773
}

774
/**
775
 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
776 777 778 779 780
 * @priv: driver private structure
 * Description: this is to verify if the HW supports the PCS.
 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 * configured for the TBI, RTBI, or SGMII PHY interface.
 */
781 782 783 784 785
static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
{
	int interface = priv->plat->interface;

	if (priv->dma_cap.pcs) {
B
Byungho An 已提交
786 787 788 789
		if ((interface == PHY_INTERFACE_MODE_RGMII) ||
		    (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
		    (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
		    (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
790 791
			pr_debug("STMMAC: PCS RGMII support enable\n");
			priv->pcs = STMMAC_PCS_RGMII;
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792
		} else if (interface == PHY_INTERFACE_MODE_SGMII) {
793 794 795 796 797 798
			pr_debug("STMMAC: PCS SGMII support enable\n");
			priv->pcs = STMMAC_PCS_SGMII;
		}
	}
}

799 800 801 802 803 804 805 806 807 808 809 810
/**
 * stmmac_init_phy - PHY initialization
 * @dev: net device structure
 * Description: it initializes the driver's PHY state, and attaches the PHY
 * to the mac driver.
 *  Return value:
 *  0 on success
 */
static int stmmac_init_phy(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	struct phy_device *phydev;
811
	char phy_id_fmt[MII_BUS_ID_SIZE + 3];
812
	char bus_id[MII_BUS_ID_SIZE];
813
	int interface = priv->plat->interface;
814
	int max_speed = priv->plat->max_speed;
815 816 817 818
	priv->oldlink = 0;
	priv->speed = 0;
	priv->oldduplex = -1;

819 820
	if (priv->plat->phy_bus_name)
		snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
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Giuseppe CAVALLARO 已提交
821
			 priv->plat->phy_bus_name, priv->plat->bus_id);
822 823
	else
		snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
G
Giuseppe CAVALLARO 已提交
824
			 priv->plat->bus_id);
825

826
	snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
827
		 priv->plat->phy_addr);
828
	pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
829

830
	phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
831 832 833 834 835 836

	if (IS_ERR(phydev)) {
		pr_err("%s: Could not attach to PHY\n", dev->name);
		return PTR_ERR(phydev);
	}

837
	/* Stop Advertising 1000BASE Capability if interface is not GMII */
838
	if ((interface == PHY_INTERFACE_MODE_MII) ||
839
	    (interface == PHY_INTERFACE_MODE_RMII) ||
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Pavel Machek 已提交
840
		(max_speed < 1000 && max_speed > 0))
841 842
		phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
					 SUPPORTED_1000baseT_Full);
843

844 845 846 847 848 849 850 851 852 853 854 855
	/*
	 * Broken HW is sometimes missing the pull-up resistor on the
	 * MDIO line, which results in reads to non-existent devices returning
	 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
	 * device as well.
	 * Note: phydev->phy_id is the result of reading the UID PHY registers.
	 */
	if (phydev->phy_id == 0) {
		phy_disconnect(phydev);
		return -ENODEV;
	}
	pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
856
		 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
857 858 859 860 861 862 863

	priv->phydev = phydev;

	return 0;
}

/**
864
 * stmmac_display_ring - display ring
865
 * @head: pointer to the head of the ring passed.
866
 * @size: size of the ring.
867
 * @extend_desc: to verify if extended descriptors are used.
868
 * Description: display the control/status and buffer descriptors.
869
 */
870
static void stmmac_display_ring(void *head, int size, int extend_desc)
871 872
{
	int i;
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Giuseppe CAVALLARO 已提交
873 874
	struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
	struct dma_desc *p = (struct dma_desc *)head;
875

876
	for (i = 0; i < size; i++) {
877 878 879 880
		u64 x;
		if (extend_desc) {
			x = *(u64 *) ep;
			pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
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Giuseppe CAVALLARO 已提交
881 882
				i, (unsigned int)virt_to_phys(ep),
				(unsigned int)x, (unsigned int)(x >> 32),
883 884 885 886 887
				ep->basic.des2, ep->basic.des3);
			ep++;
		} else {
			x = *(u64 *) p;
			pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
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Giuseppe CAVALLARO 已提交
888 889
				i, (unsigned int)virt_to_phys(p),
				(unsigned int)x, (unsigned int)(x >> 32),
890 891 892
				p->des2, p->des3);
			p++;
		}
893 894 895 896
		pr_info("\n");
	}
}

897 898 899 900 901 902 903
static void stmmac_display_rings(struct stmmac_priv *priv)
{
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;

	if (priv->extend_desc) {
		pr_info("Extended RX descriptor ring:\n");
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Giuseppe CAVALLARO 已提交
904
		stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
905
		pr_info("Extended TX descriptor ring:\n");
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Giuseppe CAVALLARO 已提交
906
		stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
907 908 909 910 911 912 913 914
	} else {
		pr_info("RX descriptor ring:\n");
		stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
		pr_info("TX descriptor ring:\n");
		stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
	}
}

915 916 917 918 919 920 921 922
static int stmmac_set_bfsize(int mtu, int bufsize)
{
	int ret = bufsize;

	if (mtu >= BUF_SIZE_4KiB)
		ret = BUF_SIZE_8KiB;
	else if (mtu >= BUF_SIZE_2KiB)
		ret = BUF_SIZE_4KiB;
923
	else if (mtu > DEFAULT_BUFSIZE)
924 925
		ret = BUF_SIZE_2KiB;
	else
926
		ret = DEFAULT_BUFSIZE;
927 928 929 930

	return ret;
}

931
/**
932
 * stmmac_clear_descriptors - clear descriptors
933 934 935 936
 * @priv: driver private structure
 * Description: this function is called to clear the tx and rx descriptors
 * in case of both basic and extended descriptors are used.
 */
937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963
static void stmmac_clear_descriptors(struct stmmac_priv *priv)
{
	int i;
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;

	/* Clear the Rx/Tx descriptors */
	for (i = 0; i < rxsize; i++)
		if (priv->extend_desc)
			priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
						     priv->use_riwt, priv->mode,
						     (i == rxsize - 1));
		else
			priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
						     priv->use_riwt, priv->mode,
						     (i == rxsize - 1));
	for (i = 0; i < txsize; i++)
		if (priv->extend_desc)
			priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
						     priv->mode,
						     (i == txsize - 1));
		else
			priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
						     priv->mode,
						     (i == txsize - 1));
}

964 965 966 967 968 969 970 971 972
/**
 * stmmac_init_rx_buffers - init the RX descriptor buffer.
 * @priv: driver private structure
 * @p: descriptor pointer
 * @i: descriptor index
 * @flags: gfp flag.
 * Description: this function is called to allocate a receive buffer, perform
 * the DMA mapping and init the descriptor.
 */
973
static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
974
				  int i, gfp_t flags)
975 976 977 978
{
	struct sk_buff *skb;

	skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
979
				 flags);
980
	if (!skb) {
981
		pr_err("%s: Rx init fails; skb is NULL\n", __func__);
982
		return -ENOMEM;
983 984 985 986 987 988
	}
	skb_reserve(skb, NET_IP_ALIGN);
	priv->rx_skbuff[i] = skb;
	priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
						priv->dma_buf_sz,
						DMA_FROM_DEVICE);
989 990 991 992 993
	if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
		pr_err("%s: DMA mapping error\n", __func__);
		dev_kfree_skb_any(skb);
		return -EINVAL;
	}
994 995 996

	p->des2 = priv->rx_skbuff_dma[i];

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Giuseppe CAVALLARO 已提交
997
	if ((priv->hw->mode->init_desc3) &&
998
	    (priv->dma_buf_sz == BUF_SIZE_16KiB))
G
Giuseppe CAVALLARO 已提交
999
		priv->hw->mode->init_desc3(p);
1000 1001 1002 1003

	return 0;
}

1004 1005 1006 1007 1008 1009 1010 1011 1012 1013
static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
{
	if (priv->rx_skbuff[i]) {
		dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
				 priv->dma_buf_sz, DMA_FROM_DEVICE);
		dev_kfree_skb_any(priv->rx_skbuff[i]);
	}
	priv->rx_skbuff[i] = NULL;
}

1014 1015 1016
/**
 * init_dma_desc_rings - init the RX/TX descriptor rings
 * @dev: net device structure
1017 1018
 * @flags: gfp flag.
 * Description: this function initializes the DMA RX/TX descriptors
1019 1020
 * and allocates the socket buffers. It suppors the chained and ring
 * modes.
1021
 */
1022
static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1023 1024 1025 1026 1027
{
	int i;
	struct stmmac_priv *priv = netdev_priv(dev);
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;
1028
	unsigned int bfsize = 0;
1029
	int ret = -ENOMEM;
1030

G
Giuseppe CAVALLARO 已提交
1031 1032
	if (priv->hw->mode->set_16kib_bfsize)
		bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1033

1034
	if (bfsize < BUF_SIZE_16KiB)
1035
		bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1036

1037 1038
	priv->dma_buf_sz = bfsize;

1039 1040 1041
	if (netif_msg_probe(priv))
		pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
			 txsize, rxsize, bfsize);
1042

1043
	if (netif_msg_probe(priv)) {
1044 1045
		pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
			 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1046

1047 1048 1049
		/* RX INITIALIZATION */
		pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
	}
1050
	for (i = 0; i < rxsize; i++) {
1051 1052 1053 1054 1055
		struct dma_desc *p;
		if (priv->extend_desc)
			p = &((priv->dma_erx + i)->basic);
		else
			p = priv->dma_rx + i;
1056

1057
		ret = stmmac_init_rx_buffers(priv, p, i, flags);
1058 1059
		if (ret)
			goto err_init_rx_buffers;
1060

1061 1062 1063 1064
		if (netif_msg_probe(priv))
			pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
				 priv->rx_skbuff[i]->data,
				 (unsigned int)priv->rx_skbuff_dma[i]);
1065 1066 1067 1068 1069
	}
	priv->cur_rx = 0;
	priv->dirty_rx = (unsigned int)(i - rxsize);
	buf_sz = bfsize;

1070 1071 1072
	/* Setup the chained descriptor addresses */
	if (priv->mode == STMMAC_CHAIN_MODE) {
		if (priv->extend_desc) {
G
Giuseppe CAVALLARO 已提交
1073 1074 1075 1076
			priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
					     rxsize, 1);
			priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
					     txsize, 1);
1077
		} else {
G
Giuseppe CAVALLARO 已提交
1078 1079 1080 1081
			priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
					     rxsize, 0);
			priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
					     txsize, 0);
1082 1083 1084
		}
	}

1085 1086
	/* TX INITIALIZATION */
	for (i = 0; i < txsize; i++) {
1087 1088 1089 1090 1091 1092
		struct dma_desc *p;
		if (priv->extend_desc)
			p = &((priv->dma_etx + i)->basic);
		else
			p = priv->dma_tx + i;
		p->des2 = 0;
G
Giuseppe CAVALLARO 已提交
1093 1094
		priv->tx_skbuff_dma[i].buf = 0;
		priv->tx_skbuff_dma[i].map_as_page = false;
1095 1096
		priv->tx_skbuff[i] = NULL;
	}
1097

1098 1099
	priv->dirty_tx = 0;
	priv->cur_tx = 0;
B
Beniamino Galvani 已提交
1100
	netdev_reset_queue(priv->dev);
1101

1102
	stmmac_clear_descriptors(priv);
1103

1104 1105
	if (netif_msg_hw(priv))
		stmmac_display_rings(priv);
1106 1107 1108 1109 1110 1111

	return 0;
err_init_rx_buffers:
	while (--i >= 0)
		stmmac_free_rx_buffers(priv, i);
	return ret;
1112 1113 1114 1115 1116 1117
}

static void dma_free_rx_skbufs(struct stmmac_priv *priv)
{
	int i;

1118 1119
	for (i = 0; i < priv->dma_rx_size; i++)
		stmmac_free_rx_buffers(priv, i);
1120 1121 1122 1123 1124 1125 1126
}

static void dma_free_tx_skbufs(struct stmmac_priv *priv)
{
	int i;

	for (i = 0; i < priv->dma_tx_size; i++) {
1127 1128 1129 1130 1131 1132 1133
		struct dma_desc *p;

		if (priv->extend_desc)
			p = &((priv->dma_etx + i)->basic);
		else
			p = priv->dma_tx + i;

G
Giuseppe CAVALLARO 已提交
1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144
		if (priv->tx_skbuff_dma[i].buf) {
			if (priv->tx_skbuff_dma[i].map_as_page)
				dma_unmap_page(priv->device,
					       priv->tx_skbuff_dma[i].buf,
					       priv->hw->desc->get_tx_len(p),
					       DMA_TO_DEVICE);
			else
				dma_unmap_single(priv->device,
						 priv->tx_skbuff_dma[i].buf,
						 priv->hw->desc->get_tx_len(p),
						 DMA_TO_DEVICE);
1145
		}
1146

1147
		if (priv->tx_skbuff[i] != NULL) {
1148 1149
			dev_kfree_skb_any(priv->tx_skbuff[i]);
			priv->tx_skbuff[i] = NULL;
G
Giuseppe CAVALLARO 已提交
1150 1151
			priv->tx_skbuff_dma[i].buf = 0;
			priv->tx_skbuff_dma[i].map_as_page = false;
1152 1153 1154 1155
		}
	}
}

1156 1157 1158 1159 1160 1161 1162 1163
/**
 * alloc_dma_desc_resources - alloc TX/RX resources.
 * @priv: private structure
 * Description: according to which descriptor can be used (extend or basic)
 * this function allocates the resources for TX and RX paths. In case of
 * reception, for example, it pre-allocated the RX socket buffer in order to
 * allow zero-copy mechanism.
 */
1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179
static int alloc_dma_desc_resources(struct stmmac_priv *priv)
{
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;
	int ret = -ENOMEM;

	priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
					    GFP_KERNEL);
	if (!priv->rx_skbuff_dma)
		return -ENOMEM;

	priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
					GFP_KERNEL);
	if (!priv->rx_skbuff)
		goto err_rx_skbuff;

G
Giuseppe CAVALLARO 已提交
1180 1181
	priv->tx_skbuff_dma = kmalloc_array(txsize,
					    sizeof(*priv->tx_skbuff_dma),
1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
					    GFP_KERNEL);
	if (!priv->tx_skbuff_dma)
		goto err_tx_skbuff_dma;

	priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
					GFP_KERNEL);
	if (!priv->tx_skbuff)
		goto err_tx_skbuff;

	if (priv->extend_desc) {
		priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
						   sizeof(struct
							  dma_extended_desc),
						   &priv->dma_rx_phy,
						   GFP_KERNEL);
		if (!priv->dma_erx)
			goto err_dma;

		priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
						   sizeof(struct
							  dma_extended_desc),
						   &priv->dma_tx_phy,
						   GFP_KERNEL);
		if (!priv->dma_etx) {
			dma_free_coherent(priv->device, priv->dma_rx_size *
					sizeof(struct dma_extended_desc),
					priv->dma_erx, priv->dma_rx_phy);
			goto err_dma;
		}
	} else {
		priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
						  sizeof(struct dma_desc),
						  &priv->dma_rx_phy,
						  GFP_KERNEL);
		if (!priv->dma_rx)
			goto err_dma;

		priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
						  sizeof(struct dma_desc),
						  &priv->dma_tx_phy,
						  GFP_KERNEL);
		if (!priv->dma_tx) {
			dma_free_coherent(priv->device, priv->dma_rx_size *
					sizeof(struct dma_desc),
					priv->dma_rx, priv->dma_rx_phy);
			goto err_dma;
		}
	}

	return 0;

err_dma:
	kfree(priv->tx_skbuff);
err_tx_skbuff:
	kfree(priv->tx_skbuff_dma);
err_tx_skbuff_dma:
	kfree(priv->rx_skbuff);
err_rx_skbuff:
	kfree(priv->rx_skbuff_dma);
	return ret;
}

1244 1245 1246 1247 1248 1249
static void free_dma_desc_resources(struct stmmac_priv *priv)
{
	/* Release the DMA TX/RX socket buffers */
	dma_free_rx_skbufs(priv);
	dma_free_tx_skbufs(priv);

G
Giuseppe CAVALLARO 已提交
1250
	/* Free DMA regions of consistent memory previously allocated */
1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265
	if (!priv->extend_desc) {
		dma_free_coherent(priv->device,
				  priv->dma_tx_size * sizeof(struct dma_desc),
				  priv->dma_tx, priv->dma_tx_phy);
		dma_free_coherent(priv->device,
				  priv->dma_rx_size * sizeof(struct dma_desc),
				  priv->dma_rx, priv->dma_rx_phy);
	} else {
		dma_free_coherent(priv->device, priv->dma_tx_size *
				  sizeof(struct dma_extended_desc),
				  priv->dma_etx, priv->dma_tx_phy);
		dma_free_coherent(priv->device, priv->dma_rx_size *
				  sizeof(struct dma_extended_desc),
				  priv->dma_erx, priv->dma_rx_phy);
	}
1266 1267
	kfree(priv->rx_skbuff_dma);
	kfree(priv->rx_skbuff);
1268
	kfree(priv->tx_skbuff_dma);
1269 1270 1271 1272 1273
	kfree(priv->tx_skbuff);
}

/**
 *  stmmac_dma_operation_mode - HW DMA operation mode
1274
 *  @priv: driver private structure
1275 1276
 *  Description: it is used for configuring the DMA operation mode register in
 *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1277 1278 1279
 */
static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
{
1280 1281 1282
	if (priv->plat->force_thresh_dma_mode)
		priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
	else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1283 1284 1285
		/*
		 * In case of GMAC, SF mode can be enabled
		 * to perform the TX COE in HW. This depends on:
1286 1287 1288 1289
		 * 1) TX COE if actually supported
		 * 2) There is no bugged Jumbo frame support
		 *    that needs to not insert csum in the TDES.
		 */
G
Giuseppe CAVALLARO 已提交
1290
		priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1291 1292 1293
		tc = SF_DMA_MODE;
	} else
		priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1294 1295 1296
}

/**
1297
 * stmmac_tx_clean - to manage the transmission completion
1298
 * @priv: driver private structure
1299
 * Description: it reclaims the transmit resources after transmission completes.
1300
 */
1301
static void stmmac_tx_clean(struct stmmac_priv *priv)
1302 1303
{
	unsigned int txsize = priv->dma_tx_size;
B
Beniamino Galvani 已提交
1304
	unsigned int bytes_compl = 0, pkts_compl = 0;
1305

1306 1307
	spin_lock(&priv->tx_lock);

1308 1309
	priv->xstats.tx_clean++;

1310 1311 1312 1313
	while (priv->dirty_tx != priv->cur_tx) {
		int last;
		unsigned int entry = priv->dirty_tx % txsize;
		struct sk_buff *skb = priv->tx_skbuff[entry];
1314 1315 1316
		struct dma_desc *p;

		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
1317
			p = (struct dma_desc *)(priv->dma_etx + entry);
1318 1319
		else
			p = priv->dma_tx + entry;
1320 1321

		/* Check if the descriptor is owned by the DMA. */
1322
		if (priv->hw->desc->get_tx_owner(p))
1323 1324
			break;

1325
		/* Verify tx error by looking at the last segment. */
1326
		last = priv->hw->desc->get_tx_ls(p);
1327 1328
		if (likely(last)) {
			int tx_error =
G
Giuseppe CAVALLARO 已提交
1329 1330 1331
			    priv->hw->desc->tx_status(&priv->dev->stats,
						      &priv->xstats, p,
						      priv->ioaddr);
1332 1333 1334 1335 1336
			if (likely(tx_error == 0)) {
				priv->dev->stats.tx_packets++;
				priv->xstats.tx_pkt_n++;
			} else
				priv->dev->stats.tx_errors++;
1337 1338

			stmmac_get_tx_hwtstamp(priv, entry, skb);
1339
		}
1340 1341 1342
		if (netif_msg_tx_done(priv))
			pr_debug("%s: curr %d, dirty %d\n", __func__,
				 priv->cur_tx, priv->dirty_tx);
1343

G
Giuseppe CAVALLARO 已提交
1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356
		if (likely(priv->tx_skbuff_dma[entry].buf)) {
			if (priv->tx_skbuff_dma[entry].map_as_page)
				dma_unmap_page(priv->device,
					       priv->tx_skbuff_dma[entry].buf,
					       priv->hw->desc->get_tx_len(p),
					       DMA_TO_DEVICE);
			else
				dma_unmap_single(priv->device,
						 priv->tx_skbuff_dma[entry].buf,
						 priv->hw->desc->get_tx_len(p),
						 DMA_TO_DEVICE);
			priv->tx_skbuff_dma[entry].buf = 0;
			priv->tx_skbuff_dma[entry].map_as_page = false;
1357
		}
G
Giuseppe CAVALLARO 已提交
1358
		priv->hw->mode->clean_desc3(priv, p);
1359 1360

		if (likely(skb != NULL)) {
B
Beniamino Galvani 已提交
1361 1362
			pkts_compl++;
			bytes_compl += skb->len;
1363
			dev_consume_skb_any(skb);
1364 1365 1366
			priv->tx_skbuff[entry] = NULL;
		}

1367
		priv->hw->desc->release_tx_desc(p, priv->mode);
1368

1369
		priv->dirty_tx++;
1370
	}
B
Beniamino Galvani 已提交
1371 1372 1373

	netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);

1374 1375 1376 1377
	if (unlikely(netif_queue_stopped(priv->dev) &&
		     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
		netif_tx_lock(priv->dev);
		if (netif_queue_stopped(priv->dev) &&
G
Giuseppe CAVALLARO 已提交
1378
		    stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1379 1380
			if (netif_msg_tx_done(priv))
				pr_debug("%s: restart transmit\n", __func__);
1381 1382 1383 1384
			netif_wake_queue(priv->dev);
		}
		netif_tx_unlock(priv->dev);
	}
1385 1386 1387

	if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
		stmmac_enable_eee_mode(priv);
G
Giuseppe CAVALLARO 已提交
1388
		mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1389
	}
1390
	spin_unlock(&priv->tx_lock);
1391 1392
}

1393
static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1394
{
1395
	priv->hw->dma->enable_dma_irq(priv->ioaddr);
1396 1397
}

1398
static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1399
{
1400
	priv->hw->dma->disable_dma_irq(priv->ioaddr);
1401 1402 1403
}

/**
1404
 * stmmac_tx_err - to manage the tx error
1405
 * @priv: driver private structure
1406
 * Description: it cleans the descriptors and restarts the transmission
1407
 * in case of transmission errors.
1408 1409 1410
 */
static void stmmac_tx_err(struct stmmac_priv *priv)
{
1411 1412
	int i;
	int txsize = priv->dma_tx_size;
1413 1414
	netif_stop_queue(priv->dev);

1415
	priv->hw->dma->stop_tx(priv->ioaddr);
1416
	dma_free_tx_skbufs(priv);
1417 1418 1419 1420 1421 1422 1423 1424 1425
	for (i = 0; i < txsize; i++)
		if (priv->extend_desc)
			priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
						     priv->mode,
						     (i == txsize - 1));
		else
			priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
						     priv->mode,
						     (i == txsize - 1));
1426 1427
	priv->dirty_tx = 0;
	priv->cur_tx = 0;
B
Beniamino Galvani 已提交
1428
	netdev_reset_queue(priv->dev);
1429
	priv->hw->dma->start_tx(priv->ioaddr);
1430 1431 1432 1433 1434

	priv->dev->stats.tx_errors++;
	netif_wake_queue(priv->dev);
}

1435
/**
1436
 * stmmac_dma_interrupt - DMA ISR
1437 1438
 * @priv: driver private structure
 * Description: this is the DMA ISR. It is called by the main ISR.
1439 1440
 * It calls the dwmac dma routine and schedule poll method in case of some
 * work can be done.
1441
 */
1442 1443 1444 1445
static void stmmac_dma_interrupt(struct stmmac_priv *priv)
{
	int status;

1446
	status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1447 1448 1449 1450 1451 1452 1453
	if (likely((status & handle_rx)) || (status & handle_tx)) {
		if (likely(napi_schedule_prep(&priv->napi))) {
			stmmac_disable_dma_irq(priv);
			__napi_schedule(&priv->napi);
		}
	}
	if (unlikely(status & tx_hard_error_bump_tc)) {
1454 1455 1456
		/* Try to bump up the dma threshold on this failure */
		if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
			tc += 64;
1457
			priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1458
			priv->xstats.threshold = tc;
1459
		}
1460 1461
	} else if (unlikely(status == tx_hard_error))
		stmmac_tx_err(priv);
1462 1463
}

1464 1465 1466 1467 1468
/**
 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
 * @priv: driver private structure
 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
 */
1469 1470 1471
static void stmmac_mmc_setup(struct stmmac_priv *priv)
{
	unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
G
Giuseppe CAVALLARO 已提交
1472
	    MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1473 1474

	dwmac_mmc_intr_all_mask(priv->ioaddr);
G
Giuseppe CAVALLARO 已提交
1475 1476 1477 1478 1479

	if (priv->dma_cap.rmon) {
		dwmac_mmc_ctrl(priv->ioaddr, mode);
		memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
	} else
1480
		pr_info(" No MAC Management Counters available\n");
1481 1482
}

1483 1484 1485 1486 1487 1488
/**
 * stmmac_get_synopsys_id - return the SYINID.
 * @priv: driver private structure
 * Description: this simple function is to decode and return the SYINID
 * starting from the HW core register.
 */
1489 1490 1491 1492
static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
{
	u32 hwid = priv->hw->synopsys_uid;

G
Giuseppe CAVALLARO 已提交
1493
	/* Check Synopsys Id (not available on old chips) */
1494 1495 1496 1497
	if (likely(hwid)) {
		u32 uid = ((hwid & 0x0000ff00) >> 8);
		u32 synid = (hwid & 0x000000ff);

1498
		pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1499 1500 1501 1502 1503 1504
			uid, synid);

		return synid;
	}
	return 0;
}
1505

1506
/**
1507
 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1508 1509
 * @priv: driver private structure
 * Description: select the Enhanced/Alternate or Normal descriptors.
1510 1511
 * In case of Enhanced/Alternate, it checks if the extended descriptors are
 * supported by the HW capability register.
1512
 */
1513 1514 1515 1516
static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
{
	if (priv->plat->enh_desc) {
		pr_info(" Enhanced/Alternate descriptors\n");
1517 1518 1519 1520 1521 1522 1523 1524

		/* GMAC older than 3.50 has no extended descriptors */
		if (priv->synopsys_id >= DWMAC_CORE_3_50) {
			pr_info("\tEnabled extended descriptors\n");
			priv->extend_desc = 1;
		} else
			pr_warn("Extended descriptors not supported\n");

1525 1526 1527 1528 1529 1530 1531 1532
		priv->hw->desc = &enh_desc_ops;
	} else {
		pr_info(" Normal descriptors\n");
		priv->hw->desc = &ndesc_ops;
	}
}

/**
1533
 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1534
 * @priv: driver private structure
1535 1536 1537 1538 1539
 * Description:
 *  new GMAC chip generations have a new register to indicate the
 *  presence of the optional feature/functions.
 *  This can be also used to override the value passed through the
 *  platform and necessary for old MAC10/100 and GMAC chips.
1540 1541 1542
 */
static int stmmac_get_hw_features(struct stmmac_priv *priv)
{
1543
	u32 hw_cap = 0;
1544

1545 1546
	if (priv->hw->dma->get_hw_feature) {
		hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1547

1548 1549 1550 1551
		priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
		priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
		priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
		priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
G
Giuseppe CAVALLARO 已提交
1552
		priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1553 1554 1555
		priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
		priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
		priv->dma_cap.pmt_remote_wake_up =
G
Giuseppe CAVALLARO 已提交
1556
		    (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1557
		priv->dma_cap.pmt_magic_frame =
G
Giuseppe CAVALLARO 已提交
1558
		    (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1559
		/* MMC */
1560
		priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
G
Giuseppe CAVALLARO 已提交
1561
		/* IEEE 1588-2002 */
1562
		priv->dma_cap.time_stamp =
G
Giuseppe CAVALLARO 已提交
1563 1564
		    (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
		/* IEEE 1588-2008 */
1565
		priv->dma_cap.atime_stamp =
G
Giuseppe CAVALLARO 已提交
1566
		    (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1567
		/* 802.3az - Energy-Efficient Ethernet (EEE) */
1568 1569
		priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
		priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1570
		/* TX and RX csum */
1571 1572
		priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
		priv->dma_cap.rx_coe_type1 =
G
Giuseppe CAVALLARO 已提交
1573
		    (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1574
		priv->dma_cap.rx_coe_type2 =
G
Giuseppe CAVALLARO 已提交
1575
		    (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1576
		priv->dma_cap.rxfifo_over_2048 =
G
Giuseppe CAVALLARO 已提交
1577
		    (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1578
		/* TX and RX number of channels */
1579
		priv->dma_cap.number_rx_channel =
G
Giuseppe CAVALLARO 已提交
1580
		    (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1581
		priv->dma_cap.number_tx_channel =
G
Giuseppe CAVALLARO 已提交
1582 1583 1584
		    (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
		/* Alternate (enhanced) DESC mode */
		priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1585
	}
1586 1587 1588 1589

	return hw_cap;
}

1590
/**
1591
 * stmmac_check_ether_addr - check if the MAC addr is valid
1592 1593 1594 1595 1596
 * @priv: driver private structure
 * Description:
 * it is to verify if the MAC address is valid, in case of failures it
 * generates a random MAC address
 */
1597 1598 1599
static void stmmac_check_ether_addr(struct stmmac_priv *priv)
{
	if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1600
		priv->hw->mac->get_umac_addr(priv->hw,
1601
					     priv->dev->dev_addr, 0);
G
Giuseppe CAVALLARO 已提交
1602
		if (!is_valid_ether_addr(priv->dev->dev_addr))
1603
			eth_hw_addr_random(priv->dev);
1604 1605
		pr_info("%s: device MAC address %pM\n", priv->dev->name,
			priv->dev->dev_addr);
1606 1607 1608
	}
}

1609
/**
1610
 * stmmac_init_dma_engine - DMA init.
1611 1612 1613 1614 1615 1616
 * @priv: driver private structure
 * Description:
 * It inits the DMA invoking the specific MAC/GMAC callback.
 * Some DMA parameters can be passed from the platform;
 * in case of these are not passed a default is kept for the MAC or GMAC.
 */
1617 1618 1619
static int stmmac_init_dma_engine(struct stmmac_priv *priv)
{
	int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1620
	int mixed_burst = 0;
1621
	int atds = 0;
1622 1623 1624 1625

	if (priv->plat->dma_cfg) {
		pbl = priv->plat->dma_cfg->pbl;
		fixed_burst = priv->plat->dma_cfg->fixed_burst;
1626
		mixed_burst = priv->plat->dma_cfg->mixed_burst;
1627 1628 1629
		burst_len = priv->plat->dma_cfg->burst_len;
	}

1630 1631 1632
	if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
		atds = 1;

1633
	return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1634
				   burst_len, priv->dma_tx_phy,
1635
				   priv->dma_rx_phy, atds);
1636 1637
}

1638
/**
1639
 * stmmac_tx_timer - mitigation sw timer for tx.
1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651
 * @data: data pointer
 * Description:
 * This is the timer handler to directly invoke the stmmac_tx_clean.
 */
static void stmmac_tx_timer(unsigned long data)
{
	struct stmmac_priv *priv = (struct stmmac_priv *)data;

	stmmac_tx_clean(priv);
}

/**
1652
 * stmmac_init_tx_coalesce - init tx mitigation options.
1653
 * @priv: driver private structure
1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669
 * Description:
 * This inits the transmit coalesce parameters: i.e. timer rate,
 * timer handler and default threshold used for enabling the
 * interrupt on completion bit.
 */
static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
{
	priv->tx_coal_frames = STMMAC_TX_FRAMES;
	priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
	init_timer(&priv->txtimer);
	priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
	priv->txtimer.data = (unsigned long)priv;
	priv->txtimer.function = stmmac_tx_timer;
	add_timer(&priv->txtimer);
}

1670
/**
1671
 * stmmac_hw_setup - setup mac in a usable state.
1672 1673
 *  @dev : pointer to the device structure.
 *  Description:
1674 1675 1676 1677
 *  this is the main function to setup the HW in a usable state because the
 *  dma engine is reset, the core registers are configured (e.g. AXI,
 *  Checksum features, timers). The DMA is ready to start receiving and
 *  transmitting.
1678 1679 1680 1681
 *  Return value:
 *  0 on success and an appropriate (-)ve integer as defined in errno.h
 *  file on failure.
 */
1682
static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694
{
	struct stmmac_priv *priv = netdev_priv(dev);
	int ret;

	/* DMA initialization and SW reset */
	ret = stmmac_init_dma_engine(priv);
	if (ret < 0) {
		pr_err("%s: DMA engine initialization failed\n", __func__);
		return ret;
	}

	/* Copy the MAC addr into the HW  */
1695
	priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1696 1697 1698 1699 1700 1701

	/* If required, perform hw setup of the bus. */
	if (priv->plat->bus_setup)
		priv->plat->bus_setup(priv->ioaddr);

	/* Initialize the MAC Core */
1702
	priv->hw->mac->core_init(priv->hw, dev->mtu);
1703

1704 1705 1706 1707
	ret = priv->hw->mac->rx_ipc(priv->hw);
	if (!ret) {
		pr_warn(" RX IPC Checksum Offload disabled\n");
		priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1708
		priv->hw->rx_csum = 0;
1709 1710
	}

1711 1712 1713 1714 1715 1716 1717 1718
	/* Enable the MAC Rx/Tx */
	stmmac_set_mac(priv->ioaddr, true);

	/* Set the HW DMA mode and the COE */
	stmmac_dma_operation_mode(priv);

	stmmac_mmc_setup(priv);

1719 1720 1721 1722 1723
	if (init_ptp) {
		ret = stmmac_init_ptp(priv);
		if (ret && ret != -EOPNOTSUPP)
			pr_warn("%s: failed PTP initialisation\n", __func__);
	}
1724

1725
#ifdef CONFIG_DEBUG_FS
1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736
	ret = stmmac_init_fs(dev);
	if (ret < 0)
		pr_warn("%s: failed debugFS registration\n", __func__);
#endif
	/* Start the ball rolling... */
	pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
	priv->hw->dma->start_tx(priv->ioaddr);
	priv->hw->dma->start_rx(priv->ioaddr);

	/* Dump DMA/MAC registers */
	if (netif_msg_hw(priv)) {
1737
		priv->hw->mac->dump_regs(priv->hw);
1738 1739 1740 1741 1742 1743 1744 1745 1746 1747
		priv->hw->dma->dump_regs(priv->ioaddr);
	}
	priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;

	if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
		priv->rx_riwt = MAX_DMA_RIWT;
		priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
	}

	if (priv->pcs && priv->hw->mac->ctrl_ane)
1748
		priv->hw->mac->ctrl_ane(priv->hw, 0);
1749 1750 1751 1752

	return 0;
}

1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
/**
 *  stmmac_open - open entry point of the driver
 *  @dev : pointer to the device structure.
 *  Description:
 *  This function is the open entry point of the driver.
 *  Return value:
 *  0 on success and an appropriate (-)ve integer as defined in errno.h
 *  file on failure.
 */
static int stmmac_open(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	int ret;

1767 1768
	stmmac_check_ether_addr(priv);

1769 1770
	if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
	    priv->pcs != STMMAC_PCS_RTBI) {
1771 1772 1773 1774
		ret = stmmac_init_phy(dev);
		if (ret) {
			pr_err("%s: Cannot attach to PHY (error: %d)\n",
			       __func__, ret);
1775
			return ret;
1776
		}
1777
	}
1778

1779 1780 1781 1782
	/* Extra statistics */
	memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
	priv->xstats.threshold = tc;

1783 1784 1785 1786
	/* Create and initialize the TX/RX descriptors chains. */
	priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
	priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
	priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1787

1788
	ret = alloc_dma_desc_resources(priv);
1789 1790 1791 1792 1793
	if (ret < 0) {
		pr_err("%s: DMA descriptors allocation failed\n", __func__);
		goto dma_desc_error;
	}

1794 1795 1796 1797 1798 1799
	ret = init_dma_desc_rings(dev, GFP_KERNEL);
	if (ret < 0) {
		pr_err("%s: DMA descriptors initialization failed\n", __func__);
		goto init_error;
	}

1800
	ret = stmmac_hw_setup(dev, true);
1801
	if (ret < 0) {
1802
		pr_err("%s: Hw setup failed\n", __func__);
1803
		goto init_error;
1804 1805
	}

1806 1807
	stmmac_init_tx_coalesce(priv);

1808 1809
	if (priv->phydev)
		phy_start(priv->phydev);
1810

1811 1812
	/* Request the IRQ lines */
	ret = request_irq(dev->irq, stmmac_interrupt,
G
Giuseppe CAVALLARO 已提交
1813
			  IRQF_SHARED, dev->name, dev);
1814 1815 1816
	if (unlikely(ret < 0)) {
		pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
		       __func__, dev->irq, ret);
1817
		goto init_error;
1818 1819
	}

1820 1821 1822 1823 1824
	/* Request the Wake IRQ in case of another line is used for WoL */
	if (priv->wol_irq != dev->irq) {
		ret = request_irq(priv->wol_irq, stmmac_interrupt,
				  IRQF_SHARED, dev->name, dev);
		if (unlikely(ret < 0)) {
G
Giuseppe CAVALLARO 已提交
1825 1826
			pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
			       __func__, priv->wol_irq, ret);
1827
			goto wolirq_error;
1828 1829 1830
		}
	}

1831
	/* Request the IRQ lines */
1832
	if (priv->lpi_irq > 0) {
1833 1834 1835 1836 1837
		ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
				  dev->name, dev);
		if (unlikely(ret < 0)) {
			pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
			       __func__, priv->lpi_irq, ret);
1838
			goto lpiirq_error;
1839 1840 1841
		}
	}

1842 1843
	napi_enable(&priv->napi);
	netif_start_queue(dev);
1844

1845
	return 0;
1846

1847
lpiirq_error:
1848 1849
	if (priv->wol_irq != dev->irq)
		free_irq(priv->wol_irq, dev);
1850
wolirq_error:
1851 1852
	free_irq(dev->irq, dev);

1853 1854
init_error:
	free_dma_desc_resources(priv);
1855
dma_desc_error:
1856 1857
	if (priv->phydev)
		phy_disconnect(priv->phydev);
1858

1859
	return ret;
1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871
}

/**
 *  stmmac_release - close entry point of the driver
 *  @dev : device pointer.
 *  Description:
 *  This is the stop entry point of the driver.
 */
static int stmmac_release(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);

1872 1873 1874
	if (priv->eee_enabled)
		del_timer_sync(&priv->eee_ctrl_timer);

1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885
	/* Stop and disconnect the PHY */
	if (priv->phydev) {
		phy_stop(priv->phydev);
		phy_disconnect(priv->phydev);
		priv->phydev = NULL;
	}

	netif_stop_queue(dev);

	napi_disable(&priv->napi);

1886 1887
	del_timer_sync(&priv->txtimer);

1888 1889
	/* Free the IRQ lines */
	free_irq(dev->irq, dev);
1890 1891
	if (priv->wol_irq != dev->irq)
		free_irq(priv->wol_irq, dev);
1892
	if (priv->lpi_irq > 0)
1893
		free_irq(priv->lpi_irq, dev);
1894 1895

	/* Stop TX/RX DMA and clear the descriptors */
1896 1897
	priv->hw->dma->stop_tx(priv->ioaddr);
	priv->hw->dma->stop_rx(priv->ioaddr);
1898 1899 1900 1901

	/* Release and free the Rx/Tx resources */
	free_dma_desc_resources(priv);

1902
	/* Disable the MAC Rx/Tx */
1903
	stmmac_set_mac(priv->ioaddr, false);
1904 1905 1906

	netif_carrier_off(dev);

1907
#ifdef CONFIG_DEBUG_FS
1908 1909 1910
	stmmac_exit_fs();
#endif

1911 1912
	stmmac_release_ptp(priv);

1913 1914 1915 1916
	return 0;
}

/**
1917
 *  stmmac_xmit - Tx entry point of the driver
1918 1919
 *  @skb : the socket buffer
 *  @dev : device pointer
1920 1921 1922
 *  Description : this is the tx entry point of the driver.
 *  It programs the chain or the ring and supports oversized frames
 *  and SG feature.
1923 1924 1925 1926 1927 1928
 */
static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	unsigned int txsize = priv->dma_tx_size;
	unsigned int entry;
1929
	int i, csum_insertion = 0, is_jumbo = 0;
1930 1931
	int nfrags = skb_shinfo(skb)->nr_frags;
	struct dma_desc *desc, *first;
1932
	unsigned int nopaged_len = skb_headlen(skb);
G
Giuseppe CAVALLARO 已提交
1933
	unsigned int enh_desc = priv->plat->enh_desc;
1934

1935 1936
	spin_lock(&priv->tx_lock);

1937
	if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1938
		spin_unlock(&priv->tx_lock);
1939 1940 1941
		if (!netif_queue_stopped(dev)) {
			netif_stop_queue(dev);
			/* This is a hard error, log it. */
G
Giuseppe CAVALLARO 已提交
1942
			pr_err("%s: Tx Ring full when queue awake\n", __func__);
1943 1944 1945 1946
		}
		return NETDEV_TX_BUSY;
	}

1947 1948 1949
	if (priv->tx_path_in_lpi_mode)
		stmmac_disable_eee_mode(priv);

1950 1951
	entry = priv->cur_tx % txsize;

1952
	csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1953

1954
	if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
1955
		desc = (struct dma_desc *)(priv->dma_etx + entry);
1956 1957 1958
	else
		desc = priv->dma_tx + entry;

1959 1960
	first = desc;

1961
	/* To program the descriptors according to the size of the frame */
G
Giuseppe CAVALLARO 已提交
1962 1963 1964
	if (enh_desc)
		is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);

1965
	if (likely(!is_jumbo)) {
1966
		desc->des2 = dma_map_single(priv->device, skb->data,
G
Giuseppe CAVALLARO 已提交
1967
					    nopaged_len, DMA_TO_DEVICE);
G
Giuseppe CAVALLARO 已提交
1968 1969 1970
		if (dma_mapping_error(priv->device, desc->des2))
			goto dma_map_err;
		priv->tx_skbuff_dma[entry].buf = desc->des2;
1971
		priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1972
						csum_insertion, priv->mode);
G
Giuseppe CAVALLARO 已提交
1973
	} else {
1974
		desc = first;
G
Giuseppe CAVALLARO 已提交
1975
		entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
G
Giuseppe CAVALLARO 已提交
1976 1977
		if (unlikely(entry < 0))
			goto dma_map_err;
G
Giuseppe CAVALLARO 已提交
1978
	}
1979 1980

	for (i = 0; i < nfrags; i++) {
E
Eric Dumazet 已提交
1981 1982
		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
		int len = skb_frag_size(frag);
1983

1984
		priv->tx_skbuff[entry] = NULL;
1985
		entry = (++priv->cur_tx) % txsize;
1986
		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
1987
			desc = (struct dma_desc *)(priv->dma_etx + entry);
1988 1989
		else
			desc = priv->dma_tx + entry;
1990

1991 1992
		desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
					      DMA_TO_DEVICE);
G
Giuseppe CAVALLARO 已提交
1993 1994 1995 1996 1997
		if (dma_mapping_error(priv->device, desc->des2))
			goto dma_map_err; /* should reuse desc w/o issues */

		priv->tx_skbuff_dma[entry].buf = desc->des2;
		priv->tx_skbuff_dma[entry].map_as_page = true;
1998 1999
		priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
						priv->mode);
2000
		wmb();
2001
		priv->hw->desc->set_tx_owner(desc);
2002
		wmb();
2003 2004
	}

2005 2006
	priv->tx_skbuff[entry] = skb;

2007
	/* Finalize the latest segment. */
2008
	priv->hw->desc->close_tx_desc(desc);
2009

2010
	wmb();
2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
	/* According to the coalesce parameter the IC bit for the latest
	 * segment could be reset and the timer re-started to invoke the
	 * stmmac_tx function. This approach takes care about the fragments.
	 */
	priv->tx_count_frames += nfrags + 1;
	if (priv->tx_coal_frames > priv->tx_count_frames) {
		priv->hw->desc->clear_tx_ic(desc);
		priv->xstats.tx_reset_ic_bit++;
		mod_timer(&priv->txtimer,
			  STMMAC_COAL_TIMER(priv->tx_coal_timer));
	} else
		priv->tx_count_frames = 0;
2023

2024
	/* To avoid raise condition */
2025
	priv->hw->desc->set_tx_owner(first);
2026
	wmb();
2027 2028 2029 2030

	priv->cur_tx++;

	if (netif_msg_pktdata(priv)) {
2031
		pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
G
Giuseppe CAVALLARO 已提交
2032 2033
			__func__, (priv->cur_tx % txsize),
			(priv->dirty_tx % txsize), entry, first, nfrags);
2034

2035 2036 2037 2038 2039
		if (priv->extend_desc)
			stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
		else
			stmmac_display_ring((void *)priv->dma_tx, txsize, 0);

2040
		pr_debug(">>> frame to be transmitted: ");
2041 2042 2043
		print_pkt(skb->data, skb->len);
	}
	if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2044 2045
		if (netif_msg_hw(priv))
			pr_debug("%s: stop transmitted packets\n", __func__);
2046 2047 2048 2049 2050
		netif_stop_queue(dev);
	}

	dev->stats.tx_bytes += skb->len;

2051 2052 2053 2054 2055 2056 2057 2058 2059
	if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
		     priv->hwts_tx_en)) {
		/* declare that device is doing timestamping */
		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
		priv->hw->desc->enable_tx_timestamp(first);
	}

	if (!priv->hwts_tx_en)
		skb_tx_timestamp(skb);
2060

B
Beniamino Galvani 已提交
2061
	netdev_sent_queue(dev, skb->len);
2062 2063
	priv->hw->dma->enable_dma_transmission(priv->ioaddr);

2064
	spin_unlock(&priv->tx_lock);
G
Giuseppe CAVALLARO 已提交
2065
	return NETDEV_TX_OK;
2066

G
Giuseppe CAVALLARO 已提交
2067
dma_map_err:
2068
	spin_unlock(&priv->tx_lock);
G
Giuseppe CAVALLARO 已提交
2069 2070 2071
	dev_err(priv->device, "Tx dma map failed\n");
	dev_kfree_skb(skb);
	priv->dev->stats.tx_dropped++;
2072 2073 2074
	return NETDEV_TX_OK;
}

2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091
static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
{
	struct ethhdr *ehdr;
	u16 vlanid;

	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
	    NETIF_F_HW_VLAN_CTAG_RX &&
	    !__vlan_get_tag(skb, &vlanid)) {
		/* pop the vlan tag */
		ehdr = (struct ethhdr *)skb->data;
		memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
		skb_pull(skb, VLAN_HLEN);
		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
	}
}


2092
/**
2093
 * stmmac_rx_refill - refill used skb preallocated buffers
2094 2095 2096 2097
 * @priv: driver private structure
 * Description : this is to reallocate the skb for the reception process
 * that is based on zero-copy.
 */
2098 2099 2100 2101 2102 2103 2104
static inline void stmmac_rx_refill(struct stmmac_priv *priv)
{
	unsigned int rxsize = priv->dma_rx_size;
	int bfsize = priv->dma_buf_sz;

	for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
		unsigned int entry = priv->dirty_rx % rxsize;
2105 2106 2107
		struct dma_desc *p;

		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
2108
			p = (struct dma_desc *)(priv->dma_erx + entry);
2109 2110 2111
		else
			p = priv->dma_rx + entry;

2112 2113 2114
		if (likely(priv->rx_skbuff[entry] == NULL)) {
			struct sk_buff *skb;

E
Eric Dumazet 已提交
2115
			skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2116 2117 2118 2119 2120 2121 2122 2123

			if (unlikely(skb == NULL))
				break;

			priv->rx_skbuff[entry] = skb;
			priv->rx_skbuff_dma[entry] =
			    dma_map_single(priv->device, skb->data, bfsize,
					   DMA_FROM_DEVICE);
G
Giuseppe CAVALLARO 已提交
2124 2125 2126 2127 2128 2129
			if (dma_mapping_error(priv->device,
					      priv->rx_skbuff_dma[entry])) {
				dev_err(priv->device, "Rx dma map failed\n");
				dev_kfree_skb(skb);
				break;
			}
2130
			p->des2 = priv->rx_skbuff_dma[entry];
2131

G
Giuseppe CAVALLARO 已提交
2132
			priv->hw->mode->refill_desc3(priv, p);
2133

2134 2135
			if (netif_msg_rx_status(priv))
				pr_debug("\trefill entry #%d\n", entry);
2136
		}
2137
		wmb();
2138
		priv->hw->desc->set_rx_owner(p);
2139
		wmb();
2140 2141 2142
	}
}

2143
/**
2144
 * stmmac_rx - manage the receive process
2145 2146 2147 2148 2149
 * @priv: driver private structure
 * @limit: napi bugget.
 * Description :  this the function called by the napi poll method.
 * It gets all the frames inside the ring.
 */
2150 2151 2152 2153 2154 2155
static int stmmac_rx(struct stmmac_priv *priv, int limit)
{
	unsigned int rxsize = priv->dma_rx_size;
	unsigned int entry = priv->cur_rx % rxsize;
	unsigned int next_entry;
	unsigned int count = 0;
2156
	int coe = priv->hw->rx_csum;
2157

2158 2159
	if (netif_msg_rx_status(priv)) {
		pr_debug("%s: descriptor ring:\n", __func__);
2160
		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
2161
			stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2162 2163
		else
			stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2164
	}
2165
	while (count < limit) {
2166
		int status;
2167
		struct dma_desc *p;
2168

2169
		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
2170
			p = (struct dma_desc *)(priv->dma_erx + entry);
2171
		else
G
Giuseppe CAVALLARO 已提交
2172
			p = priv->dma_rx + entry;
2173 2174

		if (priv->hw->desc->get_rx_owner(p))
2175 2176 2177 2178 2179
			break;

		count++;

		next_entry = (++priv->cur_rx) % rxsize;
2180
		if (priv->extend_desc)
2181
			prefetch(priv->dma_erx + next_entry);
2182
		else
2183
			prefetch(priv->dma_rx + next_entry);
2184 2185

		/* read the status of the incoming frame */
2186 2187 2188 2189 2190 2191 2192
		status = priv->hw->desc->rx_status(&priv->dev->stats,
						   &priv->xstats, p);
		if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
			priv->hw->desc->rx_extended_status(&priv->dev->stats,
							   &priv->xstats,
							   priv->dma_erx +
							   entry);
2193
		if (unlikely(status == discard_frame)) {
2194
			priv->dev->stats.rx_errors++;
2195 2196 2197 2198 2199 2200 2201 2202
			if (priv->hwts_rx_en && !priv->extend_desc) {
				/* DESC2 & DESC3 will be overwitten by device
				 * with timestamp value, hence reinitialize
				 * them in stmmac_rx_refill() function so that
				 * device can reuse it.
				 */
				priv->rx_skbuff[entry] = NULL;
				dma_unmap_single(priv->device,
G
Giuseppe CAVALLARO 已提交
2203 2204 2205
						 priv->rx_skbuff_dma[entry],
						 priv->dma_buf_sz,
						 DMA_FROM_DEVICE);
2206 2207
			}
		} else {
2208
			struct sk_buff *skb;
2209
			int frame_len;
2210

G
Giuseppe CAVALLARO 已提交
2211 2212
			frame_len = priv->hw->desc->get_rx_frame_len(p, coe);

2213
			/* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
G
Giuseppe CAVALLARO 已提交
2214 2215
			 * Type frames (LLC/LLC-SNAP)
			 */
2216 2217
			if (unlikely(status != llc_snap))
				frame_len -= ETH_FCS_LEN;
2218

2219
			if (netif_msg_rx_status(priv)) {
2220
				pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
G
Giuseppe CAVALLARO 已提交
2221
					 p, entry, p->des2);
2222 2223 2224 2225
				if (frame_len > ETH_FRAME_LEN)
					pr_debug("\tframe size %d, COE: %d\n",
						 frame_len, status);
			}
2226 2227 2228
			skb = priv->rx_skbuff[entry];
			if (unlikely(!skb)) {
				pr_err("%s: Inconsistent Rx descriptor chain\n",
G
Giuseppe CAVALLARO 已提交
2229
				       priv->dev->name);
2230 2231 2232 2233 2234 2235
				priv->dev->stats.rx_dropped++;
				break;
			}
			prefetch(skb->data - NET_IP_ALIGN);
			priv->rx_skbuff[entry] = NULL;

2236 2237
			stmmac_get_rx_hwtstamp(priv, entry, skb);

2238 2239 2240 2241
			skb_put(skb, frame_len);
			dma_unmap_single(priv->device,
					 priv->rx_skbuff_dma[entry],
					 priv->dma_buf_sz, DMA_FROM_DEVICE);
2242

2243
			if (netif_msg_pktdata(priv)) {
2244
				pr_debug("frame received (%dbytes)", frame_len);
2245 2246
				print_pkt(skb->data, frame_len);
			}
2247

2248 2249
			stmmac_rx_vlan(priv->dev, skb);

2250 2251
			skb->protocol = eth_type_trans(skb, priv->dev);

G
Giuseppe CAVALLARO 已提交
2252
			if (unlikely(!coe))
2253
				skb_checksum_none_assert(skb);
2254
			else
2255
				skb->ip_summed = CHECKSUM_UNNECESSARY;
2256 2257

			napi_gro_receive(&priv->napi, skb);
2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277

			priv->dev->stats.rx_packets++;
			priv->dev->stats.rx_bytes += frame_len;
		}
		entry = next_entry;
	}

	stmmac_rx_refill(priv);

	priv->xstats.rx_pkt_n += count;

	return count;
}

/**
 *  stmmac_poll - stmmac poll method (NAPI)
 *  @napi : pointer to the napi structure.
 *  @budget : maximum number of packets that the current CPU can receive from
 *	      all interfaces.
 *  Description :
2278
 *  To look at the incoming frames and clear the tx resources.
2279 2280 2281 2282 2283 2284
 */
static int stmmac_poll(struct napi_struct *napi, int budget)
{
	struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
	int work_done = 0;

2285 2286
	priv->xstats.napi_poll++;
	stmmac_tx_clean(priv);
2287

2288
	work_done = stmmac_rx(priv, budget);
2289 2290
	if (work_done < budget) {
		napi_complete(napi);
2291
		stmmac_enable_dma_irq(priv);
2292 2293 2294 2295 2296 2297 2298 2299
	}
	return work_done;
}

/**
 *  stmmac_tx_timeout
 *  @dev : Pointer to net device structure
 *  Description: this function is called when a packet transmission fails to
2300
 *   complete within a reasonable time. The driver will mark the error in the
2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312
 *   netdev structure and arrange for the device to be reset to a sane state
 *   in order to transmit a new packet.
 */
static void stmmac_tx_timeout(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);

	/* Clear Tx resources and restart transmitting again */
	stmmac_tx_err(priv);
}

/**
2313
 *  stmmac_set_rx_mode - entry point for multicast addressing
2314 2315 2316 2317 2318 2319 2320
 *  @dev : pointer to the device structure
 *  Description:
 *  This function is a driver entry point which gets called by the kernel
 *  whenever multicast addresses must be enabled/disabled.
 *  Return value:
 *  void.
 */
2321
static void stmmac_set_rx_mode(struct net_device *dev)
2322 2323 2324
{
	struct stmmac_priv *priv = netdev_priv(dev);

2325
	priv->hw->mac->set_filter(priv->hw, dev);
2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348
}

/**
 *  stmmac_change_mtu - entry point to change MTU size for the device.
 *  @dev : device pointer.
 *  @new_mtu : the new MTU size for the device.
 *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
 *  to drive packet transmission. Ethernet has an MTU of 1500 octets
 *  (ETH_DATA_LEN). This value can be changed with ifconfig.
 *  Return value:
 *  0 on success and an appropriate (-)ve integer as defined in errno.h
 *  file on failure.
 */
static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	int max_mtu;

	if (netif_running(dev)) {
		pr_err("%s: must be stopped to change its MTU\n", dev->name);
		return -EBUSY;
	}

2349
	if (priv->plat->enh_desc)
2350 2351
		max_mtu = JUMBO_LEN;
	else
2352
		max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2353

2354 2355 2356
	if (priv->plat->maxmtu < max_mtu)
		max_mtu = priv->plat->maxmtu;

2357 2358 2359 2360 2361
	if ((new_mtu < 46) || (new_mtu > max_mtu)) {
		pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
		return -EINVAL;
	}

2362 2363 2364 2365 2366 2367
	dev->mtu = new_mtu;
	netdev_update_features(dev);

	return 0;
}

2368
static netdev_features_t stmmac_fix_features(struct net_device *dev,
G
Giuseppe CAVALLARO 已提交
2369
					     netdev_features_t features)
2370 2371 2372
{
	struct stmmac_priv *priv = netdev_priv(dev);

2373
	if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2374
		features &= ~NETIF_F_RXCSUM;
2375

2376 2377 2378
	if (!priv->plat->tx_coe)
		features &= ~NETIF_F_ALL_CSUM;

2379 2380 2381
	/* Some GMAC devices have a bugged Jumbo frame support that
	 * needs to have the Tx COE disabled for oversized frames
	 * (due to limited buffer sizes). In this case we disable
G
Giuseppe CAVALLARO 已提交
2382 2383
	 * the TX csum insertionin the TDES and not use SF.
	 */
2384 2385
	if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
		features &= ~NETIF_F_ALL_CSUM;
2386

2387
	return features;
2388 2389
}

2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407
static int stmmac_set_features(struct net_device *netdev,
			       netdev_features_t features)
{
	struct stmmac_priv *priv = netdev_priv(netdev);

	/* Keep the COE Type in case of csum is supporting */
	if (features & NETIF_F_RXCSUM)
		priv->hw->rx_csum = priv->plat->rx_coe;
	else
		priv->hw->rx_csum = 0;
	/* No check needed because rx_coe has been set before and it will be
	 * fixed in case of issue.
	 */
	priv->hw->mac->rx_ipc(priv->hw);

	return 0;
}

2408 2409 2410 2411 2412
/**
 *  stmmac_interrupt - main ISR
 *  @irq: interrupt number.
 *  @dev_id: to pass the net device pointer.
 *  Description: this is the main driver interrupt service routine.
2413 2414 2415 2416 2417
 *  It can call:
 *  o DMA service routine (to manage incoming frame reception and transmission
 *    status)
 *  o Core interrupts to manage: remote wake-up, management counter, LPI
 *    interrupts.
2418
 */
2419 2420 2421 2422 2423
static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
{
	struct net_device *dev = (struct net_device *)dev_id;
	struct stmmac_priv *priv = netdev_priv(dev);

2424 2425 2426
	if (priv->irq_wake)
		pm_wakeup_event(priv->device, 0);

2427 2428 2429 2430 2431
	if (unlikely(!dev)) {
		pr_err("%s: invalid dev pointer\n", __func__);
		return IRQ_NONE;
	}

2432 2433
	/* To handle GMAC own interrupts */
	if (priv->plat->has_gmac) {
2434
		int status = priv->hw->mac->host_irq_status(priv->hw,
2435
							    &priv->xstats);
2436 2437
		if (unlikely(status)) {
			/* For LPI we need to save the tx status */
2438
			if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2439
				priv->tx_path_in_lpi_mode = true;
2440
			if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2441 2442 2443
				priv->tx_path_in_lpi_mode = false;
		}
	}
2444

2445
	/* To handle DMA interrupts */
2446
	stmmac_dma_interrupt(priv);
2447 2448 2449 2450 2451 2452

	return IRQ_HANDLED;
}

#ifdef CONFIG_NET_POLL_CONTROLLER
/* Polling receive - used by NETCONSOLE and other diagnostic tools
G
Giuseppe CAVALLARO 已提交
2453 2454
 * to allow network I/O with interrupts disabled.
 */
2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469
static void stmmac_poll_controller(struct net_device *dev)
{
	disable_irq(dev->irq);
	stmmac_interrupt(dev->irq, dev);
	enable_irq(dev->irq);
}
#endif

/**
 *  stmmac_ioctl - Entry point for the Ioctl
 *  @dev: Device pointer.
 *  @rq: An IOCTL specefic structure, that can contain a pointer to
 *  a proprietary structure used to pass information to the driver.
 *  @cmd: IOCTL command
 *  Description:
2470
 *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2471 2472 2473 2474
 */
static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
	struct stmmac_priv *priv = netdev_priv(dev);
2475
	int ret = -EOPNOTSUPP;
2476 2477 2478 2479

	if (!netif_running(dev))
		return -EINVAL;

2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493
	switch (cmd) {
	case SIOCGMIIPHY:
	case SIOCGMIIREG:
	case SIOCSMIIREG:
		if (!priv->phydev)
			return -EINVAL;
		ret = phy_mii_ioctl(priv->phydev, rq, cmd);
		break;
	case SIOCSHWTSTAMP:
		ret = stmmac_hwtstamp_ioctl(dev, rq);
		break;
	default:
		break;
	}
2494

2495 2496 2497
	return ret;
}

2498
#ifdef CONFIG_DEBUG_FS
2499 2500
static struct dentry *stmmac_fs_dir;
static struct dentry *stmmac_rings_status;
2501
static struct dentry *stmmac_dma_cap;
2502

2503
static void sysfs_display_ring(void *head, int size, int extend_desc,
G
Giuseppe CAVALLARO 已提交
2504
			       struct seq_file *seq)
2505 2506
{
	int i;
G
Giuseppe CAVALLARO 已提交
2507 2508
	struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
	struct dma_desc *p = (struct dma_desc *)head;
2509

2510 2511 2512 2513 2514
	for (i = 0; i < size; i++) {
		u64 x;
		if (extend_desc) {
			x = *(u64 *) ep;
			seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
G
Giuseppe CAVALLARO 已提交
2515 2516
				   i, (unsigned int)virt_to_phys(ep),
				   (unsigned int)x, (unsigned int)(x >> 32),
2517 2518 2519 2520 2521
				   ep->basic.des2, ep->basic.des3);
			ep++;
		} else {
			x = *(u64 *) p;
			seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
G
Giuseppe CAVALLARO 已提交
2522 2523
				   i, (unsigned int)virt_to_phys(ep),
				   (unsigned int)x, (unsigned int)(x >> 32),
2524 2525 2526
				   p->des2, p->des3);
			p++;
		}
2527 2528
		seq_printf(seq, "\n");
	}
2529
}
2530

2531 2532 2533 2534 2535 2536
static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
{
	struct net_device *dev = seq->private;
	struct stmmac_priv *priv = netdev_priv(dev);
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;
2537

2538 2539
	if (priv->extend_desc) {
		seq_printf(seq, "Extended RX descriptor ring:\n");
G
Giuseppe CAVALLARO 已提交
2540
		sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2541
		seq_printf(seq, "Extended TX descriptor ring:\n");
G
Giuseppe CAVALLARO 已提交
2542
		sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2543 2544 2545 2546 2547
	} else {
		seq_printf(seq, "RX descriptor ring:\n");
		sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
		seq_printf(seq, "TX descriptor ring:\n");
		sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562
	}

	return 0;
}

static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
{
	return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
}

static const struct file_operations stmmac_rings_status_fops = {
	.owner = THIS_MODULE,
	.open = stmmac_sysfs_ring_open,
	.read = seq_read,
	.llseek = seq_lseek,
2563
	.release = single_release,
2564 2565
};

2566 2567 2568 2569 2570
static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
{
	struct net_device *dev = seq->private;
	struct stmmac_priv *priv = netdev_priv(dev);

2571
	if (!priv->hw_cap_support) {
2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634
		seq_printf(seq, "DMA HW features not supported\n");
		return 0;
	}

	seq_printf(seq, "==============================\n");
	seq_printf(seq, "\tDMA HW features\n");
	seq_printf(seq, "==============================\n");

	seq_printf(seq, "\t10/100 Mbps %s\n",
		   (priv->dma_cap.mbps_10_100) ? "Y" : "N");
	seq_printf(seq, "\t1000 Mbps %s\n",
		   (priv->dma_cap.mbps_1000) ? "Y" : "N");
	seq_printf(seq, "\tHalf duple %s\n",
		   (priv->dma_cap.half_duplex) ? "Y" : "N");
	seq_printf(seq, "\tHash Filter: %s\n",
		   (priv->dma_cap.hash_filter) ? "Y" : "N");
	seq_printf(seq, "\tMultiple MAC address registers: %s\n",
		   (priv->dma_cap.multi_addr) ? "Y" : "N");
	seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
		   (priv->dma_cap.pcs) ? "Y" : "N");
	seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
		   (priv->dma_cap.sma_mdio) ? "Y" : "N");
	seq_printf(seq, "\tPMT Remote wake up: %s\n",
		   (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
	seq_printf(seq, "\tPMT Magic Frame: %s\n",
		   (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
	seq_printf(seq, "\tRMON module: %s\n",
		   (priv->dma_cap.rmon) ? "Y" : "N");
	seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
		   (priv->dma_cap.time_stamp) ? "Y" : "N");
	seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
		   (priv->dma_cap.atime_stamp) ? "Y" : "N");
	seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
		   (priv->dma_cap.eee) ? "Y" : "N");
	seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
	seq_printf(seq, "\tChecksum Offload in TX: %s\n",
		   (priv->dma_cap.tx_coe) ? "Y" : "N");
	seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
		   (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
	seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
		   (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
	seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
		   (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
	seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
		   priv->dma_cap.number_rx_channel);
	seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
		   priv->dma_cap.number_tx_channel);
	seq_printf(seq, "\tEnhanced descriptors: %s\n",
		   (priv->dma_cap.enh_desc) ? "Y" : "N");

	return 0;
}

static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
{
	return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
}

static const struct file_operations stmmac_dma_cap_fops = {
	.owner = THIS_MODULE,
	.open = stmmac_sysfs_dma_cap_open,
	.read = seq_read,
	.llseek = seq_lseek,
2635
	.release = single_release,
2636 2637
};

2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651
static int stmmac_init_fs(struct net_device *dev)
{
	/* Create debugfs entries */
	stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);

	if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
		pr_err("ERROR %s, debugfs create directory failed\n",
		       STMMAC_RESOURCE_NAME);

		return -ENOMEM;
	}

	/* Entry to report DMA RX/TX rings */
	stmmac_rings_status = debugfs_create_file("descriptors_status",
G
Giuseppe CAVALLARO 已提交
2652 2653
						  S_IRUGO, stmmac_fs_dir, dev,
						  &stmmac_rings_status_fops);
2654 2655 2656 2657 2658 2659 2660 2661

	if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
		pr_info("ERROR creating stmmac ring debugfs file\n");
		debugfs_remove(stmmac_fs_dir);

		return -ENOMEM;
	}

2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673
	/* Entry to report the DMA HW features */
	stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
					     dev, &stmmac_dma_cap_fops);

	if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
		pr_info("ERROR creating stmmac MMC debugfs file\n");
		debugfs_remove(stmmac_rings_status);
		debugfs_remove(stmmac_fs_dir);

		return -ENOMEM;
	}

2674 2675 2676 2677 2678 2679
	return 0;
}

static void stmmac_exit_fs(void)
{
	debugfs_remove(stmmac_rings_status);
2680
	debugfs_remove(stmmac_dma_cap);
2681 2682
	debugfs_remove(stmmac_fs_dir);
}
2683
#endif /* CONFIG_DEBUG_FS */
2684

2685 2686 2687 2688 2689
static const struct net_device_ops stmmac_netdev_ops = {
	.ndo_open = stmmac_open,
	.ndo_start_xmit = stmmac_xmit,
	.ndo_stop = stmmac_release,
	.ndo_change_mtu = stmmac_change_mtu,
2690
	.ndo_fix_features = stmmac_fix_features,
2691
	.ndo_set_features = stmmac_set_features,
2692
	.ndo_set_rx_mode = stmmac_set_rx_mode,
2693 2694 2695 2696 2697 2698 2699 2700
	.ndo_tx_timeout = stmmac_tx_timeout,
	.ndo_do_ioctl = stmmac_ioctl,
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller = stmmac_poll_controller,
#endif
	.ndo_set_mac_address = eth_mac_addr,
};

2701 2702
/**
 *  stmmac_hw_init - Init the MAC device
2703
 *  @priv: driver private structure
2704 2705 2706 2707
 *  Description: this function is to configure the MAC device according to
 *  some platform parameters or the HW capability register. It prepares the
 *  driver to use either ring or chain modes and to setup either enhanced or
 *  normal descriptors.
2708 2709 2710 2711 2712 2713
 */
static int stmmac_hw_init(struct stmmac_priv *priv)
{
	struct mac_device_info *mac;

	/* Identify the MAC HW device */
2714 2715
	if (priv->plat->has_gmac) {
		priv->dev->priv_flags |= IFF_UNICAST_FLT;
2716 2717 2718
		mac = dwmac1000_setup(priv->ioaddr,
				      priv->plat->multicast_filter_bins,
				      priv->plat->unicast_filter_entries);
2719
	} else {
2720
		mac = dwmac100_setup(priv->ioaddr);
2721
	}
2722 2723 2724 2725 2726 2727
	if (!mac)
		return -ENOMEM;

	priv->hw = mac;

	/* Get and dump the chip ID */
2728
	priv->synopsys_id = stmmac_get_synopsys_id(priv);
2729

2730
	/* To use the chained or ring mode */
G
Giuseppe CAVALLARO 已提交
2731
	if (chain_mode) {
G
Giuseppe CAVALLARO 已提交
2732
		priv->hw->mode = &chain_mode_ops;
2733 2734 2735
		pr_info(" Chain mode enabled\n");
		priv->mode = STMMAC_CHAIN_MODE;
	} else {
G
Giuseppe CAVALLARO 已提交
2736
		priv->hw->mode = &ring_mode_ops;
2737 2738 2739 2740
		pr_info(" Ring mode enabled\n");
		priv->mode = STMMAC_RING_MODE;
	}

2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752
	/* Get the HW capability (new GMAC newer than 3.50a) */
	priv->hw_cap_support = stmmac_get_hw_features(priv);
	if (priv->hw_cap_support) {
		pr_info(" DMA HW capability register supported");

		/* We can override some gmac/dma configuration fields: e.g.
		 * enh_desc, tx_coe (e.g. that are passed through the
		 * platform) with the values from the HW capability
		 * register (if supported).
		 */
		priv->plat->enh_desc = priv->dma_cap.enh_desc;
		priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2753 2754 2755 2756 2757 2758 2759 2760

		priv->plat->tx_coe = priv->dma_cap.tx_coe;

		if (priv->dma_cap.rx_coe_type2)
			priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
		else if (priv->dma_cap.rx_coe_type1)
			priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;

2761 2762 2763
	} else
		pr_info(" No HW DMA feature register supported");

2764 2765 2766
	/* To use alternate (extended) or normal descriptor structures */
	stmmac_selec_desc_mode(priv);

2767 2768
	if (priv->plat->rx_coe) {
		priv->hw->rx_csum = priv->plat->rx_coe;
2769 2770
		pr_info(" RX Checksum Offload Engine supported (type %d)\n",
			priv->plat->rx_coe);
2771
	}
2772 2773 2774 2775 2776 2777 2778 2779
	if (priv->plat->tx_coe)
		pr_info(" TX Checksum insertion supported\n");

	if (priv->plat->pmt) {
		pr_info(" Wake-Up On Lan supported\n");
		device_set_wakeup_capable(priv->device, 1);
	}

2780
	return 0;
2781 2782
}

2783
/**
2784 2785
 * stmmac_dvr_probe
 * @device: device pointer
2786 2787
 * @plat_dat: platform data pointer
 * @addr: iobase memory address
2788 2789
 * Description: this is the main probe function used to
 * call the alloc_etherdev, allocate the priv structure.
2790
 */
2791
struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2792 2793
				     struct plat_stmmacenet_data *plat_dat,
				     void __iomem *addr)
2794 2795
{
	int ret = 0;
2796 2797
	struct net_device *ndev = NULL;
	struct stmmac_priv *priv;
2798

2799
	ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2800
	if (!ndev)
2801 2802 2803 2804 2805 2806 2807
		return NULL;

	SET_NETDEV_DEV(ndev, device);

	priv = netdev_priv(ndev);
	priv->device = device;
	priv->dev = ndev;
2808

2809
	stmmac_set_ethtool_ops(ndev);
2810 2811 2812 2813 2814 2815 2816
	priv->pause = pause;
	priv->plat = plat_dat;
	priv->ioaddr = addr;
	priv->dev->base_addr = (unsigned long)addr;

	/* Verify driver arguments */
	stmmac_verify_args();
2817

2818
	/* Override with kernel parameters if supplied XXX CRS XXX
G
Giuseppe CAVALLARO 已提交
2819 2820
	 * this needs to have multiple instances
	 */
2821 2822 2823
	if ((phyaddr >= 0) && (phyaddr <= 31))
		priv->plat->phy_addr = phyaddr;

2824 2825 2826 2827
	priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
	if (IS_ERR(priv->stmmac_clk)) {
		dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
			 __func__);
2828 2829 2830 2831 2832 2833 2834 2835 2836
		/* If failed to obtain stmmac_clk and specific clk_csr value
		 * is NOT passed from the platform, probe fail.
		 */
		if (!priv->plat->clk_csr) {
			ret = PTR_ERR(priv->stmmac_clk);
			goto error_clk_get;
		} else {
			priv->stmmac_clk = NULL;
		}
2837 2838 2839
	}
	clk_prepare_enable(priv->stmmac_clk);

2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852
	priv->stmmac_rst = devm_reset_control_get(priv->device,
						  STMMAC_RESOURCE_NAME);
	if (IS_ERR(priv->stmmac_rst)) {
		if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
			ret = -EPROBE_DEFER;
			goto error_hw_init;
		}
		dev_info(priv->device, "no reset control found\n");
		priv->stmmac_rst = NULL;
	}
	if (priv->stmmac_rst)
		reset_control_deassert(priv->stmmac_rst);

2853
	/* Init MAC and get the capabilities */
2854 2855
	ret = stmmac_hw_init(priv);
	if (ret)
2856
		goto error_hw_init;
2857 2858

	ndev->netdev_ops = &stmmac_netdev_ops;
2859

2860 2861
	ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
			    NETIF_F_RXCSUM;
2862 2863
	ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
	ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2864 2865
#ifdef STMMAC_VLAN_TAG_USED
	/* Both mac100 and gmac support receive VLAN tag detection */
2866
	ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2867 2868 2869 2870 2871 2872
#endif
	priv->msg_enable = netif_msg_init(debug, default_msg_level);

	if (flow_ctrl)
		priv->flow_ctrl = FLOW_AUTO;	/* RX/TX pause on */

2873 2874 2875 2876 2877 2878 2879 2880 2881 2882
	/* Rx Watchdog is available in the COREs newer than the 3.40.
	 * In some case, for example on bugged HW this feature
	 * has to be disable and this can be done by passing the
	 * riwt_off field from the platform.
	 */
	if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
		priv->use_riwt = 1;
		pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
	}

2883
	netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2884

2885
	spin_lock_init(&priv->lock);
2886
	spin_lock_init(&priv->tx_lock);
2887

2888
	ret = register_netdev(ndev);
2889
	if (ret) {
2890
		pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2891
		goto error_netdev_register;
2892 2893
	}

2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904
	/* If a specific clk_csr value is passed from the platform
	 * this means that the CSR Clock Range selection cannot be
	 * changed at run-time and it is fixed. Viceversa the driver'll try to
	 * set the MDC clock dynamically according to the csr actual
	 * clock input.
	 */
	if (!priv->plat->clk_csr)
		stmmac_clk_csr_set(priv);
	else
		priv->clk_csr = priv->plat->clk_csr;

2905 2906
	stmmac_check_pcs_mode(priv);

2907 2908
	if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
	    priv->pcs != STMMAC_PCS_RTBI) {
2909 2910 2911 2912 2913 2914 2915
		/* MDIO bus Registration */
		ret = stmmac_mdio_register(ndev);
		if (ret < 0) {
			pr_debug("%s: MDIO bus (id: %d) registration failed",
				 __func__, priv->plat->bus_id);
			goto error_mdio_register;
		}
2916 2917
	}

2918
	return priv;
2919

2920
error_mdio_register:
2921
	unregister_netdev(ndev);
2922 2923
error_netdev_register:
	netif_napi_del(&priv->napi);
2924 2925 2926
error_hw_init:
	clk_disable_unprepare(priv->stmmac_clk);
error_clk_get:
2927
	free_netdev(ndev);
2928

2929
	return ERR_PTR(ret);
2930
}
2931
EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2932 2933 2934

/**
 * stmmac_dvr_remove
2935
 * @ndev: net device pointer
2936
 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2937
 * changes the link status, releases the DMA descriptor rings.
2938
 */
2939
int stmmac_dvr_remove(struct net_device *ndev)
2940
{
2941
	struct stmmac_priv *priv = netdev_priv(ndev);
2942 2943 2944

	pr_info("%s:\n\tremoving driver", __func__);

2945 2946
	priv->hw->dma->stop_rx(priv->ioaddr);
	priv->hw->dma->stop_tx(priv->ioaddr);
2947

2948
	stmmac_set_mac(priv->ioaddr, false);
2949 2950
	if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
	    priv->pcs != STMMAC_PCS_RTBI)
2951
		stmmac_mdio_unregister(ndev);
2952 2953
	netif_carrier_off(ndev);
	unregister_netdev(ndev);
2954 2955
	if (priv->stmmac_rst)
		reset_control_assert(priv->stmmac_rst);
2956
	clk_disable_unprepare(priv->stmmac_clk);
2957 2958 2959 2960
	free_netdev(ndev);

	return 0;
}
2961
EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
2962

2963 2964 2965 2966 2967 2968 2969
/**
 * stmmac_suspend - suspend callback
 * @ndev: net device pointer
 * Description: this is the function to suspend the device and it is called
 * by the platform driver to stop the network queue, release the resources,
 * program the PMT register (for WoL), clean and release driver resources.
 */
2970
int stmmac_suspend(struct net_device *ndev)
2971
{
2972
	struct stmmac_priv *priv = netdev_priv(ndev);
2973
	unsigned long flags;
2974

2975
	if (!ndev || !netif_running(ndev))
2976 2977
		return 0;

2978 2979 2980
	if (priv->phydev)
		phy_stop(priv->phydev);

2981
	spin_lock_irqsave(&priv->lock, flags);
2982

2983 2984
	netif_device_detach(ndev);
	netif_stop_queue(ndev);
2985

2986 2987 2988 2989 2990
	napi_disable(&priv->napi);

	/* Stop TX/RX DMA */
	priv->hw->dma->stop_tx(priv->ioaddr);
	priv->hw->dma->stop_rx(priv->ioaddr);
2991 2992

	stmmac_clear_descriptors(priv);
2993 2994

	/* Enable Power down mode by programming the PMT regs */
2995
	if (device_may_wakeup(priv->device)) {
2996
		priv->hw->mac->pmt(priv->hw, priv->wolopts);
2997 2998
		priv->irq_wake = 1;
	} else {
2999
		stmmac_set_mac(priv->ioaddr, false);
3000
		pinctrl_pm_select_sleep_state(priv->device);
3001
		/* Disable clock in case of PWM is off */
3002
		clk_disable(priv->stmmac_clk);
3003
	}
3004
	spin_unlock_irqrestore(&priv->lock, flags);
3005 3006 3007 3008

	priv->oldlink = 0;
	priv->speed = 0;
	priv->oldduplex = -1;
3009 3010
	return 0;
}
3011
EXPORT_SYMBOL_GPL(stmmac_suspend);
3012

3013 3014 3015 3016 3017 3018
/**
 * stmmac_resume - resume callback
 * @ndev: net device pointer
 * Description: when resume this function is invoked to setup the DMA and CORE
 * in a usable state.
 */
3019
int stmmac_resume(struct net_device *ndev)
3020
{
3021
	struct stmmac_priv *priv = netdev_priv(ndev);
3022
	unsigned long flags;
3023

3024
	if (!netif_running(ndev))
3025 3026
		return 0;

3027
	spin_lock_irqsave(&priv->lock, flags);
3028

3029 3030 3031 3032
	/* Power Down bit, into the PM register, is cleared
	 * automatically as soon as a magic packet or a Wake-up frame
	 * is received. Anyway, it's better to manually clear
	 * this bit because it can generate problems while resuming
G
Giuseppe CAVALLARO 已提交
3033 3034
	 * from another devices (e.g. serial console).
	 */
3035
	if (device_may_wakeup(priv->device)) {
3036
		priv->hw->mac->pmt(priv->hw, 0);
3037
		priv->irq_wake = 0;
3038
	} else {
3039
		pinctrl_pm_select_default_state(priv->device);
3040
		/* enable the clk prevously disabled */
3041
		clk_enable(priv->stmmac_clk);
3042 3043 3044 3045
		/* reset the phy so that it's ready */
		if (priv->mii)
			stmmac_mdio_reset(priv->mii);
	}
3046

3047
	netif_device_attach(ndev);
3048

3049
	init_dma_desc_rings(ndev, GFP_ATOMIC);
3050
	stmmac_hw_setup(ndev, false);
3051
	stmmac_init_tx_coalesce(priv);
3052 3053 3054

	napi_enable(&priv->napi);

3055
	netif_start_queue(ndev);
3056

3057
	spin_unlock_irqrestore(&priv->lock, flags);
3058 3059 3060 3061

	if (priv->phydev)
		phy_start(priv->phydev);

3062 3063
	return 0;
}
3064
EXPORT_SYMBOL_GPL(stmmac_resume);
3065

3066 3067 3068 3069 3070 3071 3072 3073
#ifndef MODULE
static int __init stmmac_cmdline_opt(char *str)
{
	char *opt;

	if (!str || !*str)
		return -EINVAL;
	while ((opt = strsep(&str, ",")) != NULL) {
3074
		if (!strncmp(opt, "debug:", 6)) {
3075
			if (kstrtoint(opt + 6, 0, &debug))
3076 3077
				goto err;
		} else if (!strncmp(opt, "phyaddr:", 8)) {
3078
			if (kstrtoint(opt + 8, 0, &phyaddr))
3079 3080
				goto err;
		} else if (!strncmp(opt, "dma_txsize:", 11)) {
3081
			if (kstrtoint(opt + 11, 0, &dma_txsize))
3082 3083
				goto err;
		} else if (!strncmp(opt, "dma_rxsize:", 11)) {
3084
			if (kstrtoint(opt + 11, 0, &dma_rxsize))
3085 3086
				goto err;
		} else if (!strncmp(opt, "buf_sz:", 7)) {
3087
			if (kstrtoint(opt + 7, 0, &buf_sz))
3088 3089
				goto err;
		} else if (!strncmp(opt, "tc:", 3)) {
3090
			if (kstrtoint(opt + 3, 0, &tc))
3091 3092
				goto err;
		} else if (!strncmp(opt, "watchdog:", 9)) {
3093
			if (kstrtoint(opt + 9, 0, &watchdog))
3094 3095
				goto err;
		} else if (!strncmp(opt, "flow_ctrl:", 10)) {
3096
			if (kstrtoint(opt + 10, 0, &flow_ctrl))
3097 3098
				goto err;
		} else if (!strncmp(opt, "pause:", 6)) {
3099
			if (kstrtoint(opt + 6, 0, &pause))
3100
				goto err;
3101
		} else if (!strncmp(opt, "eee_timer:", 10)) {
3102 3103
			if (kstrtoint(opt + 10, 0, &eee_timer))
				goto err;
3104 3105 3106
		} else if (!strncmp(opt, "chain_mode:", 11)) {
			if (kstrtoint(opt + 11, 0, &chain_mode))
				goto err;
3107
		}
3108 3109
	}
	return 0;
3110 3111 3112 3113

err:
	pr_err("%s: ERROR broken module parameter conversion", __func__);
	return -EINVAL;
3114 3115 3116
}

__setup("stmmaceth=", stmmac_cmdline_opt);
G
Giuseppe CAVALLARO 已提交
3117
#endif /* MODULE */
3118 3119 3120 3121

MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
MODULE_LICENSE("GPL");