stmmac_main.c 82.8 KB
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/*******************************************************************************
  This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
  ST Ethernet IPs are built around a Synopsys IP Core.

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	Copyright(C) 2007-2011 STMicroelectronics Ltd
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  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>

  Documentation available at:
	http://www.stlinux.com
  Support available at:
	https://bugzilla.stlinux.com/
*******************************************************************************/

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#include <linux/clk.h>
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#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/if_ether.h>
#include <linux/crc32.h>
#include <linux/mii.h>
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#include <linux/if.h>
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#include <linux/if_vlan.h>
#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/prefetch.h>
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#ifdef CONFIG_STMMAC_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
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#endif /* CONFIG_STMMAC_DEBUG_FS */
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#include <linux/net_tstamp.h>
#include "stmmac_ptp.h"
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#include "stmmac.h"
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#define STMMAC_ALIGN(x)	L1_CACHE_ALIGN(x)
#define JUMBO_LEN	9000

/* Module parameters */
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#define TX_TIMEO	5000
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static int watchdog = TX_TIMEO;
module_param(watchdog, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
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static int debug = -1;
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module_param(debug, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
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static int phyaddr = -1;
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module_param(phyaddr, int, S_IRUGO);
MODULE_PARM_DESC(phyaddr, "Physical device address");

#define DMA_TX_SIZE 256
static int dma_txsize = DMA_TX_SIZE;
module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");

#define DMA_RX_SIZE 256
static int dma_rxsize = DMA_RX_SIZE;
module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");

static int flow_ctrl = FLOW_OFF;
module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");

static int pause = PAUSE_TIME;
module_param(pause, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(pause, "Flow Control Pause Time");

#define TC_DEFAULT 64
static int tc = TC_DEFAULT;
module_param(tc, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(tc, "DMA threshold control value");

#define DMA_BUFFER_SIZE	BUF_SIZE_2KiB
static int buf_sz = DMA_BUFFER_SIZE;
module_param(buf_sz, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(buf_sz, "DMA buffer size");

static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
				      NETIF_MSG_LINK | NETIF_MSG_IFUP |
				      NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);

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#define STMMAC_DEFAULT_LPI_TIMER	1000
static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
module_param(eee_timer, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
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#define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
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/* By default the driver will use the ring mode to manage tx and rx descriptors
 * but passing this value so user can force to use the chain instead of the ring
 */
static unsigned int chain_mode;
module_param(chain_mode, int, S_IRUGO);
MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");

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static irqreturn_t stmmac_interrupt(int irq, void *dev_id);

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#ifdef CONFIG_STMMAC_DEBUG_FS
static int stmmac_init_fs(struct net_device *dev);
static void stmmac_exit_fs(void);
#endif

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#define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))

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/**
 * stmmac_verify_args - verify the driver parameters.
 * Description: it verifies if some wrong parameter is passed to the driver.
 * Note that wrong parameters are replaced with the default values.
 */
static void stmmac_verify_args(void)
{
	if (unlikely(watchdog < 0))
		watchdog = TX_TIMEO;
	if (unlikely(dma_rxsize < 0))
		dma_rxsize = DMA_RX_SIZE;
	if (unlikely(dma_txsize < 0))
		dma_txsize = DMA_TX_SIZE;
	if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
		buf_sz = DMA_BUFFER_SIZE;
	if (unlikely(flow_ctrl > 1))
		flow_ctrl = FLOW_AUTO;
	else if (likely(flow_ctrl < 0))
		flow_ctrl = FLOW_OFF;
	if (unlikely((pause < 0) || (pause > 0xffff)))
		pause = PAUSE_TIME;
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	if (eee_timer < 0)
		eee_timer = STMMAC_DEFAULT_LPI_TIMER;
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}

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/**
 * stmmac_clk_csr_set - dynamically set the MDC clock
 * @priv: driver private structure
 * Description: this is to dynamically set the MDC clock according to the csr
 * clock input.
 * Note:
 *	If a specific clk_csr value is passed from the platform
 *	this means that the CSR Clock Range selection cannot be
 *	changed at run-time and it is fixed (as reported in the driver
 *	documentation). Viceversa the driver will try to set the MDC
 *	clock dynamically according to the actual clock input.
 */
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static void stmmac_clk_csr_set(struct stmmac_priv *priv)
{
	u32 clk_rate;

	clk_rate = clk_get_rate(priv->stmmac_clk);

	/* Platform provided default clk_csr would be assumed valid
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	 * for all other cases except for the below mentioned ones.
	 * For values higher than the IEEE 802.3 specified frequency
	 * we can not estimate the proper divider as it is not known
	 * the frequency of clk_csr_i. So we do not change the default
	 * divider.
	 */
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	if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
		if (clk_rate < CSR_F_35M)
			priv->clk_csr = STMMAC_CSR_20_35M;
		else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
			priv->clk_csr = STMMAC_CSR_35_60M;
		else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
			priv->clk_csr = STMMAC_CSR_60_100M;
		else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
			priv->clk_csr = STMMAC_CSR_100_150M;
		else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
			priv->clk_csr = STMMAC_CSR_150_250M;
		else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
			priv->clk_csr = STMMAC_CSR_250_300M;
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	}
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}

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static void print_pkt(unsigned char *buf, int len)
{
	int j;
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	pr_debug("len = %d byte, buf addr: 0x%p", len, buf);
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	for (j = 0; j < len; j++) {
		if ((j % 16) == 0)
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			pr_debug("\n %03x:", j);
		pr_debug(" %02x", buf[j]);
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	}
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	pr_debug("\n");
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}

/* minimum number of free TX descriptors required to wake up TX process */
#define STMMAC_TX_THRESH(x)	(x->dma_tx_size/4)

static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
{
	return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
}

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/**
 * stmmac_hw_fix_mac_speed: callback for speed selection
 * @priv: driver private structure
 * Description: on some platforms (e.g. ST), some HW system configuraton
 * registers have to be set according to the link speed negotiated.
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 */
static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
{
	struct phy_device *phydev = priv->phydev;

	if (likely(priv->plat->fix_mac_speed))
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		priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
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}

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/**
 * stmmac_enable_eee_mode: Check and enter in LPI mode
 * @priv: driver private structure
 * Description: this function is to verify and enter in LPI mode for EEE.
 */
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static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
{
	/* Check and enter in LPI mode */
	if ((priv->dirty_tx == priv->cur_tx) &&
	    (priv->tx_path_in_lpi_mode == false))
		priv->hw->mac->set_eee_mode(priv->ioaddr);
}

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/**
 * stmmac_disable_eee_mode: disable/exit from EEE
 * @priv: driver private structure
 * Description: this function is to exit and disable EEE in case of
 * LPI state is true. This is called by the xmit.
 */
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void stmmac_disable_eee_mode(struct stmmac_priv *priv)
{
	priv->hw->mac->reset_eee_mode(priv->ioaddr);
	del_timer_sync(&priv->eee_ctrl_timer);
	priv->tx_path_in_lpi_mode = false;
}

/**
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 * stmmac_eee_ctrl_timer: EEE TX SW timer.
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 * @arg : data hook
 * Description:
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 *  if there is no data transfer and if we are not in LPI state,
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 *  then MAC Transmitter can be moved to LPI state.
 */
static void stmmac_eee_ctrl_timer(unsigned long arg)
{
	struct stmmac_priv *priv = (struct stmmac_priv *)arg;

	stmmac_enable_eee_mode(priv);
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	mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
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}

/**
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 * stmmac_eee_init: init EEE
 * @priv: driver private structure
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 * Description:
 *  If the EEE support has been enabled while configuring the driver,
 *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 *  phy can also manage EEE, so enable the LPI state and start the timer
 *  to verify if the tx path can enter in LPI state.
 */
bool stmmac_eee_init(struct stmmac_priv *priv)
{
	bool ret = false;

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	/* Using PCS we cannot dial with the phy registers at this stage
	 * so we do not support extra feature like EEE.
	 */
	if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
	    (priv->pcs == STMMAC_PCS_RTBI))
		goto out;

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	/* MAC core supports the EEE feature. */
	if (priv->dma_cap.eee) {
		/* Check if the PHY supports EEE */
		if (phy_init_eee(priv->phydev, 1))
			goto out;

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		if (!priv->eee_active) {
			priv->eee_active = 1;
			init_timer(&priv->eee_ctrl_timer);
			priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
			priv->eee_ctrl_timer.data = (unsigned long)priv;
			priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
			add_timer(&priv->eee_ctrl_timer);

			priv->hw->mac->set_eee_timer(priv->ioaddr,
						     STMMAC_DEFAULT_LIT_LS,
						     priv->tx_lpi_timer);
		} else
			/* Set HW EEE according to the speed */
			priv->hw->mac->set_eee_pls(priv->ioaddr,
						   priv->phydev->link);
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		pr_info("stmmac: Energy-Efficient Ethernet initialized\n");

		ret = true;
	}
out:
	return ret;
}

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/* stmmac_get_tx_hwtstamp: get HW TX timestamps
 * @priv: driver private structure
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 * @entry : descriptor index to be used.
 * @skb : the socket buffer
 * Description :
 * This function will read timestamp from the descriptor & pass it to stack.
 * and also perform some sanity checks.
 */
static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
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				   unsigned int entry, struct sk_buff *skb)
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{
	struct skb_shared_hwtstamps shhwtstamp;
	u64 ns;
	void *desc = NULL;

	if (!priv->hwts_tx_en)
		return;

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	/* exit if skb doesn't support hw tstamp */
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	if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
		return;

	if (priv->adv_ts)
		desc = (priv->dma_etx + entry);
	else
		desc = (priv->dma_tx + entry);

	/* check tx tstamp status */
	if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
		return;

	/* get the valid tstamp */
	ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);

	memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
	shhwtstamp.hwtstamp = ns_to_ktime(ns);
	/* pass tstamp to stack */
	skb_tstamp_tx(skb, &shhwtstamp);

	return;
}

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/* stmmac_get_rx_hwtstamp: get HW RX timestamps
 * @priv: driver private structure
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 * @entry : descriptor index to be used.
 * @skb : the socket buffer
 * Description :
 * This function will read received packet's timestamp from the descriptor
 * and pass it to stack. It also perform some sanity checks.
 */
static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
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				   unsigned int entry, struct sk_buff *skb)
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{
	struct skb_shared_hwtstamps *shhwtstamp = NULL;
	u64 ns;
	void *desc = NULL;

	if (!priv->hwts_rx_en)
		return;

	if (priv->adv_ts)
		desc = (priv->dma_erx + entry);
	else
		desc = (priv->dma_rx + entry);

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	/* exit if rx tstamp is not valid */
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	if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
		return;

	/* get valid tstamp */
	ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
	shhwtstamp = skb_hwtstamps(skb);
	memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
	shhwtstamp->hwtstamp = ns_to_ktime(ns);
}

/**
 *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 *  @dev: device pointer.
 *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 *  a proprietary structure used to pass information to the driver.
 *  Description:
 *  This function configures the MAC to enable/disable both outgoing(TX)
 *  and incoming(RX) packets time stamping based on user input.
 *  Return Value:
 *  0 on success and an appropriate -ve integer on failure.
 */
static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	struct hwtstamp_config config;
	struct timespec now;
	u64 temp = 0;
	u32 ptp_v2 = 0;
	u32 tstamp_all = 0;
	u32 ptp_over_ipv4_udp = 0;
	u32 ptp_over_ipv6_udp = 0;
	u32 ptp_over_ethernet = 0;
	u32 snap_type_sel = 0;
	u32 ts_master_en = 0;
	u32 ts_event_en = 0;
	u32 value = 0;

	if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
		netdev_alert(priv->dev, "No support for HW time stamping\n");
		priv->hwts_tx_en = 0;
		priv->hwts_rx_en = 0;

		return -EOPNOTSUPP;
	}

	if (copy_from_user(&config, ifr->ifr_data,
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			   sizeof(struct hwtstamp_config)))
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		return -EFAULT;

	pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
		 __func__, config.flags, config.tx_type, config.rx_filter);

	/* reserved for future extensions */
	if (config.flags)
		return -EINVAL;

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	if (config.tx_type != HWTSTAMP_TX_OFF &&
	    config.tx_type != HWTSTAMP_TX_ON)
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		return -ERANGE;

	if (priv->adv_ts) {
		switch (config.rx_filter) {
		case HWTSTAMP_FILTER_NONE:
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			/* time stamp no incoming packet at all */
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			config.rx_filter = HWTSTAMP_FILTER_NONE;
			break;

		case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
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			/* PTP v1, UDP, any kind of event packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
			/* take time stamp for all event messages */
			snap_type_sel = PTP_TCR_SNAPTYPSEL_1;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
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			/* PTP v1, UDP, Sync packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
			/* take time stamp for SYNC messages only */
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
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			/* PTP v1, UDP, Delay_req packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
			/* take time stamp for Delay_Req messages only */
			ts_master_en = PTP_TCR_TSMSTRENA;
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
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			/* PTP v2, UDP, any kind of event packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for all event messages */
			snap_type_sel = PTP_TCR_SNAPTYPSEL_1;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
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			/* PTP v2, UDP, Sync packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for SYNC messages only */
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
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			/* PTP v2, UDP, Delay_req packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for Delay_Req messages only */
			ts_master_en = PTP_TCR_TSMSTRENA;
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_EVENT:
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			/* PTP v2/802.AS1 any layer, any kind of event packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for all event messages */
			snap_type_sel = PTP_TCR_SNAPTYPSEL_1;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			ptp_over_ethernet = PTP_TCR_TSIPENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_SYNC:
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			/* PTP v2/802.AS1, any layer, Sync packet */
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			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for SYNC messages only */
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			ptp_over_ethernet = PTP_TCR_TSIPENA;
			break;

		case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
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			/* PTP v2/802.AS1, any layer, Delay_req packet */
540 541 542 543 544 545 546 547 548 549 550 551
			config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
			ptp_v2 = PTP_TCR_TSVER2ENA;
			/* take time stamp for Delay_Req messages only */
			ts_master_en = PTP_TCR_TSMSTRENA;
			ts_event_en = PTP_TCR_TSEVNTENA;

			ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
			ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
			ptp_over_ethernet = PTP_TCR_TSIPENA;
			break;

		case HWTSTAMP_FILTER_ALL:
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552
			/* time stamp any incoming packet */
553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571
			config.rx_filter = HWTSTAMP_FILTER_ALL;
			tstamp_all = PTP_TCR_TSENALL;
			break;

		default:
			return -ERANGE;
		}
	} else {
		switch (config.rx_filter) {
		case HWTSTAMP_FILTER_NONE:
			config.rx_filter = HWTSTAMP_FILTER_NONE;
			break;
		default:
			/* PTP v1, UDP, any kind of event packet */
			config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
			break;
		}
	}
	priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
572
	priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
573 574 575 576 577

	if (!priv->hwts_tx_en && !priv->hwts_rx_en)
		priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
	else {
		value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
G
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578 579 580
			 tstamp_all | ptp_v2 | ptp_over_ethernet |
			 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
			 ts_master_en | snap_type_sel);
581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597

		priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);

		/* program Sub Second Increment reg */
		priv->hw->ptp->config_sub_second_increment(priv->ioaddr);

		/* calculate default added value:
		 * formula is :
		 * addend = (2^32)/freq_div_ratio;
		 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
		 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
		 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
		 *       achive 20ns accuracy.
		 *
		 * 2^x * y == (y << x), hence
		 * 2^32 * 50000000 ==> (50000000 << 32)
		 */
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Giuseppe CAVALLARO 已提交
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		temp = (u64) (50000000ULL << 32);
599 600 601 602 603 604 605 606 607 608 609 610 611 612
		priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
		priv->hw->ptp->config_addend(priv->ioaddr,
					     priv->default_addend);

		/* initialize system time */
		getnstimeofday(&now);
		priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
					    now.tv_nsec);
	}

	return copy_to_user(ifr->ifr_data, &config,
			    sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
}

613 614 615 616 617 618 619
/**
 * stmmac_init_ptp: init PTP
 * @priv: driver private structure
 * Description: this is to verify if the HW supports the PTPv1 or v2.
 * This is done by looking at the HW cap. register.
 * Also it registers the ptp driver.
 */
620
static int stmmac_init_ptp(struct stmmac_priv *priv)
621
{
622 623 624
	if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
		return -EOPNOTSUPP;

625 626 627 628 629 630 631 632 633
	priv->adv_ts = 0;
	if (priv->dma_cap.atime_stamp && priv->extend_desc)
		priv->adv_ts = 1;

	if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
		pr_debug("IEEE 1588-2002 Time Stamp supported\n");

	if (netif_msg_hw(priv) && priv->adv_ts)
		pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
634 635 636 637

	priv->hw->ptp = &stmmac_ptp;
	priv->hwts_tx_en = 0;
	priv->hwts_rx_en = 0;
638 639 640 641 642 643 644

	return stmmac_ptp_register(priv);
}

static void stmmac_release_ptp(struct stmmac_priv *priv)
{
	stmmac_ptp_unregister(priv);
645 646
}

647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663
/**
 * stmmac_adjust_link
 * @dev: net device structure
 * Description: it adjusts the link parameters.
 */
static void stmmac_adjust_link(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phydev;
	unsigned long flags;
	int new_state = 0;
	unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;

	if (phydev == NULL)
		return;

	spin_lock_irqsave(&priv->lock, flags);
664

665
	if (phydev->link) {
666
		u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
667 668 669 670 671 672

		/* Now we make sure that we can be in full duplex mode.
		 * If not, we operate in half-duplex mode. */
		if (phydev->duplex != priv->oldduplex) {
			new_state = 1;
			if (!(phydev->duplex))
673
				ctrl &= ~priv->hw->link.duplex;
674
			else
675
				ctrl |= priv->hw->link.duplex;
676 677 678 679
			priv->oldduplex = phydev->duplex;
		}
		/* Flow Control operation */
		if (phydev->pause)
680
			priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
681
						 fc, pause_time);
682 683 684 685 686

		if (phydev->speed != priv->speed) {
			new_state = 1;
			switch (phydev->speed) {
			case 1000:
687
				if (likely(priv->plat->has_gmac))
688
					ctrl &= ~priv->hw->link.port;
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Giuseppe CAVALLARO 已提交
689
				stmmac_hw_fix_mac_speed(priv);
690 691 692
				break;
			case 100:
			case 10:
693
				if (priv->plat->has_gmac) {
694
					ctrl |= priv->hw->link.port;
695
					if (phydev->speed == SPEED_100) {
696
						ctrl |= priv->hw->link.speed;
697
					} else {
698
						ctrl &= ~(priv->hw->link.speed);
699 700
					}
				} else {
701
					ctrl &= ~priv->hw->link.port;
702
				}
703
				stmmac_hw_fix_mac_speed(priv);
704 705 706
				break;
			default:
				if (netif_msg_link(priv))
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Giuseppe CAVALLARO 已提交
707 708
					pr_warn("%s: Speed (%d) not 10/100\n",
						dev->name, phydev->speed);
709 710 711 712 713 714
				break;
			}

			priv->speed = phydev->speed;
		}

715
		writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
716 717 718 719 720 721 722 723 724 725 726 727 728 729 730

		if (!priv->oldlink) {
			new_state = 1;
			priv->oldlink = 1;
		}
	} else if (priv->oldlink) {
		new_state = 1;
		priv->oldlink = 0;
		priv->speed = 0;
		priv->oldduplex = -1;
	}

	if (new_state && netif_msg_link(priv))
		phy_print_status(phydev);

G
Giuseppe CAVALLARO 已提交
731 732 733 734
	/* At this stage, it could be needed to setup the EEE or adjust some
	 * MAC related HW registers.
	 */
	priv->eee_enabled = stmmac_eee_init(priv);
735

736 737 738
	spin_unlock_irqrestore(&priv->lock, flags);
}

739 740 741 742 743 744 745
/**
 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
 * @priv: driver private structure
 * Description: this is to verify if the HW supports the PCS.
 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 * configured for the TBI, RTBI, or SGMII PHY interface.
 */
746 747 748 749 750
static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
{
	int interface = priv->plat->interface;

	if (priv->dma_cap.pcs) {
B
Byungho An 已提交
751 752 753 754
		if ((interface == PHY_INTERFACE_MODE_RGMII) ||
		    (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
		    (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
		    (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
755 756
			pr_debug("STMMAC: PCS RGMII support enable\n");
			priv->pcs = STMMAC_PCS_RGMII;
B
Byungho An 已提交
757
		} else if (interface == PHY_INTERFACE_MODE_SGMII) {
758 759 760 761 762 763
			pr_debug("STMMAC: PCS SGMII support enable\n");
			priv->pcs = STMMAC_PCS_SGMII;
		}
	}
}

764 765 766 767 768 769 770 771 772 773 774 775
/**
 * stmmac_init_phy - PHY initialization
 * @dev: net device structure
 * Description: it initializes the driver's PHY state, and attaches the PHY
 * to the mac driver.
 *  Return value:
 *  0 on success
 */
static int stmmac_init_phy(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	struct phy_device *phydev;
776
	char phy_id_fmt[MII_BUS_ID_SIZE + 3];
777
	char bus_id[MII_BUS_ID_SIZE];
778
	int interface = priv->plat->interface;
779
	int max_speed = priv->plat->max_speed;
780 781 782 783
	priv->oldlink = 0;
	priv->speed = 0;
	priv->oldduplex = -1;

784 785
	if (priv->plat->phy_bus_name)
		snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
G
Giuseppe CAVALLARO 已提交
786
			 priv->plat->phy_bus_name, priv->plat->bus_id);
787 788
	else
		snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
G
Giuseppe CAVALLARO 已提交
789
			 priv->plat->bus_id);
790

791
	snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
792
		 priv->plat->phy_addr);
793
	pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
794

795
	phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
796 797 798 799 800 801

	if (IS_ERR(phydev)) {
		pr_err("%s: Could not attach to PHY\n", dev->name);
		return PTR_ERR(phydev);
	}

802
	/* Stop Advertising 1000BASE Capability if interface is not GMII */
803
	if ((interface == PHY_INTERFACE_MODE_MII) ||
804 805
	    (interface == PHY_INTERFACE_MODE_RMII) ||
		(max_speed < 1000 &&  max_speed > 0))
806 807
		phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
					 SUPPORTED_1000baseT_Full);
808

809 810 811 812 813 814 815 816 817 818 819 820
	/*
	 * Broken HW is sometimes missing the pull-up resistor on the
	 * MDIO line, which results in reads to non-existent devices returning
	 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
	 * device as well.
	 * Note: phydev->phy_id is the result of reading the UID PHY registers.
	 */
	if (phydev->phy_id == 0) {
		phy_disconnect(phydev);
		return -ENODEV;
	}
	pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
821
		 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
822 823 824 825 826 827 828

	priv->phydev = phydev;

	return 0;
}

/**
829 830
 * stmmac_display_ring: display ring
 * @head: pointer to the head of the ring passed.
831
 * @size: size of the ring.
832
 * @extend_desc: to verify if extended descriptors are used.
833
 * Description: display the control/status and buffer descriptors.
834
 */
835
static void stmmac_display_ring(void *head, int size, int extend_desc)
836 837
{
	int i;
G
Giuseppe CAVALLARO 已提交
838 839
	struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
	struct dma_desc *p = (struct dma_desc *)head;
840

841
	for (i = 0; i < size; i++) {
842 843 844 845
		u64 x;
		if (extend_desc) {
			x = *(u64 *) ep;
			pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
G
Giuseppe CAVALLARO 已提交
846 847
				i, (unsigned int)virt_to_phys(ep),
				(unsigned int)x, (unsigned int)(x >> 32),
848 849 850 851 852
				ep->basic.des2, ep->basic.des3);
			ep++;
		} else {
			x = *(u64 *) p;
			pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
G
Giuseppe CAVALLARO 已提交
853 854
				i, (unsigned int)virt_to_phys(p),
				(unsigned int)x, (unsigned int)(x >> 32),
855 856 857
				p->des2, p->des3);
			p++;
		}
858 859 860 861
		pr_info("\n");
	}
}

862 863 864 865 866 867 868
static void stmmac_display_rings(struct stmmac_priv *priv)
{
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;

	if (priv->extend_desc) {
		pr_info("Extended RX descriptor ring:\n");
G
Giuseppe CAVALLARO 已提交
869
		stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
870
		pr_info("Extended TX descriptor ring:\n");
G
Giuseppe CAVALLARO 已提交
871
		stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
872 873 874 875 876 877 878 879
	} else {
		pr_info("RX descriptor ring:\n");
		stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
		pr_info("TX descriptor ring:\n");
		stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
	}
}

880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895
static int stmmac_set_bfsize(int mtu, int bufsize)
{
	int ret = bufsize;

	if (mtu >= BUF_SIZE_4KiB)
		ret = BUF_SIZE_8KiB;
	else if (mtu >= BUF_SIZE_2KiB)
		ret = BUF_SIZE_4KiB;
	else if (mtu >= DMA_BUFFER_SIZE)
		ret = BUF_SIZE_2KiB;
	else
		ret = DMA_BUFFER_SIZE;

	return ret;
}

896 897 898 899 900 901
/**
 * stmmac_clear_descriptors: clear descriptors
 * @priv: driver private structure
 * Description: this function is called to clear the tx and rx descriptors
 * in case of both basic and extended descriptors are used.
 */
902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935
static void stmmac_clear_descriptors(struct stmmac_priv *priv)
{
	int i;
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;

	/* Clear the Rx/Tx descriptors */
	for (i = 0; i < rxsize; i++)
		if (priv->extend_desc)
			priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
						     priv->use_riwt, priv->mode,
						     (i == rxsize - 1));
		else
			priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
						     priv->use_riwt, priv->mode,
						     (i == rxsize - 1));
	for (i = 0; i < txsize; i++)
		if (priv->extend_desc)
			priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
						     priv->mode,
						     (i == txsize - 1));
		else
			priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
						     priv->mode,
						     (i == txsize - 1));
}

static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
				  int i)
{
	struct sk_buff *skb;

	skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
				 GFP_KERNEL);
936
	if (!skb) {
937
		pr_err("%s: Rx init fails; skb is NULL\n", __func__);
938
		return -ENOMEM;
939 940 941 942 943 944
	}
	skb_reserve(skb, NET_IP_ALIGN);
	priv->rx_skbuff[i] = skb;
	priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
						priv->dma_buf_sz,
						DMA_FROM_DEVICE);
945 946 947 948 949
	if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
		pr_err("%s: DMA mapping error\n", __func__);
		dev_kfree_skb_any(skb);
		return -EINVAL;
	}
950 951 952 953 954 955 956 957 958 959

	p->des2 = priv->rx_skbuff_dma[i];

	if ((priv->mode == STMMAC_RING_MODE) &&
	    (priv->dma_buf_sz == BUF_SIZE_16KiB))
		priv->hw->ring->init_desc3(p);

	return 0;
}

960 961 962 963 964 965 966 967 968 969
static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
{
	if (priv->rx_skbuff[i]) {
		dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
				 priv->dma_buf_sz, DMA_FROM_DEVICE);
		dev_kfree_skb_any(priv->rx_skbuff[i]);
	}
	priv->rx_skbuff[i] = NULL;
}

970 971 972 973
/**
 * init_dma_desc_rings - init the RX/TX descriptor rings
 * @dev: net device structure
 * Description:  this function initializes the DMA RX/TX descriptors
974 975
 * and allocates the socket buffers. It suppors the chained and ring
 * modes.
976
 */
977
static int init_dma_desc_rings(struct net_device *dev)
978 979 980 981 982
{
	int i;
	struct stmmac_priv *priv = netdev_priv(dev);
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;
983
	unsigned int bfsize = 0;
984
	int ret = -ENOMEM;
985

986
	/* Set the max buffer size according to the DESC mode
G
Giuseppe CAVALLARO 已提交
987 988
	 * and the MTU. Note that RING mode allows 16KiB bsize.
	 */
989 990
	if (priv->mode == STMMAC_RING_MODE)
		bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
991

992
	if (bfsize < BUF_SIZE_16KiB)
993
		bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
994

995 996 997
	if (netif_msg_probe(priv))
		pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
			 txsize, rxsize, bfsize);
998

999
	if (netif_msg_probe(priv)) {
1000 1001
		pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
			 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1002

1003 1004 1005
		/* RX INITIALIZATION */
		pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
	}
1006
	for (i = 0; i < rxsize; i++) {
1007 1008 1009 1010 1011
		struct dma_desc *p;
		if (priv->extend_desc)
			p = &((priv->dma_erx + i)->basic);
		else
			p = priv->dma_rx + i;
1012

1013 1014 1015
		ret = stmmac_init_rx_buffers(priv, p, i);
		if (ret)
			goto err_init_rx_buffers;
1016

1017 1018 1019 1020
		if (netif_msg_probe(priv))
			pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
				 priv->rx_skbuff[i]->data,
				 (unsigned int)priv->rx_skbuff_dma[i]);
1021 1022 1023 1024 1025 1026
	}
	priv->cur_rx = 0;
	priv->dirty_rx = (unsigned int)(i - rxsize);
	priv->dma_buf_sz = bfsize;
	buf_sz = bfsize;

1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041
	/* Setup the chained descriptor addresses */
	if (priv->mode == STMMAC_CHAIN_MODE) {
		if (priv->extend_desc) {
			priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
					      rxsize, 1);
			priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
					      txsize, 1);
		} else {
			priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
					      rxsize, 0);
			priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
					      txsize, 0);
		}
	}

1042 1043
	/* TX INITIALIZATION */
	for (i = 0; i < txsize; i++) {
1044 1045 1046 1047 1048 1049
		struct dma_desc *p;
		if (priv->extend_desc)
			p = &((priv->dma_etx + i)->basic);
		else
			p = priv->dma_tx + i;
		p->des2 = 0;
1050
		priv->tx_skbuff_dma[i] = 0;
1051 1052
		priv->tx_skbuff[i] = NULL;
	}
1053

1054 1055 1056
	priv->dirty_tx = 0;
	priv->cur_tx = 0;

1057
	stmmac_clear_descriptors(priv);
1058

1059 1060
	if (netif_msg_hw(priv))
		stmmac_display_rings(priv);
1061 1062 1063 1064 1065 1066

	return 0;
err_init_rx_buffers:
	while (--i >= 0)
		stmmac_free_rx_buffers(priv, i);
	return ret;
1067 1068 1069 1070 1071 1072
}

static void dma_free_rx_skbufs(struct stmmac_priv *priv)
{
	int i;

1073 1074
	for (i = 0; i < priv->dma_rx_size; i++)
		stmmac_free_rx_buffers(priv, i);
1075 1076 1077 1078 1079 1080 1081 1082
}

static void dma_free_tx_skbufs(struct stmmac_priv *priv)
{
	int i;

	for (i = 0; i < priv->dma_tx_size; i++) {
		if (priv->tx_skbuff[i] != NULL) {
1083 1084 1085 1086 1087 1088
			struct dma_desc *p;
			if (priv->extend_desc)
				p = &((priv->dma_etx + i)->basic);
			else
				p = priv->dma_tx + i;

1089 1090 1091
			if (priv->tx_skbuff_dma[i])
				dma_unmap_single(priv->device,
						 priv->tx_skbuff_dma[i],
1092 1093
						 priv->hw->desc->get_tx_len(p),
						 DMA_TO_DEVICE);
1094 1095
			dev_kfree_skb_any(priv->tx_skbuff[i]);
			priv->tx_skbuff[i] = NULL;
1096
			priv->tx_skbuff_dma[i] = 0;
1097 1098 1099 1100
		}
	}
}

1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179
static int alloc_dma_desc_resources(struct stmmac_priv *priv)
{
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;
	int ret = -ENOMEM;

	priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
					    GFP_KERNEL);
	if (!priv->rx_skbuff_dma)
		return -ENOMEM;

	priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
					GFP_KERNEL);
	if (!priv->rx_skbuff)
		goto err_rx_skbuff;

	priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
					    GFP_KERNEL);
	if (!priv->tx_skbuff_dma)
		goto err_tx_skbuff_dma;

	priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
					GFP_KERNEL);
	if (!priv->tx_skbuff)
		goto err_tx_skbuff;

	if (priv->extend_desc) {
		priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
						   sizeof(struct
							  dma_extended_desc),
						   &priv->dma_rx_phy,
						   GFP_KERNEL);
		if (!priv->dma_erx)
			goto err_dma;

		priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
						   sizeof(struct
							  dma_extended_desc),
						   &priv->dma_tx_phy,
						   GFP_KERNEL);
		if (!priv->dma_etx) {
			dma_free_coherent(priv->device, priv->dma_rx_size *
					sizeof(struct dma_extended_desc),
					priv->dma_erx, priv->dma_rx_phy);
			goto err_dma;
		}
	} else {
		priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
						  sizeof(struct dma_desc),
						  &priv->dma_rx_phy,
						  GFP_KERNEL);
		if (!priv->dma_rx)
			goto err_dma;

		priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
						  sizeof(struct dma_desc),
						  &priv->dma_tx_phy,
						  GFP_KERNEL);
		if (!priv->dma_tx) {
			dma_free_coherent(priv->device, priv->dma_rx_size *
					sizeof(struct dma_desc),
					priv->dma_rx, priv->dma_rx_phy);
			goto err_dma;
		}
	}

	return 0;

err_dma:
	kfree(priv->tx_skbuff);
err_tx_skbuff:
	kfree(priv->tx_skbuff_dma);
err_tx_skbuff_dma:
	kfree(priv->rx_skbuff);
err_rx_skbuff:
	kfree(priv->rx_skbuff_dma);
	return ret;
}

1180 1181 1182 1183 1184 1185
static void free_dma_desc_resources(struct stmmac_priv *priv)
{
	/* Release the DMA TX/RX socket buffers */
	dma_free_rx_skbufs(priv);
	dma_free_tx_skbufs(priv);

G
Giuseppe CAVALLARO 已提交
1186
	/* Free DMA regions of consistent memory previously allocated */
1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201
	if (!priv->extend_desc) {
		dma_free_coherent(priv->device,
				  priv->dma_tx_size * sizeof(struct dma_desc),
				  priv->dma_tx, priv->dma_tx_phy);
		dma_free_coherent(priv->device,
				  priv->dma_rx_size * sizeof(struct dma_desc),
				  priv->dma_rx, priv->dma_rx_phy);
	} else {
		dma_free_coherent(priv->device, priv->dma_tx_size *
				  sizeof(struct dma_extended_desc),
				  priv->dma_etx, priv->dma_tx_phy);
		dma_free_coherent(priv->device, priv->dma_rx_size *
				  sizeof(struct dma_extended_desc),
				  priv->dma_erx, priv->dma_rx_phy);
	}
1202 1203
	kfree(priv->rx_skbuff_dma);
	kfree(priv->rx_skbuff);
1204
	kfree(priv->tx_skbuff_dma);
1205 1206 1207 1208 1209
	kfree(priv->tx_skbuff);
}

/**
 *  stmmac_dma_operation_mode - HW DMA operation mode
1210
 *  @priv: driver private structure
1211
 *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1212
 *  or Store-And-Forward capability.
1213 1214 1215
 */
static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
{
1216 1217 1218
	if (priv->plat->force_thresh_dma_mode)
		priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
	else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1219 1220 1221
		/*
		 * In case of GMAC, SF mode can be enabled
		 * to perform the TX COE in HW. This depends on:
1222 1223 1224 1225
		 * 1) TX COE if actually supported
		 * 2) There is no bugged Jumbo frame support
		 *    that needs to not insert csum in the TDES.
		 */
G
Giuseppe CAVALLARO 已提交
1226
		priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1227 1228 1229
		tc = SF_DMA_MODE;
	} else
		priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1230 1231 1232
}

/**
1233
 * stmmac_tx_clean:
1234
 * @priv: driver private structure
1235 1236
 * Description: it reclaims resources after transmission completes.
 */
1237
static void stmmac_tx_clean(struct stmmac_priv *priv)
1238 1239 1240
{
	unsigned int txsize = priv->dma_tx_size;

1241 1242
	spin_lock(&priv->tx_lock);

1243 1244
	priv->xstats.tx_clean++;

1245 1246 1247 1248
	while (priv->dirty_tx != priv->cur_tx) {
		int last;
		unsigned int entry = priv->dirty_tx % txsize;
		struct sk_buff *skb = priv->tx_skbuff[entry];
1249 1250 1251
		struct dma_desc *p;

		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
1252
			p = (struct dma_desc *)(priv->dma_etx + entry);
1253 1254
		else
			p = priv->dma_tx + entry;
1255 1256

		/* Check if the descriptor is owned by the DMA. */
1257
		if (priv->hw->desc->get_tx_owner(p))
1258 1259
			break;

1260
		/* Verify tx error by looking at the last segment. */
1261
		last = priv->hw->desc->get_tx_ls(p);
1262 1263
		if (likely(last)) {
			int tx_error =
G
Giuseppe CAVALLARO 已提交
1264 1265 1266
			    priv->hw->desc->tx_status(&priv->dev->stats,
						      &priv->xstats, p,
						      priv->ioaddr);
1267 1268 1269 1270 1271
			if (likely(tx_error == 0)) {
				priv->dev->stats.tx_packets++;
				priv->xstats.tx_pkt_n++;
			} else
				priv->dev->stats.tx_errors++;
1272 1273

			stmmac_get_tx_hwtstamp(priv, entry, skb);
1274
		}
1275 1276 1277
		if (netif_msg_tx_done(priv))
			pr_debug("%s: curr %d, dirty %d\n", __func__,
				 priv->cur_tx, priv->dirty_tx);
1278

1279 1280 1281
		if (likely(priv->tx_skbuff_dma[entry])) {
			dma_unmap_single(priv->device,
					 priv->tx_skbuff_dma[entry],
1282
					 priv->hw->desc->get_tx_len(p),
1283
					 DMA_TO_DEVICE);
1284 1285
			priv->tx_skbuff_dma[entry] = 0;
		}
1286
		priv->hw->ring->clean_desc3(priv, p);
1287 1288

		if (likely(skb != NULL)) {
E
Eric Dumazet 已提交
1289
			dev_kfree_skb(skb);
1290 1291 1292
			priv->tx_skbuff[entry] = NULL;
		}

1293
		priv->hw->desc->release_tx_desc(p, priv->mode);
1294

1295
		priv->dirty_tx++;
1296 1297 1298 1299 1300
	}
	if (unlikely(netif_queue_stopped(priv->dev) &&
		     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
		netif_tx_lock(priv->dev);
		if (netif_queue_stopped(priv->dev) &&
G
Giuseppe CAVALLARO 已提交
1301
		    stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1302 1303
			if (netif_msg_tx_done(priv))
				pr_debug("%s: restart transmit\n", __func__);
1304 1305 1306 1307
			netif_wake_queue(priv->dev);
		}
		netif_tx_unlock(priv->dev);
	}
1308 1309 1310

	if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
		stmmac_enable_eee_mode(priv);
G
Giuseppe CAVALLARO 已提交
1311
		mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1312
	}
1313
	spin_unlock(&priv->tx_lock);
1314 1315
}

1316
static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1317
{
1318
	priv->hw->dma->enable_dma_irq(priv->ioaddr);
1319 1320
}

1321
static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1322
{
1323
	priv->hw->dma->disable_dma_irq(priv->ioaddr);
1324 1325 1326
}

/**
1327 1328
 * stmmac_tx_err: irq tx error mng function
 * @priv: driver private structure
1329 1330 1331 1332 1333
 * Description: it cleans the descriptors and restarts the transmission
 * in case of errors.
 */
static void stmmac_tx_err(struct stmmac_priv *priv)
{
1334 1335
	int i;
	int txsize = priv->dma_tx_size;
1336 1337
	netif_stop_queue(priv->dev);

1338
	priv->hw->dma->stop_tx(priv->ioaddr);
1339
	dma_free_tx_skbufs(priv);
1340 1341 1342 1343 1344 1345 1346 1347 1348
	for (i = 0; i < txsize; i++)
		if (priv->extend_desc)
			priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
						     priv->mode,
						     (i == txsize - 1));
		else
			priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
						     priv->mode,
						     (i == txsize - 1));
1349 1350
	priv->dirty_tx = 0;
	priv->cur_tx = 0;
1351
	priv->hw->dma->start_tx(priv->ioaddr);
1352 1353 1354 1355 1356

	priv->dev->stats.tx_errors++;
	netif_wake_queue(priv->dev);
}

1357 1358 1359 1360 1361 1362 1363 1364
/**
 * stmmac_dma_interrupt: DMA ISR
 * @priv: driver private structure
 * Description: this is the DMA ISR. It is called by the main ISR.
 * It calls the dwmac dma routine to understand which type of interrupt
 * happened. In case of there is a Normal interrupt and either TX or RX
 * interrupt happened so the NAPI is scheduled.
 */
1365 1366 1367 1368
static void stmmac_dma_interrupt(struct stmmac_priv *priv)
{
	int status;

1369
	status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1370 1371 1372 1373 1374 1375 1376
	if (likely((status & handle_rx)) || (status & handle_tx)) {
		if (likely(napi_schedule_prep(&priv->napi))) {
			stmmac_disable_dma_irq(priv);
			__napi_schedule(&priv->napi);
		}
	}
	if (unlikely(status & tx_hard_error_bump_tc)) {
1377 1378 1379
		/* Try to bump up the dma threshold on this failure */
		if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
			tc += 64;
1380
			priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1381
			priv->xstats.threshold = tc;
1382
		}
1383 1384
	} else if (unlikely(status == tx_hard_error))
		stmmac_tx_err(priv);
1385 1386
}

1387 1388 1389 1390 1391
/**
 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
 * @priv: driver private structure
 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
 */
1392 1393 1394
static void stmmac_mmc_setup(struct stmmac_priv *priv)
{
	unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
G
Giuseppe CAVALLARO 已提交
1395
	    MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1396 1397

	dwmac_mmc_intr_all_mask(priv->ioaddr);
G
Giuseppe CAVALLARO 已提交
1398 1399 1400 1401 1402

	if (priv->dma_cap.rmon) {
		dwmac_mmc_ctrl(priv->ioaddr, mode);
		memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
	} else
1403
		pr_info(" No MAC Management Counters available\n");
1404 1405
}

1406 1407 1408 1409
static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
{
	u32 hwid = priv->hw->synopsys_uid;

G
Giuseppe CAVALLARO 已提交
1410
	/* Check Synopsys Id (not available on old chips) */
1411 1412 1413 1414
	if (likely(hwid)) {
		u32 uid = ((hwid & 0x0000ff00) >> 8);
		u32 synid = (hwid & 0x000000ff);

1415
		pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1416 1417 1418 1419 1420 1421
			uid, synid);

		return synid;
	}
	return 0;
}
1422

1423
/**
1424 1425 1426 1427 1428
 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
 * @priv: driver private structure
 * Description: select the Enhanced/Alternate or Normal descriptors.
 * In case of Enhanced/Alternate, it looks at the extended descriptors are
 * supported by the HW cap. register.
1429
 */
1430 1431 1432 1433
static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
{
	if (priv->plat->enh_desc) {
		pr_info(" Enhanced/Alternate descriptors\n");
1434 1435 1436 1437 1438 1439 1440 1441

		/* GMAC older than 3.50 has no extended descriptors */
		if (priv->synopsys_id >= DWMAC_CORE_3_50) {
			pr_info("\tEnabled extended descriptors\n");
			priv->extend_desc = 1;
		} else
			pr_warn("Extended descriptors not supported\n");

1442 1443 1444 1445 1446 1447 1448 1449
		priv->hw->desc = &enh_desc_ops;
	} else {
		pr_info(" Normal descriptors\n");
		priv->hw->desc = &ndesc_ops;
	}
}

/**
1450 1451
 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
 * @priv: driver private structure
1452 1453 1454 1455 1456
 * Description:
 *  new GMAC chip generations have a new register to indicate the
 *  presence of the optional feature/functions.
 *  This can be also used to override the value passed through the
 *  platform and necessary for old MAC10/100 and GMAC chips.
1457 1458 1459
 */
static int stmmac_get_hw_features(struct stmmac_priv *priv)
{
1460
	u32 hw_cap = 0;
1461

1462 1463
	if (priv->hw->dma->get_hw_feature) {
		hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1464

1465 1466 1467 1468
		priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
		priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
		priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
		priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
G
Giuseppe CAVALLARO 已提交
1469
		priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1470 1471 1472
		priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
		priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
		priv->dma_cap.pmt_remote_wake_up =
G
Giuseppe CAVALLARO 已提交
1473
		    (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1474
		priv->dma_cap.pmt_magic_frame =
G
Giuseppe CAVALLARO 已提交
1475
		    (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1476
		/* MMC */
1477
		priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
G
Giuseppe CAVALLARO 已提交
1478
		/* IEEE 1588-2002 */
1479
		priv->dma_cap.time_stamp =
G
Giuseppe CAVALLARO 已提交
1480 1481
		    (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
		/* IEEE 1588-2008 */
1482
		priv->dma_cap.atime_stamp =
G
Giuseppe CAVALLARO 已提交
1483
		    (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1484
		/* 802.3az - Energy-Efficient Ethernet (EEE) */
1485 1486
		priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
		priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1487
		/* TX and RX csum */
1488 1489
		priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
		priv->dma_cap.rx_coe_type1 =
G
Giuseppe CAVALLARO 已提交
1490
		    (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1491
		priv->dma_cap.rx_coe_type2 =
G
Giuseppe CAVALLARO 已提交
1492
		    (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1493
		priv->dma_cap.rxfifo_over_2048 =
G
Giuseppe CAVALLARO 已提交
1494
		    (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1495
		/* TX and RX number of channels */
1496
		priv->dma_cap.number_rx_channel =
G
Giuseppe CAVALLARO 已提交
1497
		    (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1498
		priv->dma_cap.number_tx_channel =
G
Giuseppe CAVALLARO 已提交
1499 1500 1501
		    (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
		/* Alternate (enhanced) DESC mode */
		priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1502
	}
1503 1504 1505 1506

	return hw_cap;
}

1507 1508 1509 1510 1511 1512 1513
/**
 * stmmac_check_ether_addr: check if the MAC addr is valid
 * @priv: driver private structure
 * Description:
 * it is to verify if the MAC address is valid, in case of failures it
 * generates a random MAC address
 */
1514 1515 1516 1517 1518 1519
static void stmmac_check_ether_addr(struct stmmac_priv *priv)
{
	if (!is_valid_ether_addr(priv->dev->dev_addr)) {
		priv->hw->mac->get_umac_addr((void __iomem *)
					     priv->dev->base_addr,
					     priv->dev->dev_addr, 0);
G
Giuseppe CAVALLARO 已提交
1520
		if (!is_valid_ether_addr(priv->dev->dev_addr))
1521
			eth_hw_addr_random(priv->dev);
1522
	}
G
Giuseppe CAVALLARO 已提交
1523 1524
	pr_warn("%s: device MAC address %pM\n", priv->dev->name,
		priv->dev->dev_addr);
1525 1526
}

1527 1528 1529 1530 1531 1532 1533 1534
/**
 * stmmac_init_dma_engine: DMA init.
 * @priv: driver private structure
 * Description:
 * It inits the DMA invoking the specific MAC/GMAC callback.
 * Some DMA parameters can be passed from the platform;
 * in case of these are not passed a default is kept for the MAC or GMAC.
 */
1535 1536 1537
static int stmmac_init_dma_engine(struct stmmac_priv *priv)
{
	int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1538
	int mixed_burst = 0;
1539
	int atds = 0;
1540 1541 1542 1543

	if (priv->plat->dma_cfg) {
		pbl = priv->plat->dma_cfg->pbl;
		fixed_burst = priv->plat->dma_cfg->fixed_burst;
1544
		mixed_burst = priv->plat->dma_cfg->mixed_burst;
1545 1546 1547
		burst_len = priv->plat->dma_cfg->burst_len;
	}

1548 1549 1550
	if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
		atds = 1;

1551
	return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1552
				   burst_len, priv->dma_tx_phy,
1553
				   priv->dma_rx_phy, atds);
1554 1555
}

1556
/**
1557
 * stmmac_tx_timer: mitigation sw timer for tx.
1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569
 * @data: data pointer
 * Description:
 * This is the timer handler to directly invoke the stmmac_tx_clean.
 */
static void stmmac_tx_timer(unsigned long data)
{
	struct stmmac_priv *priv = (struct stmmac_priv *)data;

	stmmac_tx_clean(priv);
}

/**
1570 1571
 * stmmac_init_tx_coalesce: init tx mitigation options.
 * @priv: driver private structure
1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587
 * Description:
 * This inits the transmit coalesce parameters: i.e. timer rate,
 * timer handler and default threshold used for enabling the
 * interrupt on completion bit.
 */
static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
{
	priv->tx_coal_frames = STMMAC_TX_FRAMES;
	priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
	init_timer(&priv->txtimer);
	priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
	priv->txtimer.data = (unsigned long)priv;
	priv->txtimer.function = stmmac_tx_timer;
	add_timer(&priv->txtimer);
}

1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667
/**
 * stmmac_hw_setup: setup mac in a usable state.
 *  @dev : pointer to the device structure.
 *  Description:
 *  This function sets up the ip in a usable state.
 *  Return value:
 *  0 on success and an appropriate (-)ve integer as defined in errno.h
 *  file on failure.
 */
static int stmmac_hw_setup(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	int ret;

	ret = init_dma_desc_rings(dev);
	if (ret < 0) {
		pr_err("%s: DMA descriptors initialization failed\n", __func__);
		return ret;
	}
	/* DMA initialization and SW reset */
	ret = stmmac_init_dma_engine(priv);
	if (ret < 0) {
		pr_err("%s: DMA engine initialization failed\n", __func__);
		return ret;
	}

	/* Copy the MAC addr into the HW  */
	priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);

	/* If required, perform hw setup of the bus. */
	if (priv->plat->bus_setup)
		priv->plat->bus_setup(priv->ioaddr);

	/* Initialize the MAC Core */
	priv->hw->mac->core_init(priv->ioaddr);

	/* Enable the MAC Rx/Tx */
	stmmac_set_mac(priv->ioaddr, true);

	/* Set the HW DMA mode and the COE */
	stmmac_dma_operation_mode(priv);

	stmmac_mmc_setup(priv);

	ret = stmmac_init_ptp(priv);
	if (ret)
		pr_warn("%s: failed PTP initialisation\n", __func__);

#ifdef CONFIG_STMMAC_DEBUG_FS
	ret = stmmac_init_fs(dev);
	if (ret < 0)
		pr_warn("%s: failed debugFS registration\n", __func__);
#endif
	/* Start the ball rolling... */
	pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
	priv->hw->dma->start_tx(priv->ioaddr);
	priv->hw->dma->start_rx(priv->ioaddr);

	/* Dump DMA/MAC registers */
	if (netif_msg_hw(priv)) {
		priv->hw->mac->dump_regs(priv->ioaddr);
		priv->hw->dma->dump_regs(priv->ioaddr);
	}
	priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;

	priv->eee_enabled = stmmac_eee_init(priv);

	stmmac_init_tx_coalesce(priv);

	if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
		priv->rx_riwt = MAX_DMA_RIWT;
		priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
	}

	if (priv->pcs && priv->hw->mac->ctrl_ane)
		priv->hw->mac->ctrl_ane(priv->ioaddr, 0);

	return 0;
}

1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681
/**
 *  stmmac_open - open entry point of the driver
 *  @dev : pointer to the device structure.
 *  Description:
 *  This function is the open entry point of the driver.
 *  Return value:
 *  0 on success and an appropriate (-)ve integer as defined in errno.h
 *  file on failure.
 */
static int stmmac_open(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	int ret;

1682
	clk_prepare_enable(priv->stmmac_clk);
1683 1684 1685

	stmmac_check_ether_addr(priv);

1686 1687
	if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
	    priv->pcs != STMMAC_PCS_RTBI) {
1688 1689 1690 1691
		ret = stmmac_init_phy(dev);
		if (ret) {
			pr_err("%s: Cannot attach to PHY (error: %d)\n",
			       __func__, ret);
1692
			goto phy_error;
1693
		}
1694
	}
1695

1696 1697 1698 1699
	/* Extra statistics */
	memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
	priv->xstats.threshold = tc;

1700 1701 1702 1703
	/* Create and initialize the TX/RX descriptors chains. */
	priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
	priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
	priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1704

1705 1706 1707 1708 1709 1710
	alloc_dma_desc_resources(priv);
	if (ret < 0) {
		pr_err("%s: DMA descriptors allocation failed\n", __func__);
		goto dma_desc_error;
	}

1711
	ret = stmmac_hw_setup(dev);
1712
	if (ret < 0) {
1713
		pr_err("%s: Hw setup failed\n", __func__);
1714
		goto init_error;
1715 1716
	}

1717 1718
	if (priv->phydev)
		phy_start(priv->phydev);
1719

1720 1721
	/* Request the IRQ lines */
	ret = request_irq(dev->irq, stmmac_interrupt,
G
Giuseppe CAVALLARO 已提交
1722
			  IRQF_SHARED, dev->name, dev);
1723 1724 1725
	if (unlikely(ret < 0)) {
		pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
		       __func__, dev->irq, ret);
1726
		goto init_error;
1727 1728
	}

1729 1730 1731 1732 1733
	/* Request the Wake IRQ in case of another line is used for WoL */
	if (priv->wol_irq != dev->irq) {
		ret = request_irq(priv->wol_irq, stmmac_interrupt,
				  IRQF_SHARED, dev->name, dev);
		if (unlikely(ret < 0)) {
G
Giuseppe CAVALLARO 已提交
1734 1735
			pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
			       __func__, priv->wol_irq, ret);
1736
			goto wolirq_error;
1737 1738 1739
		}
	}

1740 1741 1742 1743 1744 1745 1746
	/* Request the IRQ lines */
	if (priv->lpi_irq != -ENXIO) {
		ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
				  dev->name, dev);
		if (unlikely(ret < 0)) {
			pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
			       __func__, priv->lpi_irq, ret);
1747
			goto lpiirq_error;
1748 1749 1750
		}
	}

1751 1752
	napi_enable(&priv->napi);
	netif_start_queue(dev);
1753

1754
	return 0;
1755

1756
lpiirq_error:
1757 1758
	if (priv->wol_irq != dev->irq)
		free_irq(priv->wol_irq, dev);
1759
wolirq_error:
1760 1761
	free_irq(dev->irq, dev);

1762 1763
init_error:
	free_dma_desc_resources(priv);
1764
dma_desc_error:
1765 1766
	if (priv->phydev)
		phy_disconnect(priv->phydev);
1767
phy_error:
1768
	clk_disable_unprepare(priv->stmmac_clk);
1769

1770
	return ret;
1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782
}

/**
 *  stmmac_release - close entry point of the driver
 *  @dev : device pointer.
 *  Description:
 *  This is the stop entry point of the driver.
 */
static int stmmac_release(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);

1783 1784 1785
	if (priv->eee_enabled)
		del_timer_sync(&priv->eee_ctrl_timer);

1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796
	/* Stop and disconnect the PHY */
	if (priv->phydev) {
		phy_stop(priv->phydev);
		phy_disconnect(priv->phydev);
		priv->phydev = NULL;
	}

	netif_stop_queue(dev);

	napi_disable(&priv->napi);

1797 1798
	del_timer_sync(&priv->txtimer);

1799 1800
	/* Free the IRQ lines */
	free_irq(dev->irq, dev);
1801 1802
	if (priv->wol_irq != dev->irq)
		free_irq(priv->wol_irq, dev);
1803 1804
	if (priv->lpi_irq != -ENXIO)
		free_irq(priv->lpi_irq, dev);
1805 1806

	/* Stop TX/RX DMA and clear the descriptors */
1807 1808
	priv->hw->dma->stop_tx(priv->ioaddr);
	priv->hw->dma->stop_rx(priv->ioaddr);
1809 1810 1811 1812

	/* Release and free the Rx/Tx resources */
	free_dma_desc_resources(priv);

1813
	/* Disable the MAC Rx/Tx */
1814
	stmmac_set_mac(priv->ioaddr, false);
1815 1816 1817

	netif_carrier_off(dev);

1818 1819 1820
#ifdef CONFIG_STMMAC_DEBUG_FS
	stmmac_exit_fs();
#endif
1821
	clk_disable_unprepare(priv->stmmac_clk);
1822

1823 1824
	stmmac_release_ptp(priv);

1825 1826 1827 1828
	return 0;
}

/**
1829
 *  stmmac_xmit: Tx entry point of the driver
1830 1831
 *  @skb : the socket buffer
 *  @dev : device pointer
1832 1833 1834
 *  Description : this is the tx entry point of the driver.
 *  It programs the chain or the ring and supports oversized frames
 *  and SG feature.
1835 1836 1837 1838 1839 1840
 */
static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	unsigned int txsize = priv->dma_tx_size;
	unsigned int entry;
1841
	int i, csum_insertion = 0, is_jumbo = 0;
1842 1843
	int nfrags = skb_shinfo(skb)->nr_frags;
	struct dma_desc *desc, *first;
1844
	unsigned int nopaged_len = skb_headlen(skb);
1845 1846 1847 1848 1849

	if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
		if (!netif_queue_stopped(dev)) {
			netif_stop_queue(dev);
			/* This is a hard error, log it. */
G
Giuseppe CAVALLARO 已提交
1850
			pr_err("%s: Tx Ring full when queue awake\n", __func__);
1851 1852 1853 1854
		}
		return NETDEV_TX_BUSY;
	}

1855 1856
	spin_lock(&priv->tx_lock);

1857 1858 1859
	if (priv->tx_path_in_lpi_mode)
		stmmac_disable_eee_mode(priv);

1860 1861
	entry = priv->cur_tx % txsize;

1862
	csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1863

1864
	if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
1865
		desc = (struct dma_desc *)(priv->dma_etx + entry);
1866 1867 1868
	else
		desc = priv->dma_tx + entry;

1869 1870 1871
	first = desc;

	priv->tx_skbuff[entry] = skb;
1872

1873 1874 1875 1876 1877 1878 1879
	/* To program the descriptors according to the size of the frame */
	if (priv->mode == STMMAC_RING_MODE) {
		is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
							priv->plat->enh_desc);
		if (unlikely(is_jumbo))
			entry = priv->hw->ring->jumbo_frm(priv, skb,
							  csum_insertion);
1880
	} else {
1881
		is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
G
Giuseppe CAVALLARO 已提交
1882
							 priv->plat->enh_desc);
1883 1884 1885 1886 1887
		if (unlikely(is_jumbo))
			entry = priv->hw->chain->jumbo_frm(priv, skb,
							   csum_insertion);
	}
	if (likely(!is_jumbo)) {
1888
		desc->des2 = dma_map_single(priv->device, skb->data,
G
Giuseppe CAVALLARO 已提交
1889
					    nopaged_len, DMA_TO_DEVICE);
1890
		priv->tx_skbuff_dma[entry] = desc->des2;
1891
		priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1892 1893
						csum_insertion, priv->mode);
	} else
1894
		desc = first;
1895 1896

	for (i = 0; i < nfrags; i++) {
E
Eric Dumazet 已提交
1897 1898
		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
		int len = skb_frag_size(frag);
1899 1900

		entry = (++priv->cur_tx) % txsize;
1901
		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
1902
			desc = (struct dma_desc *)(priv->dma_etx + entry);
1903 1904
		else
			desc = priv->dma_tx + entry;
1905

1906 1907
		desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
					      DMA_TO_DEVICE);
1908
		priv->tx_skbuff_dma[entry] = desc->des2;
1909
		priv->tx_skbuff[entry] = NULL;
1910 1911
		priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
						priv->mode);
1912
		wmb();
1913
		priv->hw->desc->set_tx_owner(desc);
1914
		wmb();
1915 1916
	}

1917
	/* Finalize the latest segment. */
1918
	priv->hw->desc->close_tx_desc(desc);
1919

1920
	wmb();
1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932
	/* According to the coalesce parameter the IC bit for the latest
	 * segment could be reset and the timer re-started to invoke the
	 * stmmac_tx function. This approach takes care about the fragments.
	 */
	priv->tx_count_frames += nfrags + 1;
	if (priv->tx_coal_frames > priv->tx_count_frames) {
		priv->hw->desc->clear_tx_ic(desc);
		priv->xstats.tx_reset_ic_bit++;
		mod_timer(&priv->txtimer,
			  STMMAC_COAL_TIMER(priv->tx_coal_timer));
	} else
		priv->tx_count_frames = 0;
1933

1934
	/* To avoid raise condition */
1935
	priv->hw->desc->set_tx_owner(first);
1936
	wmb();
1937 1938 1939 1940

	priv->cur_tx++;

	if (netif_msg_pktdata(priv)) {
1941
		pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
G
Giuseppe CAVALLARO 已提交
1942 1943
			__func__, (priv->cur_tx % txsize),
			(priv->dirty_tx % txsize), entry, first, nfrags);
1944

1945 1946 1947 1948 1949
		if (priv->extend_desc)
			stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
		else
			stmmac_display_ring((void *)priv->dma_tx, txsize, 0);

1950
		pr_debug(">>> frame to be transmitted: ");
1951 1952 1953
		print_pkt(skb->data, skb->len);
	}
	if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1954 1955
		if (netif_msg_hw(priv))
			pr_debug("%s: stop transmitted packets\n", __func__);
1956 1957 1958 1959 1960
		netif_stop_queue(dev);
	}

	dev->stats.tx_bytes += skb->len;

1961 1962 1963 1964 1965 1966 1967 1968 1969
	if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
		     priv->hwts_tx_en)) {
		/* declare that device is doing timestamping */
		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
		priv->hw->desc->enable_tx_timestamp(first);
	}

	if (!priv->hwts_tx_en)
		skb_tx_timestamp(skb);
1970

1971 1972
	priv->hw->dma->enable_dma_transmission(priv->ioaddr);

1973 1974
	spin_unlock(&priv->tx_lock);

1975 1976 1977
	return NETDEV_TX_OK;
}

1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994
static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
{
	struct ethhdr *ehdr;
	u16 vlanid;

	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
	    NETIF_F_HW_VLAN_CTAG_RX &&
	    !__vlan_get_tag(skb, &vlanid)) {
		/* pop the vlan tag */
		ehdr = (struct ethhdr *)skb->data;
		memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
		skb_pull(skb, VLAN_HLEN);
		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
	}
}


1995 1996 1997 1998 1999 2000
/**
 * stmmac_rx_refill: refill used skb preallocated buffers
 * @priv: driver private structure
 * Description : this is to reallocate the skb for the reception process
 * that is based on zero-copy.
 */
2001 2002 2003 2004 2005 2006 2007
static inline void stmmac_rx_refill(struct stmmac_priv *priv)
{
	unsigned int rxsize = priv->dma_rx_size;
	int bfsize = priv->dma_buf_sz;

	for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
		unsigned int entry = priv->dirty_rx % rxsize;
2008 2009 2010
		struct dma_desc *p;

		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
2011
			p = (struct dma_desc *)(priv->dma_erx + entry);
2012 2013 2014
		else
			p = priv->dma_rx + entry;

2015 2016 2017
		if (likely(priv->rx_skbuff[entry] == NULL)) {
			struct sk_buff *skb;

E
Eric Dumazet 已提交
2018
			skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2019 2020 2021 2022 2023 2024 2025 2026 2027

			if (unlikely(skb == NULL))
				break;

			priv->rx_skbuff[entry] = skb;
			priv->rx_skbuff_dma[entry] =
			    dma_map_single(priv->device, skb->data, bfsize,
					   DMA_FROM_DEVICE);

2028
			p->des2 = priv->rx_skbuff_dma[entry];
2029

2030
			priv->hw->ring->refill_desc3(priv, p);
2031

2032 2033
			if (netif_msg_rx_status(priv))
				pr_debug("\trefill entry #%d\n", entry);
2034
		}
2035
		wmb();
2036
		priv->hw->desc->set_rx_owner(p);
2037
		wmb();
2038 2039 2040
	}
}

2041 2042 2043 2044 2045 2046 2047
/**
 * stmmac_rx_refill: refill used skb preallocated buffers
 * @priv: driver private structure
 * @limit: napi bugget.
 * Description :  this the function called by the napi poll method.
 * It gets all the frames inside the ring.
 */
2048 2049 2050 2051 2052 2053
static int stmmac_rx(struct stmmac_priv *priv, int limit)
{
	unsigned int rxsize = priv->dma_rx_size;
	unsigned int entry = priv->cur_rx % rxsize;
	unsigned int next_entry;
	unsigned int count = 0;
G
Giuseppe CAVALLARO 已提交
2054
	int coe = priv->plat->rx_coe;
2055

2056 2057
	if (netif_msg_rx_status(priv)) {
		pr_debug("%s: descriptor ring:\n", __func__);
2058
		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
2059
			stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2060 2061
		else
			stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2062
	}
2063
	while (count < limit) {
2064
		int status;
2065
		struct dma_desc *p;
2066

2067
		if (priv->extend_desc)
G
Giuseppe CAVALLARO 已提交
2068
			p = (struct dma_desc *)(priv->dma_erx + entry);
2069
		else
G
Giuseppe CAVALLARO 已提交
2070
			p = priv->dma_rx + entry;
2071 2072

		if (priv->hw->desc->get_rx_owner(p))
2073 2074 2075 2076 2077
			break;

		count++;

		next_entry = (++priv->cur_rx) % rxsize;
2078
		if (priv->extend_desc)
2079
			prefetch(priv->dma_erx + next_entry);
2080
		else
2081
			prefetch(priv->dma_rx + next_entry);
2082 2083

		/* read the status of the incoming frame */
2084 2085 2086 2087 2088 2089 2090
		status = priv->hw->desc->rx_status(&priv->dev->stats,
						   &priv->xstats, p);
		if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
			priv->hw->desc->rx_extended_status(&priv->dev->stats,
							   &priv->xstats,
							   priv->dma_erx +
							   entry);
2091
		if (unlikely(status == discard_frame)) {
2092
			priv->dev->stats.rx_errors++;
2093 2094 2095 2096 2097 2098 2099 2100
			if (priv->hwts_rx_en && !priv->extend_desc) {
				/* DESC2 & DESC3 will be overwitten by device
				 * with timestamp value, hence reinitialize
				 * them in stmmac_rx_refill() function so that
				 * device can reuse it.
				 */
				priv->rx_skbuff[entry] = NULL;
				dma_unmap_single(priv->device,
G
Giuseppe CAVALLARO 已提交
2101 2102 2103
						 priv->rx_skbuff_dma[entry],
						 priv->dma_buf_sz,
						 DMA_FROM_DEVICE);
2104 2105
			}
		} else {
2106
			struct sk_buff *skb;
2107
			int frame_len;
2108

G
Giuseppe CAVALLARO 已提交
2109 2110
			frame_len = priv->hw->desc->get_rx_frame_len(p, coe);

2111
			/* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
G
Giuseppe CAVALLARO 已提交
2112 2113
			 * Type frames (LLC/LLC-SNAP)
			 */
2114 2115
			if (unlikely(status != llc_snap))
				frame_len -= ETH_FCS_LEN;
2116

2117
			if (netif_msg_rx_status(priv)) {
2118
				pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
G
Giuseppe CAVALLARO 已提交
2119
					 p, entry, p->des2);
2120 2121 2122 2123
				if (frame_len > ETH_FRAME_LEN)
					pr_debug("\tframe size %d, COE: %d\n",
						 frame_len, status);
			}
2124 2125 2126
			skb = priv->rx_skbuff[entry];
			if (unlikely(!skb)) {
				pr_err("%s: Inconsistent Rx descriptor chain\n",
G
Giuseppe CAVALLARO 已提交
2127
				       priv->dev->name);
2128 2129 2130 2131 2132 2133
				priv->dev->stats.rx_dropped++;
				break;
			}
			prefetch(skb->data - NET_IP_ALIGN);
			priv->rx_skbuff[entry] = NULL;

2134 2135
			stmmac_get_rx_hwtstamp(priv, entry, skb);

2136 2137 2138 2139
			skb_put(skb, frame_len);
			dma_unmap_single(priv->device,
					 priv->rx_skbuff_dma[entry],
					 priv->dma_buf_sz, DMA_FROM_DEVICE);
2140

2141
			if (netif_msg_pktdata(priv)) {
2142
				pr_debug("frame received (%dbytes)", frame_len);
2143 2144
				print_pkt(skb->data, frame_len);
			}
2145

2146 2147
			stmmac_rx_vlan(priv->dev, skb);

2148 2149
			skb->protocol = eth_type_trans(skb, priv->dev);

G
Giuseppe CAVALLARO 已提交
2150
			if (unlikely(!coe))
2151
				skb_checksum_none_assert(skb);
2152
			else
2153
				skb->ip_summed = CHECKSUM_UNNECESSARY;
2154 2155

			napi_gro_receive(&priv->napi, skb);
2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175

			priv->dev->stats.rx_packets++;
			priv->dev->stats.rx_bytes += frame_len;
		}
		entry = next_entry;
	}

	stmmac_rx_refill(priv);

	priv->xstats.rx_pkt_n += count;

	return count;
}

/**
 *  stmmac_poll - stmmac poll method (NAPI)
 *  @napi : pointer to the napi structure.
 *  @budget : maximum number of packets that the current CPU can receive from
 *	      all interfaces.
 *  Description :
2176
 *  To look at the incoming frames and clear the tx resources.
2177 2178 2179 2180 2181 2182
 */
static int stmmac_poll(struct napi_struct *napi, int budget)
{
	struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
	int work_done = 0;

2183 2184
	priv->xstats.napi_poll++;
	stmmac_tx_clean(priv);
2185

2186
	work_done = stmmac_rx(priv, budget);
2187 2188
	if (work_done < budget) {
		napi_complete(napi);
2189
		stmmac_enable_dma_irq(priv);
2190 2191 2192 2193 2194 2195 2196 2197
	}
	return work_done;
}

/**
 *  stmmac_tx_timeout
 *  @dev : Pointer to net device structure
 *  Description: this function is called when a packet transmission fails to
2198
 *   complete within a reasonable time. The driver will mark the error in the
2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217
 *   netdev structure and arrange for the device to be reset to a sane state
 *   in order to transmit a new packet.
 */
static void stmmac_tx_timeout(struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);

	/* Clear Tx resources and restart transmitting again */
	stmmac_tx_err(priv);
}

/* Configuration changes (passed on by ifconfig) */
static int stmmac_config(struct net_device *dev, struct ifmap *map)
{
	if (dev->flags & IFF_UP)	/* can't act on a running interface */
		return -EBUSY;

	/* Don't allow changing the I/O address */
	if (map->base_addr != dev->base_addr) {
G
Giuseppe CAVALLARO 已提交
2218
		pr_warn("%s: can't change I/O address\n", dev->name);
2219 2220 2221 2222 2223
		return -EOPNOTSUPP;
	}

	/* Don't allow changing the IRQ */
	if (map->irq != dev->irq) {
G
Giuseppe CAVALLARO 已提交
2224
		pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
2225 2226 2227 2228 2229 2230 2231
		return -EOPNOTSUPP;
	}

	return 0;
}

/**
2232
 *  stmmac_set_rx_mode - entry point for multicast addressing
2233 2234 2235 2236 2237 2238 2239
 *  @dev : pointer to the device structure
 *  Description:
 *  This function is a driver entry point which gets called by the kernel
 *  whenever multicast addresses must be enabled/disabled.
 *  Return value:
 *  void.
 */
2240
static void stmmac_set_rx_mode(struct net_device *dev)
2241 2242 2243 2244
{
	struct stmmac_priv *priv = netdev_priv(dev);

	spin_lock(&priv->lock);
2245
	priv->hw->mac->set_filter(dev, priv->synopsys_id);
2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269
	spin_unlock(&priv->lock);
}

/**
 *  stmmac_change_mtu - entry point to change MTU size for the device.
 *  @dev : device pointer.
 *  @new_mtu : the new MTU size for the device.
 *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
 *  to drive packet transmission. Ethernet has an MTU of 1500 octets
 *  (ETH_DATA_LEN). This value can be changed with ifconfig.
 *  Return value:
 *  0 on success and an appropriate (-)ve integer as defined in errno.h
 *  file on failure.
 */
static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	int max_mtu;

	if (netif_running(dev)) {
		pr_err("%s: must be stopped to change its MTU\n", dev->name);
		return -EBUSY;
	}

2270
	if (priv->plat->enh_desc)
2271 2272
		max_mtu = JUMBO_LEN;
	else
2273
		max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2274 2275 2276 2277 2278 2279

	if ((new_mtu < 46) || (new_mtu > max_mtu)) {
		pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
		return -EINVAL;
	}

2280 2281 2282 2283 2284 2285
	dev->mtu = new_mtu;
	netdev_update_features(dev);

	return 0;
}

2286
static netdev_features_t stmmac_fix_features(struct net_device *dev,
G
Giuseppe CAVALLARO 已提交
2287
					     netdev_features_t features)
2288 2289 2290
{
	struct stmmac_priv *priv = netdev_priv(dev);

2291
	if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2292
		features &= ~NETIF_F_RXCSUM;
2293 2294
	else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
		features &= ~NETIF_F_IPV6_CSUM;
2295 2296 2297
	if (!priv->plat->tx_coe)
		features &= ~NETIF_F_ALL_CSUM;

2298 2299 2300
	/* Some GMAC devices have a bugged Jumbo frame support that
	 * needs to have the Tx COE disabled for oversized frames
	 * (due to limited buffer sizes). In this case we disable
G
Giuseppe CAVALLARO 已提交
2301 2302
	 * the TX csum insertionin the TDES and not use SF.
	 */
2303 2304
	if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
		features &= ~NETIF_F_ALL_CSUM;
2305

2306
	return features;
2307 2308
}

2309 2310 2311 2312 2313 2314 2315 2316
/**
 *  stmmac_interrupt - main ISR
 *  @irq: interrupt number.
 *  @dev_id: to pass the net device pointer.
 *  Description: this is the main driver interrupt service routine.
 *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
 *  interrupts.
 */
2317 2318 2319 2320 2321 2322 2323 2324 2325 2326
static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
{
	struct net_device *dev = (struct net_device *)dev_id;
	struct stmmac_priv *priv = netdev_priv(dev);

	if (unlikely(!dev)) {
		pr_err("%s: invalid dev pointer\n", __func__);
		return IRQ_NONE;
	}

2327 2328 2329
	/* To handle GMAC own interrupts */
	if (priv->plat->has_gmac) {
		int status = priv->hw->mac->host_irq_status((void __iomem *)
2330 2331
							    dev->base_addr,
							    &priv->xstats);
2332 2333
		if (unlikely(status)) {
			/* For LPI we need to save the tx status */
2334
			if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2335
				priv->tx_path_in_lpi_mode = true;
2336
			if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2337 2338 2339
				priv->tx_path_in_lpi_mode = false;
		}
	}
2340

2341
	/* To handle DMA interrupts */
2342
	stmmac_dma_interrupt(priv);
2343 2344 2345 2346 2347 2348

	return IRQ_HANDLED;
}

#ifdef CONFIG_NET_POLL_CONTROLLER
/* Polling receive - used by NETCONSOLE and other diagnostic tools
G
Giuseppe CAVALLARO 已提交
2349 2350
 * to allow network I/O with interrupts disabled.
 */
2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365
static void stmmac_poll_controller(struct net_device *dev)
{
	disable_irq(dev->irq);
	stmmac_interrupt(dev->irq, dev);
	enable_irq(dev->irq);
}
#endif

/**
 *  stmmac_ioctl - Entry point for the Ioctl
 *  @dev: Device pointer.
 *  @rq: An IOCTL specefic structure, that can contain a pointer to
 *  a proprietary structure used to pass information to the driver.
 *  @cmd: IOCTL command
 *  Description:
2366
 *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2367 2368 2369 2370
 */
static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
	struct stmmac_priv *priv = netdev_priv(dev);
2371
	int ret = -EOPNOTSUPP;
2372 2373 2374 2375

	if (!netif_running(dev))
		return -EINVAL;

2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389
	switch (cmd) {
	case SIOCGMIIPHY:
	case SIOCGMIIREG:
	case SIOCSMIIREG:
		if (!priv->phydev)
			return -EINVAL;
		ret = phy_mii_ioctl(priv->phydev, rq, cmd);
		break;
	case SIOCSHWTSTAMP:
		ret = stmmac_hwtstamp_ioctl(dev, rq);
		break;
	default:
		break;
	}
2390

2391 2392 2393
	return ret;
}

2394 2395 2396
#ifdef CONFIG_STMMAC_DEBUG_FS
static struct dentry *stmmac_fs_dir;
static struct dentry *stmmac_rings_status;
2397
static struct dentry *stmmac_dma_cap;
2398

2399
static void sysfs_display_ring(void *head, int size, int extend_desc,
G
Giuseppe CAVALLARO 已提交
2400
			       struct seq_file *seq)
2401 2402
{
	int i;
G
Giuseppe CAVALLARO 已提交
2403 2404
	struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
	struct dma_desc *p = (struct dma_desc *)head;
2405

2406 2407 2408 2409 2410
	for (i = 0; i < size; i++) {
		u64 x;
		if (extend_desc) {
			x = *(u64 *) ep;
			seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
G
Giuseppe CAVALLARO 已提交
2411 2412
				   i, (unsigned int)virt_to_phys(ep),
				   (unsigned int)x, (unsigned int)(x >> 32),
2413 2414 2415 2416 2417
				   ep->basic.des2, ep->basic.des3);
			ep++;
		} else {
			x = *(u64 *) p;
			seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
G
Giuseppe CAVALLARO 已提交
2418 2419
				   i, (unsigned int)virt_to_phys(ep),
				   (unsigned int)x, (unsigned int)(x >> 32),
2420 2421 2422
				   p->des2, p->des3);
			p++;
		}
2423 2424
		seq_printf(seq, "\n");
	}
2425
}
2426

2427 2428 2429 2430 2431 2432
static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
{
	struct net_device *dev = seq->private;
	struct stmmac_priv *priv = netdev_priv(dev);
	unsigned int txsize = priv->dma_tx_size;
	unsigned int rxsize = priv->dma_rx_size;
2433

2434 2435
	if (priv->extend_desc) {
		seq_printf(seq, "Extended RX descriptor ring:\n");
G
Giuseppe CAVALLARO 已提交
2436
		sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2437
		seq_printf(seq, "Extended TX descriptor ring:\n");
G
Giuseppe CAVALLARO 已提交
2438
		sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2439 2440 2441 2442 2443
	} else {
		seq_printf(seq, "RX descriptor ring:\n");
		sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
		seq_printf(seq, "TX descriptor ring:\n");
		sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458
	}

	return 0;
}

static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
{
	return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
}

static const struct file_operations stmmac_rings_status_fops = {
	.owner = THIS_MODULE,
	.open = stmmac_sysfs_ring_open,
	.read = seq_read,
	.llseek = seq_lseek,
2459
	.release = single_release,
2460 2461
};

2462 2463 2464 2465 2466
static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
{
	struct net_device *dev = seq->private;
	struct stmmac_priv *priv = netdev_priv(dev);

2467
	if (!priv->hw_cap_support) {
2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530
		seq_printf(seq, "DMA HW features not supported\n");
		return 0;
	}

	seq_printf(seq, "==============================\n");
	seq_printf(seq, "\tDMA HW features\n");
	seq_printf(seq, "==============================\n");

	seq_printf(seq, "\t10/100 Mbps %s\n",
		   (priv->dma_cap.mbps_10_100) ? "Y" : "N");
	seq_printf(seq, "\t1000 Mbps %s\n",
		   (priv->dma_cap.mbps_1000) ? "Y" : "N");
	seq_printf(seq, "\tHalf duple %s\n",
		   (priv->dma_cap.half_duplex) ? "Y" : "N");
	seq_printf(seq, "\tHash Filter: %s\n",
		   (priv->dma_cap.hash_filter) ? "Y" : "N");
	seq_printf(seq, "\tMultiple MAC address registers: %s\n",
		   (priv->dma_cap.multi_addr) ? "Y" : "N");
	seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
		   (priv->dma_cap.pcs) ? "Y" : "N");
	seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
		   (priv->dma_cap.sma_mdio) ? "Y" : "N");
	seq_printf(seq, "\tPMT Remote wake up: %s\n",
		   (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
	seq_printf(seq, "\tPMT Magic Frame: %s\n",
		   (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
	seq_printf(seq, "\tRMON module: %s\n",
		   (priv->dma_cap.rmon) ? "Y" : "N");
	seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
		   (priv->dma_cap.time_stamp) ? "Y" : "N");
	seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
		   (priv->dma_cap.atime_stamp) ? "Y" : "N");
	seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
		   (priv->dma_cap.eee) ? "Y" : "N");
	seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
	seq_printf(seq, "\tChecksum Offload in TX: %s\n",
		   (priv->dma_cap.tx_coe) ? "Y" : "N");
	seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
		   (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
	seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
		   (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
	seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
		   (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
	seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
		   priv->dma_cap.number_rx_channel);
	seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
		   priv->dma_cap.number_tx_channel);
	seq_printf(seq, "\tEnhanced descriptors: %s\n",
		   (priv->dma_cap.enh_desc) ? "Y" : "N");

	return 0;
}

static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
{
	return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
}

static const struct file_operations stmmac_dma_cap_fops = {
	.owner = THIS_MODULE,
	.open = stmmac_sysfs_dma_cap_open,
	.read = seq_read,
	.llseek = seq_lseek,
2531
	.release = single_release,
2532 2533
};

2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547
static int stmmac_init_fs(struct net_device *dev)
{
	/* Create debugfs entries */
	stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);

	if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
		pr_err("ERROR %s, debugfs create directory failed\n",
		       STMMAC_RESOURCE_NAME);

		return -ENOMEM;
	}

	/* Entry to report DMA RX/TX rings */
	stmmac_rings_status = debugfs_create_file("descriptors_status",
G
Giuseppe CAVALLARO 已提交
2548 2549
						  S_IRUGO, stmmac_fs_dir, dev,
						  &stmmac_rings_status_fops);
2550 2551 2552 2553 2554 2555 2556 2557

	if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
		pr_info("ERROR creating stmmac ring debugfs file\n");
		debugfs_remove(stmmac_fs_dir);

		return -ENOMEM;
	}

2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569
	/* Entry to report the DMA HW features */
	stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
					     dev, &stmmac_dma_cap_fops);

	if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
		pr_info("ERROR creating stmmac MMC debugfs file\n");
		debugfs_remove(stmmac_rings_status);
		debugfs_remove(stmmac_fs_dir);

		return -ENOMEM;
	}

2570 2571 2572 2573 2574 2575
	return 0;
}

static void stmmac_exit_fs(void)
{
	debugfs_remove(stmmac_rings_status);
2576
	debugfs_remove(stmmac_dma_cap);
2577 2578 2579 2580
	debugfs_remove(stmmac_fs_dir);
}
#endif /* CONFIG_STMMAC_DEBUG_FS */

2581 2582 2583 2584 2585
static const struct net_device_ops stmmac_netdev_ops = {
	.ndo_open = stmmac_open,
	.ndo_start_xmit = stmmac_xmit,
	.ndo_stop = stmmac_release,
	.ndo_change_mtu = stmmac_change_mtu,
2586
	.ndo_fix_features = stmmac_fix_features,
2587
	.ndo_set_rx_mode = stmmac_set_rx_mode,
2588 2589 2590 2591 2592 2593 2594 2595 2596
	.ndo_tx_timeout = stmmac_tx_timeout,
	.ndo_do_ioctl = stmmac_ioctl,
	.ndo_set_config = stmmac_config,
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller = stmmac_poll_controller,
#endif
	.ndo_set_mac_address = eth_mac_addr,
};

2597 2598
/**
 *  stmmac_hw_init - Init the MAC device
2599
 *  @priv: driver private structure
2600 2601 2602 2603 2604 2605 2606 2607
 *  Description: this function detects which MAC device
 *  (GMAC/MAC10-100) has to attached, checks the HW capability
 *  (if supported) and sets the driver's features (for example
 *  to use the ring or chaine mode or support the normal/enh
 *  descriptor structure).
 */
static int stmmac_hw_init(struct stmmac_priv *priv)
{
2608
	int ret;
2609 2610 2611
	struct mac_device_info *mac;

	/* Identify the MAC HW device */
2612 2613
	if (priv->plat->has_gmac) {
		priv->dev->priv_flags |= IFF_UNICAST_FLT;
2614
		mac = dwmac1000_setup(priv->ioaddr);
2615
	} else {
2616
		mac = dwmac100_setup(priv->ioaddr);
2617
	}
2618 2619 2620 2621 2622 2623
	if (!mac)
		return -ENOMEM;

	priv->hw = mac;

	/* Get and dump the chip ID */
2624
	priv->synopsys_id = stmmac_get_synopsys_id(priv);
2625

2626
	/* To use the chained or ring mode */
G
Giuseppe CAVALLARO 已提交
2627
	if (chain_mode) {
2628 2629 2630 2631 2632 2633 2634 2635 2636
		priv->hw->chain = &chain_mode_ops;
		pr_info(" Chain mode enabled\n");
		priv->mode = STMMAC_CHAIN_MODE;
	} else {
		priv->hw->ring = &ring_mode_ops;
		pr_info(" Ring mode enabled\n");
		priv->mode = STMMAC_RING_MODE;
	}

2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648
	/* Get the HW capability (new GMAC newer than 3.50a) */
	priv->hw_cap_support = stmmac_get_hw_features(priv);
	if (priv->hw_cap_support) {
		pr_info(" DMA HW capability register supported");

		/* We can override some gmac/dma configuration fields: e.g.
		 * enh_desc, tx_coe (e.g. that are passed through the
		 * platform) with the values from the HW capability
		 * register (if supported).
		 */
		priv->plat->enh_desc = priv->dma_cap.enh_desc;
		priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2649 2650 2651 2652 2653 2654 2655 2656

		priv->plat->tx_coe = priv->dma_cap.tx_coe;

		if (priv->dma_cap.rx_coe_type2)
			priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
		else if (priv->dma_cap.rx_coe_type1)
			priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;

2657 2658 2659
	} else
		pr_info(" No HW DMA feature register supported");

2660 2661 2662
	/* To use alternate (extended) or normal descriptor structures */
	stmmac_selec_desc_mode(priv);

2663 2664
	ret = priv->hw->mac->rx_ipc(priv->ioaddr);
	if (!ret) {
G
Giuseppe CAVALLARO 已提交
2665
		pr_warn(" RX IPC Checksum Offload not configured.\n");
2666 2667 2668 2669 2670 2671
		priv->plat->rx_coe = STMMAC_RX_COE_NONE;
	}

	if (priv->plat->rx_coe)
		pr_info(" RX Checksum Offload Engine supported (type %d)\n",
			priv->plat->rx_coe);
2672 2673 2674 2675 2676 2677 2678 2679
	if (priv->plat->tx_coe)
		pr_info(" TX Checksum insertion supported\n");

	if (priv->plat->pmt) {
		pr_info(" Wake-Up On Lan supported\n");
		device_set_wakeup_capable(priv->device, 1);
	}

2680
	return 0;
2681 2682
}

2683
/**
2684 2685
 * stmmac_dvr_probe
 * @device: device pointer
2686 2687
 * @plat_dat: platform data pointer
 * @addr: iobase memory address
2688 2689
 * Description: this is the main probe function used to
 * call the alloc_etherdev, allocate the priv structure.
2690
 */
2691
struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2692 2693
				     struct plat_stmmacenet_data *plat_dat,
				     void __iomem *addr)
2694 2695
{
	int ret = 0;
2696 2697
	struct net_device *ndev = NULL;
	struct stmmac_priv *priv;
2698

2699
	ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2700
	if (!ndev)
2701 2702 2703 2704 2705 2706 2707
		return NULL;

	SET_NETDEV_DEV(ndev, device);

	priv = netdev_priv(ndev);
	priv->device = device;
	priv->dev = ndev;
2708

2709
	ether_setup(ndev);
2710

2711
	stmmac_set_ethtool_ops(ndev);
2712 2713 2714 2715 2716 2717 2718
	priv->pause = pause;
	priv->plat = plat_dat;
	priv->ioaddr = addr;
	priv->dev->base_addr = (unsigned long)addr;

	/* Verify driver arguments */
	stmmac_verify_args();
2719

2720
	/* Override with kernel parameters if supplied XXX CRS XXX
G
Giuseppe CAVALLARO 已提交
2721 2722
	 * this needs to have multiple instances
	 */
2723 2724 2725 2726
	if ((phyaddr >= 0) && (phyaddr <= 31))
		priv->plat->phy_addr = phyaddr;

	/* Init MAC and get the capabilities */
2727 2728 2729
	ret = stmmac_hw_init(priv);
	if (ret)
		goto error_free_netdev;
2730 2731

	ndev->netdev_ops = &stmmac_netdev_ops;
2732

2733 2734
	ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
			    NETIF_F_RXCSUM;
2735 2736
	ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
	ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2737 2738
#ifdef STMMAC_VLAN_TAG_USED
	/* Both mac100 and gmac support receive VLAN tag detection */
2739
	ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2740 2741 2742 2743 2744 2745
#endif
	priv->msg_enable = netif_msg_init(debug, default_msg_level);

	if (flow_ctrl)
		priv->flow_ctrl = FLOW_AUTO;	/* RX/TX pause on */

2746 2747 2748 2749 2750 2751 2752 2753 2754 2755
	/* Rx Watchdog is available in the COREs newer than the 3.40.
	 * In some case, for example on bugged HW this feature
	 * has to be disable and this can be done by passing the
	 * riwt_off field from the platform.
	 */
	if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
		priv->use_riwt = 1;
		pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
	}

2756
	netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2757

2758
	spin_lock_init(&priv->lock);
2759
	spin_lock_init(&priv->tx_lock);
2760

2761
	ret = register_netdev(ndev);
2762
	if (ret) {
2763
		pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2764
		goto error_netdev_register;
2765 2766
	}

2767
	priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2768
	if (IS_ERR(priv->stmmac_clk)) {
G
Giuseppe CAVALLARO 已提交
2769
		pr_warn("%s: warning: cannot get CSR clock\n", __func__);
2770 2771
		goto error_clk_get;
	}
2772

2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783
	/* If a specific clk_csr value is passed from the platform
	 * this means that the CSR Clock Range selection cannot be
	 * changed at run-time and it is fixed. Viceversa the driver'll try to
	 * set the MDC clock dynamically according to the csr actual
	 * clock input.
	 */
	if (!priv->plat->clk_csr)
		stmmac_clk_csr_set(priv);
	else
		priv->clk_csr = priv->plat->clk_csr;

2784 2785
	stmmac_check_pcs_mode(priv);

2786 2787
	if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
	    priv->pcs != STMMAC_PCS_RTBI) {
2788 2789 2790 2791 2792 2793 2794
		/* MDIO bus Registration */
		ret = stmmac_mdio_register(ndev);
		if (ret < 0) {
			pr_debug("%s: MDIO bus (id: %d) registration failed",
				 __func__, priv->plat->bus_id);
			goto error_mdio_register;
		}
2795 2796
	}

2797
	return priv;
2798

2799 2800 2801
error_mdio_register:
	clk_put(priv->stmmac_clk);
error_clk_get:
2802
	unregister_netdev(ndev);
2803 2804
error_netdev_register:
	netif_napi_del(&priv->napi);
2805
error_free_netdev:
2806
	free_netdev(ndev);
2807

2808
	return NULL;
2809 2810 2811 2812
}

/**
 * stmmac_dvr_remove
2813
 * @ndev: net device pointer
2814
 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2815
 * changes the link status, releases the DMA descriptor rings.
2816
 */
2817
int stmmac_dvr_remove(struct net_device *ndev)
2818
{
2819
	struct stmmac_priv *priv = netdev_priv(ndev);
2820 2821 2822

	pr_info("%s:\n\tremoving driver", __func__);

2823 2824
	priv->hw->dma->stop_rx(priv->ioaddr);
	priv->hw->dma->stop_tx(priv->ioaddr);
2825

2826
	stmmac_set_mac(priv->ioaddr, false);
2827 2828
	if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
	    priv->pcs != STMMAC_PCS_RTBI)
2829
		stmmac_mdio_unregister(ndev);
2830 2831 2832 2833 2834 2835 2836 2837
	netif_carrier_off(ndev);
	unregister_netdev(ndev);
	free_netdev(ndev);

	return 0;
}

#ifdef CONFIG_PM
2838
int stmmac_suspend(struct net_device *ndev)
2839
{
2840
	struct stmmac_priv *priv = netdev_priv(ndev);
2841
	unsigned long flags;
2842

2843
	if (!ndev || !netif_running(ndev))
2844 2845
		return 0;

2846 2847 2848
	if (priv->phydev)
		phy_stop(priv->phydev);

2849
	spin_lock_irqsave(&priv->lock, flags);
2850

2851 2852
	netif_device_detach(ndev);
	netif_stop_queue(ndev);
2853

2854 2855 2856 2857 2858
	napi_disable(&priv->napi);

	/* Stop TX/RX DMA */
	priv->hw->dma->stop_tx(priv->ioaddr);
	priv->hw->dma->stop_rx(priv->ioaddr);
2859 2860

	stmmac_clear_descriptors(priv);
2861 2862 2863 2864

	/* Enable Power down mode by programming the PMT regs */
	if (device_may_wakeup(priv->device))
		priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2865
	else {
2866
		stmmac_set_mac(priv->ioaddr, false);
2867
		/* Disable clock in case of PWM is off */
2868
		clk_disable_unprepare(priv->stmmac_clk);
2869
	}
2870
	spin_unlock_irqrestore(&priv->lock, flags);
2871 2872 2873
	return 0;
}

2874
int stmmac_resume(struct net_device *ndev)
2875
{
2876
	struct stmmac_priv *priv = netdev_priv(ndev);
2877
	unsigned long flags;
2878

2879
	if (!netif_running(ndev))
2880 2881
		return 0;

2882
	spin_lock_irqsave(&priv->lock, flags);
2883

2884 2885 2886 2887
	/* Power Down bit, into the PM register, is cleared
	 * automatically as soon as a magic packet or a Wake-up frame
	 * is received. Anyway, it's better to manually clear
	 * this bit because it can generate problems while resuming
G
Giuseppe CAVALLARO 已提交
2888 2889
	 * from another devices (e.g. serial console).
	 */
2890
	if (device_may_wakeup(priv->device))
2891
		priv->hw->mac->pmt(priv->ioaddr, 0);
2892 2893
	else
		/* enable the clk prevously disabled */
2894
		clk_prepare_enable(priv->stmmac_clk);
2895

2896
	netif_device_attach(ndev);
2897 2898

	/* Enable the MAC and DMA */
2899
	stmmac_set_mac(priv->ioaddr, true);
2900 2901
	priv->hw->dma->start_tx(priv->ioaddr);
	priv->hw->dma->start_rx(priv->ioaddr);
2902 2903 2904

	napi_enable(&priv->napi);

2905
	netif_start_queue(ndev);
2906

2907
	spin_unlock_irqrestore(&priv->lock, flags);
2908 2909 2910 2911

	if (priv->phydev)
		phy_start(priv->phydev);

2912 2913 2914
	return 0;
}

2915
int stmmac_freeze(struct net_device *ndev)
2916 2917 2918 2919 2920 2921 2922
{
	if (!ndev || !netif_running(ndev))
		return 0;

	return stmmac_release(ndev);
}

2923
int stmmac_restore(struct net_device *ndev)
2924 2925 2926 2927 2928 2929 2930
{
	if (!ndev || !netif_running(ndev))
		return 0;

	return stmmac_open(ndev);
}
#endif /* CONFIG_PM */
2931

2932 2933 2934
/* Driver can be configured w/ and w/ both PCI and Platf drivers
 * depending on the configuration selected.
 */
2935 2936
static int __init stmmac_init(void)
{
2937
	int ret;
2938

2939 2940 2941 2942 2943 2944
	ret = stmmac_register_platform();
	if (ret)
		goto err;
	ret = stmmac_register_pci();
	if (ret)
		goto err_pci;
2945
	return 0;
2946 2947 2948 2949 2950
err_pci:
	stmmac_unregister_platform();
err:
	pr_err("stmmac: driver registration failed\n");
	return ret;
2951 2952 2953 2954
}

static void __exit stmmac_exit(void)
{
2955 2956
	stmmac_unregister_platform();
	stmmac_unregister_pci();
2957 2958 2959 2960 2961
}

module_init(stmmac_init);
module_exit(stmmac_exit);

2962 2963 2964 2965 2966 2967 2968 2969
#ifndef MODULE
static int __init stmmac_cmdline_opt(char *str)
{
	char *opt;

	if (!str || !*str)
		return -EINVAL;
	while ((opt = strsep(&str, ",")) != NULL) {
2970
		if (!strncmp(opt, "debug:", 6)) {
2971
			if (kstrtoint(opt + 6, 0, &debug))
2972 2973
				goto err;
		} else if (!strncmp(opt, "phyaddr:", 8)) {
2974
			if (kstrtoint(opt + 8, 0, &phyaddr))
2975 2976
				goto err;
		} else if (!strncmp(opt, "dma_txsize:", 11)) {
2977
			if (kstrtoint(opt + 11, 0, &dma_txsize))
2978 2979
				goto err;
		} else if (!strncmp(opt, "dma_rxsize:", 11)) {
2980
			if (kstrtoint(opt + 11, 0, &dma_rxsize))
2981 2982
				goto err;
		} else if (!strncmp(opt, "buf_sz:", 7)) {
2983
			if (kstrtoint(opt + 7, 0, &buf_sz))
2984 2985
				goto err;
		} else if (!strncmp(opt, "tc:", 3)) {
2986
			if (kstrtoint(opt + 3, 0, &tc))
2987 2988
				goto err;
		} else if (!strncmp(opt, "watchdog:", 9)) {
2989
			if (kstrtoint(opt + 9, 0, &watchdog))
2990 2991
				goto err;
		} else if (!strncmp(opt, "flow_ctrl:", 10)) {
2992
			if (kstrtoint(opt + 10, 0, &flow_ctrl))
2993 2994
				goto err;
		} else if (!strncmp(opt, "pause:", 6)) {
2995
			if (kstrtoint(opt + 6, 0, &pause))
2996
				goto err;
2997
		} else if (!strncmp(opt, "eee_timer:", 10)) {
2998 2999
			if (kstrtoint(opt + 10, 0, &eee_timer))
				goto err;
3000 3001 3002
		} else if (!strncmp(opt, "chain_mode:", 11)) {
			if (kstrtoint(opt + 11, 0, &chain_mode))
				goto err;
3003
		}
3004 3005
	}
	return 0;
3006 3007 3008 3009

err:
	pr_err("%s: ERROR broken module parameter conversion", __func__);
	return -EINVAL;
3010 3011 3012
}

__setup("stmmaceth=", stmmac_cmdline_opt);
G
Giuseppe CAVALLARO 已提交
3013
#endif /* MODULE */
3014 3015 3016 3017

MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
MODULE_LICENSE("GPL");