This will allow backends to make intelligent choices about how
to implement GUEST_BASE.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Alpha passes oldset by value in a register, and returns the newset
as the return value; as compared to the standard implementation in
which both are passed by reference.  This requires being able to
distinguish negative return values that are not errors.  Do this in
the same way as the Alpha Linux kernel, by storing a zero in V0 in
the implementation of the syscall.

At the same time, fix a think-o in the regular sigprocmask path in
which we passed the target, rather than the host, HOW value.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

rlim_t conversion between host and target added.
Otherwise there are some incorrect case like
- RLIM_INFINITY on 32bit target -> 64bit host.
- RLIM_INFINITY on 64bit host -> mips and sparc target ?
- Big value(for 32bit target) on 64bit host -> 32bit target.

One is added into getrlimit, setrlimit, and ugetrlimit. It converts both
RLIM_INFINITY and value bigger than target can hold(>31bit) to RLIM_INFINITY.

Another one is added to guest_stack_size calculation introduced by
703e0e89. The rule is mostly same except the result on the case is keeping
the value of guest_stack_size.

Slightly tested for SH4, and x86_64 -linux-user on x86_64-pc-linux host.
Signed-off-by: NTakashi YOSHII <takasi-y@ops.dti.ne.jp>
Acked-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Use an exception plus start_exclusive to implement the compare-and-swap.
This follows the example set by the MIPS and PPC ports.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

This is a per-cpu flag; there's no need for a spinlock of any kind.

We were also failing to manipulate the flag with $31 as a target reg
and failing to clear the flag on execution of a return-from-interrupt
instruction.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Arrange various declarations so that also non-CPU code can access
them, adjust users.

Move CPU specific code to cpus.c.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The current default stack limit of 512kB is far too small; a fair
number of gcc testsuite failures (for all guests) are directly
attributable to this.  Using the -s option in every invocation of
the emulator is annoying to say the least.

A reasonable compromise seems to be to honor the system rlimit.
At least on two Linux distributions, this is set to 8MB and 10MB
respectively.  If the system does not limit the stack, then we're
no worse off than before.

At the same time, rename the variable from x86_stack_size and
change the ultimate fallback size from 512kB to 8MB.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Don't return addresses that aren't properly aligned for the guest,
e.g. when the guest has a larger page size than the host.  Don't
return addresses that are outside the virtual address space for the
target, by paying proper attention to the h2g/g2h macros.

At the same time, place the default mapping base for 64-bit guests
(on 64-bit hosts) outside the low 4G.  Consistently interpret
mmap_next_start in the guest address space.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Move userland PALcode handling into linux-user main loop so that
we can send signals from there.  This also makes alpha_palcode.c
system-level only, so don't build it for userland.  Add defines
for GENTRAP PALcall mapping to signals.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The existing set of IPRs is totally irrelevant to user-mode emulation.
Indeed, they most are irrelevant to implementing kernel-mode emulation,
and would only be relevant to PAL-mode emulation, which I suspect that
no one will ever attempt.

Reducing the set of processor registers reduces the size of the CPU state.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

This is a reimplementation of prior versions which adds
the ability to define cpu models for contemporary processors.
The added models are likewise selected via -cpu <name>,
and are intended to displace the existing convention
of "-cpu qemu64" augmented with a series of feature flags.

A primary motivation was determination of a least common
denominator within a given processor class to simplify guest
migration.  It is still possible to modify an arbitrary model
via additional feature flags however the goal here was to
make doing so unnecessary in typical usage.  The other
consideration was providing models names reflective of
current processors.  Both AMD and Intel have reviewed the
models in terms of balancing generality of migration vs.
excessive feature downgrade relative to released silicon.

This version of the patch replaces the prior hard wired
definitions with a configuration file approach for new
models.  Existing models are thus far left as-is but may
easily be transitioned to (or may be overridden by) the
configuration file representation.

Proposed new model definitions are provided here for current
AMD and Intel processors.  Each model consists of a name
used to select it on the command line (-cpu <name>), and a
model_id which corresponds to a least common denominator
commercial instance of the processor class.

A table of names/model_ids may be queried via "-cpu ?model":

        :
    x86       Opteron_G3  AMD Opteron 23xx (Gen 3 Class Opteron)
    x86       Opteron_G2  AMD Opteron 22xx (Gen 2 Class Opteron)
    x86       Opteron_G1  AMD Opteron 240 (Gen 1 Class Opteron)
    x86          Nehalem  Intel Core i7 9xx (Nehalem Class Core i7)
    x86           Penryn  Intel Core 2 Duo P9xxx (Penryn Class Core 2)
    x86           Conroe  Intel Celeron_4x0 (Conroe/Merom Class Core 2)
        :

Also added is "-cpu ?dump" which exhaustively outputs all config
data for all defined models, and "-cpu ?cpuid" which enumerates
all qemu recognized CPUID feature flags.

The pseudo cpuid flag 'check' when added to the feature flag list
will warn when feature flags (either implicit in a cpu model or
explicit on the command line) would have otherwise been quietly
unavailable to a guest:

    # qemu-system-x86_64 ... -cpu Nehalem,check
    warning: host cpuid 0000_0001 lacks requested flag 'sse4.2|sse4_2' [0x00100000]
    warning: host cpuid 0000_0001 lacks requested flag 'popcnt' [0x00800000]

A similar 'enforce' pseudo flag exists which in addition
to the above causes qemu to error exit if requested flags are
unavailable.

Configuration data for a cpu model resides in the target config
file which by default will be installed as:

    /usr/local/etc/qemu/target-<arch>.conf

The format of this file should be self explanatory given the
definitions for the above six models and essentially mimics
the structure of the static x86_def_t x86_defs.

Encoding of cpuid flags names now allows aliases for both the
configuration file and the command line which reconciles some
Intel/AMD/Linux/Qemu naming differences.

This patch was tested relative to qemu.git.
Signed-off-by: Njohn cooper <john.cooper@redhat.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

For what I know DCR is always 32 bits wide, so we should also use uint32_t to
pass it along the stacks.

This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, making
it compile without --disable-werror
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Fix the alternate time base the same way as the default timebase. SPR_ATBL
should return a 64-bit value on 64 bit implementations.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

On PPC we have a 64-bit time base. Usually (PPC32) this is accessed using
two separate 32 bit SPR accesses to SPR_TBU and SPR_TBL.

On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full
64 bits as return value. If we only take the lower ones, fine. But Linux
wants to see all 64 bits or it breaks.

This patch makes PPC64 Linux work even after TB crossed the 32-bit boundary,
which usually happened a few seconds after bootup.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

mmap_lock() can be called while tb_lock() is being held. To
avoid deadlock when one thread is holding mmap_lock and another
tb_lock, _always_ lock first tb_lock().
Signed-off-by: NRiku Voipio <riku.voipio@nokia.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NPaul Brook <paul@codesourcery.com>

Signed-off-by: NPaul Brook <paul@codesourcery.com>

Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.
Signed-off-by: NPaul Brook <paul@codesourcery.com>

The variable CP0_LLAddr represent the full lladdr, not the actual
register value, which is only part of this value and depends on the
CPU.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b.
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

Some not so obvious bits, slirp and Xen were left alone for the time
being.
Signed-off-by: Nmalc <av1474@comtv.ru>

This reverts commit 91b40c5b.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

While i386, x86_64 and Sparc64/OpenBSD still worked after
df70204d, Sparc32 and Sparc64 Linux hosts
broke.

Partially revert the commit: make the restored code conditional to
!CONFIG_USER_PIE.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

There is a link hack in linux-user which produces an executable that
looks like PIE, but always has text relocations since all object files
isn't position-independent (compiled without -fpic/-fpie). Dynamic loader
has to do more work to load a binary with text relocations.

The best way to keep this functionality is to build a true PIE without
text relocations.
Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

tl and tsptr of members sparc64 cpu state must be changed
simultaneously to keep trap state window in sync with current
trap level. Currently translation of store to tl does not change
tsptr, which leads to corrupt trap state on corresponding
trap level.

This patch removes tsptr from sparc64 cpu state and replaces
all uses with call to helper routine.

Changes v0->v1:
- reimplemented helper routine with tcg generator
- on cpu reset trap type and pstate are populated with power-on reset
values, including tl=maxtl

Signed-off-by: igor.v.kovalenko@gmail.com
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

We handle conditional stores as an exception so we can ensure that no
other thread is changing memory out from underneath us.
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Nmalc <av1474@comtv.ru>

Signed-off-by: NJuan Quintela <quintela@redhat.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

Re-implement GUEST_BASE support.
Offset guest ddress space by default if the guest binary contains
regions below the host mmap_min_addr.
Implement support for i386, x86-64 and arm hosts.
Signed-off-by: NRiku Voipio <riku.voipio@iki.fi>
Signed-off-by: NPaul Brook <paul@codesourcery.com>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: Nmalc <av1474@comtv.ru>

Signed-off-by: NIsaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

Implement MIPS ll/sc instructions using atomic compare+exchange.
Signed-off-by: NPaul Brook <paul@codesourcery.com>

The clone syscall takes 6 args.
Signed-off-by: NPaul Brook <paul@codesourcery.com>

There's a error When doing something like that :
find / -type f -print0 | xargs -0 echo

[ done in a arm chroot with qemu-arm and linux binfmt stuff or with
find / -type f -print0 | qemu-arm -L <path> <path>/usr/bin/xargs -0
echo ]

Doing this outsite qemu is fine. The problem was the huge number of
parameters. Increasing MAX_ARG_PAGES is fixing that.

While I was at it, I've modified linux-user/main.c to report error code
of loader_exec. It helps to debug/know what's wrong.
Signed-off-by: NArnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: NRiku Voipio <riku.voipio@iki.fi>