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提交 90e189ec 编写于 作者: B Blue Swirl
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Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx 

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
上级 636aa200
展开全部 隐藏空白更改
内联 并排
Showing with 269 addition and 245 deletion
darwin-user/main.c
浏览文件 @ 90e189ec
......@@ -156,7 +156,7 @@ void cpu_loop(CPUPPCState *env)
/* To deal with multiple qemu header version as host for the darwin-user code */
# define DAR SPR_DAR
#endif
EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
env->spr[SPR_DAR]);
/* Handle this via the gdb */
gdb_handlesig (env, SIGSEGV);
......@@ -165,7 +165,7 @@ void cpu_loop(CPUPPCState *env)
queue_signal(info.si_signo, &info);
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx "\n",
env->spr[SPR_DAR]);
/* Handle this via the gdb */
gdb_handlesig (env, SIGSEGV);
......
hw/ppc.c
浏览文件 @ 90e189ec
......@@ -795,9 +795,9 @@ static void cpu_4xx_fit_cb (void *opaque)
env->spr[SPR_40x_TSR] |= 1 << 26;
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
LOG_TB("%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
}
/* Programmable interval timer */
......@@ -841,12 +841,12 @@ static void cpu_4xx_pit_cb (void *opaque)
if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
start_stop_pit(env, tb_env, 1);
LOG_TB("%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
"%016" PRIx64 "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
ppcemb_timer->pit_reload);
LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
"%016" PRIx64 "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
ppcemb_timer->pit_reload);
}
/* Watchdog timer */
......@@ -881,8 +881,8 @@ static void cpu_4xx_wdt_cb (void *opaque)
next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq);
if (next == now)
next++;
LOG_TB("%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
case 0x0:
case 0x1:
......@@ -924,7 +924,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
tb_env = env->tb_env;
ppcemb_timer = tb_env->opaque;
LOG_TB("%s val" ADDRX "\n", __func__, val);
LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
ppcemb_timer->pit_reload = val;
start_stop_pit(env, tb_env, 0);
}
......@@ -936,7 +936,7 @@ target_ulong load_40x_pit (CPUState *env)
void store_booke_tsr (CPUState *env, target_ulong val)
{
LOG_TB("%s: val " ADDRX "\n", __func__, val);
LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
if (val & 0x80000000)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
......@@ -947,7 +947,7 @@ void store_booke_tcr (CPUState *env, target_ulong val)
ppc_tb_t *tb_env;
tb_env = env->tb_env;
LOG_TB("%s: val " ADDRX "\n", __func__, val);
LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
env->spr[SPR_40x_TCR] = val & 0xFFC00000;
start_stop_pit(env, tb_env, 1);
cpu_4xx_wdt_cb(env);
......
hw/ppc405_boards.c
浏览文件 @ 90e189ec
......@@ -221,8 +221,8 @@ static void ref405ep_init (ram_addr_t ram_size,
bios_offset = qemu_ram_alloc(bios_size);
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " ADDRX " at offset %08lx "
" addr " ADDRX " '%s' %d\n",
printf("Register parallel flash %d size " TARGET_FMT_lx
" at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
......@@ -536,8 +536,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
fl_sectors = (bios_size + 65535) >> 16;
bios_offset = qemu_ram_alloc(bios_size);
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " ADDRX " at offset %08lx "
" addr " ADDRX " '%s' %d\n",
printf("Register parallel flash %d size " TARGET_FMT_lx
" at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
......@@ -577,8 +577,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
bios_size = 32 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " ADDRX " at offset %08lx "
" addr " ADDRX " '%s'\n",
printf("Register parallel flash %d size " TARGET_FMT_lx
" at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
bdrv_get_device_name(dinfo->bdrv));
#endif
......
hw/ppc405_uc.c
浏览文件 @ 90e189ec
......@@ -267,7 +267,7 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
opba = opaque;
switch (addr) {
......@@ -291,7 +291,8 @@ static void opba_writeb (void *opaque,
ppc4xx_opba_t *opba;
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
opba = opaque;
switch (addr) {
......@@ -311,7 +312,7 @@ static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = opba_readb(opaque, addr) << 8;
ret |= opba_readb(opaque, addr + 1);
......@@ -323,7 +324,8 @@ static void opba_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
opba_writeb(opaque, addr, value >> 8);
opba_writeb(opaque, addr + 1, value);
......@@ -334,7 +336,7 @@ static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = opba_readb(opaque, addr) << 24;
ret |= opba_readb(opaque, addr + 1) << 16;
......@@ -346,7 +348,8 @@ static void opba_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
opba_writeb(opaque, addr, value >> 24);
opba_writeb(opaque, addr + 1, value >> 16);
......@@ -380,7 +383,7 @@ static void ppc4xx_opba_init(target_phys_addr_t base)
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA
printf("%s: offset " PADDRX "\n", __func__, base);
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(opba_read, opba_write, opba);
cpu_register_physical_memory(base, 0x002, io);
......@@ -744,7 +747,7 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
......@@ -757,7 +760,8 @@ static void ppc405_gpio_writeb (void *opaque,
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
}
......@@ -767,7 +771,7 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
......@@ -780,7 +784,8 @@ static void ppc405_gpio_writew (void *opaque,
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
}
......@@ -790,7 +795,7 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
......@@ -803,7 +808,8 @@ static void ppc405_gpio_writel (void *opaque,
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
}
......@@ -833,7 +839,7 @@ static void ppc405_gpio_init(target_phys_addr_t base)
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO
printf("%s: offset " PADDRX "\n", __func__, base);
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
cpu_register_physical_memory(base, 0x038, io);
......@@ -1035,7 +1041,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
i2c = opaque;
switch (addr) {
......@@ -1090,7 +1096,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
break;
}
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
#endif
return ret;
......@@ -1102,7 +1108,8 @@ static void ppc4xx_i2c_writeb (void *opaque,
ppc4xx_i2c_t *i2c;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
i2c = opaque;
switch (addr) {
......@@ -1160,7 +1167,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = ppc4xx_i2c_readb(opaque, addr) << 8;
ret |= ppc4xx_i2c_readb(opaque, addr + 1);
......@@ -1172,7 +1179,8 @@ static void ppc4xx_i2c_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
ppc4xx_i2c_writeb(opaque, addr, value >> 8);
ppc4xx_i2c_writeb(opaque, addr + 1, value);
......@@ -1183,7 +1191,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = ppc4xx_i2c_readb(opaque, addr) << 24;
ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
......@@ -1197,7 +1205,8 @@ static void ppc4xx_i2c_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
ppc4xx_i2c_writeb(opaque, addr, value >> 24);
ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
......@@ -1241,7 +1250,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
i2c->irq = irq;
#ifdef DEBUG_I2C
printf("%s: offset " PADDRX "\n", __func__, base);
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
cpu_register_physical_memory(base, 0x011, io);
......@@ -1269,7 +1278,7 @@ struct ppc4xx_gpt_t {
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
/* XXX: generate a bus fault */
return -1;
......@@ -1279,7 +1288,8 @@ static void ppc4xx_gpt_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
/* XXX: generate a bus fault */
}
......@@ -1287,7 +1297,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
/* XXX: generate a bus fault */
return -1;
......@@ -1297,7 +1307,8 @@ static void ppc4xx_gpt_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
/* XXX: generate a bus fault */
}
......@@ -1361,7 +1372,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
int idx;
#ifdef DEBUG_GPT
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
gpt = opaque;
switch (addr) {
......@@ -1416,7 +1427,8 @@ static void ppc4xx_gpt_writel (void *opaque,
int idx;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
gpt = opaque;
switch (addr) {
......@@ -1522,7 +1534,7 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
}
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
#ifdef DEBUG_GPT
printf("%s: offset " PADDRX "\n", __func__, base);
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
cpu_register_physical_memory(base, 0x0d4, io);
......
hw/ppc4xx_devs.c
浏览文件 @ 90e189ec
......@@ -235,7 +235,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
uic = opaque;
dcrn -= uic->dcr_base;
LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
......@@ -368,7 +368,8 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
bcr = 0x000C0000;
break;
default:
printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
ram_size);
return 0x00000000;
}
bcr |= ram_base & 0xFF800000;
......@@ -401,7 +402,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
if (*bcrp & 0x00000001) {
/* Unmap RAM */
#ifdef DEBUG_SDRAM
printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(*bcrp), sdram_size(*bcrp));
#endif
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
......@@ -410,7 +411,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
*bcrp = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
#ifdef DEBUG_SDRAM
printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(bcr), sdram_size(bcr));
#endif
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
......@@ -439,7 +440,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
for (i = 0; i < sdram->nbanks; i++) {
#ifdef DEBUG_SDRAM
printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
......
hw/ppc_prep.c
浏览文件 @ 90e189ec
......@@ -112,7 +112,10 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
static void _PPC_intack_write (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
// printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
#if 0
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
#endif
}
static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
......@@ -121,7 +124,10 @@ static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
if ((addr & 0xf) == 0)
retval = pic_intack_read(isa_pic);
// printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
#if 0
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
retval);
#endif
return retval;
}
......@@ -191,7 +197,8 @@ static struct {
static void PPC_XCSR_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writew (void *opaque,
......@@ -200,7 +207,8 @@ static void PPC_XCSR_writew (void *opaque,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writel (void *opaque,
......@@ -209,14 +217,16 @@ static void PPC_XCSR_writel (void *opaque,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
retval);
return retval;
}
......@@ -225,7 +235,8 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
retval);
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap16(retval);
#endif
......@@ -237,7 +248,8 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
retval);
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap32(retval);
#endif
......@@ -469,7 +481,7 @@ static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
cpu_outw(NULL, addr, value);
}
......@@ -483,7 +495,7 @@ static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap16(ret);
#endif
PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
return ret;
}
......@@ -497,7 +509,7 @@ static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
cpu_outl(NULL, addr, value);
}
......@@ -511,7 +523,7 @@ static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap32(ret);
#endif
PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
return ret;
}
......
linux-user/main.c
浏览文件 @ 90e189ec
......@@ -1140,7 +1140,7 @@ void cpu_loop(CPUPPCState *env)
"Aborting\n");
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
env->spr[SPR_DAR]);
/* XXX: check this. Seems bugged */
switch (env->error_code & 0xFF000000) {
......@@ -1172,8 +1172,8 @@ void cpu_loop(CPUPPCState *env)
queue_signal(env, info.si_signo, &info);
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
env->spr[SPR_SRR0]);
EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
"\n", env->spr[SPR_SRR0]);
/* XXX: check this */
switch (env->error_code & 0xFF000000) {
case 0x40000000:
......
target-ppc/cpu.h
浏览文件 @ 90e189ec
......@@ -57,8 +57,6 @@
#include "cpu-defs.h"
#define REGX "%016" PRIx64
#define ADDRX TARGET_FMT_lx
#define PADDRX TARGET_FMT_plx
#include <setjmp.h>
......
target-ppc/helper.c
浏览文件 @ 90e189ec
此差异已折叠。
target-ppc/op_helper.c
浏览文件 @ 90e189ec
......@@ -56,14 +56,14 @@ void helper_raise_exception (uint32_t exception)
/* SPR accesses */
void helper_load_dump_spr (uint32_t sprn)
{
qemu_log("Read SPR %d %03x => " ADDRX "\n",
sprn, sprn, env->spr[sprn]);
qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
env->spr[sprn]);
}
void helper_store_dump_spr (uint32_t sprn)
{
qemu_log("Write SPR %d %03x <= " ADDRX "\n",
sprn, sprn, env->spr[sprn]);
qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
env->spr[sprn]);
}
target_ulong helper_load_tbl (void)
......@@ -160,8 +160,8 @@ void helper_store_hid0_601 (target_ulong val)
env->hflags_nmsr &= ~(1 << MSR_LE);
env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
env->hflags |= env->hflags_nmsr;
qemu_log("%s: set endianness to %c => " ADDRX "\n",
__func__, val & 0x8 ? 'l' : 'b', env->hflags);
qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
val & 0x8 ? 'l' : 'b', env->hflags);
}
env->spr[SPR_HID0] = (uint32_t)val;
}
......@@ -3804,9 +3804,9 @@ static void do_6xx_tlb (target_ulong new_EPN, int is_code)
EPN = env->spr[SPR_DMISS];
}
way = (env->spr[SPR_SRR1] >> 17) & 1;
LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX " way %d\n",
__func__, new_EPN, EPN, CMP, RPN, way);
LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
" PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
RPN, way);
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
......@@ -3832,9 +3832,9 @@ static void do_74xx_tlb (target_ulong new_EPN, int is_code)
CMP = env->spr[SPR_PTEHI];
EPN = env->spr[SPR_TLBMISS] & ~0x3;
way = env->spr[SPR_TLBMISS] & 0x3;
LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX " way %d\n",
__func__, new_EPN, EPN, CMP, RPN, way);
LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
" PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
RPN, way);
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
......@@ -3958,14 +3958,15 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
ppcemb_tlb_t *tlb;
target_ulong page, end;
LOG_SWTLB("%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
LOG_SWTLB("%s entry %d val " TARGET_FMT_lx "\n", __func__, (int)entry,
val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
LOG_SWTLB("%s: invalidate old TLB %d start " ADDRX
" end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end "
TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
......@@ -3990,18 +3991,18 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
}
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
tlb->attr = val & 0xFF;
LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
/* Invalidate new TLB (if valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
LOG_SWTLB("%s: invalidate TLB %d start " ADDRX
" end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end "
TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
......@@ -4011,7 +4012,8 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
{
ppcemb_tlb_t *tlb;
LOG_SWTLB("%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
LOG_SWTLB("%s entry %i val " TARGET_FMT_lx "\n", __func__, (int)entry,
val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
tlb->RPN = val & 0xFFFFFC00;
......@@ -4020,13 +4022,13 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
tlb->prot |= PAGE_EXEC;
if (val & 0x100)
tlb->prot |= PAGE_WRITE;
LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
}
target_ulong helper_4xx_tlbsx (target_ulong address)
......@@ -4041,8 +4043,8 @@ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
target_ulong EPN, RPN, size;
int do_flush_tlbs;
LOG_SWTLB("%s word %d entry %d value " ADDRX "\n",
__func__, word, (int)entry, value);
LOG_SWTLB("%s word %d entry %d value " TARGET_FMT_lx "\n",
__func__, word, (int)entry, value);
do_flush_tlbs = 0;
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
......
target-ppc/translate.c
浏览文件 @ 90e189ec
......@@ -3755,17 +3755,17 @@ static inline void gen_op_mfspr(DisasContext *ctx)
*/
if (sprn != SPR_PVR) {
qemu_log("Trying to read privileged spr %d %03x at "
ADDRX "\n", sprn, sprn, ctx->nip);
printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
sprn, sprn, ctx->nip);
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
printf("Trying to read privileged spr %d %03x at "
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
}
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
/* Not defined */
qemu_log("Trying to read invalid spr %d %03x at "
ADDRX "\n", sprn, sprn, ctx->nip);
printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
sprn, sprn, ctx->nip);
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
}
......@@ -3905,16 +3905,16 @@ static void gen_mtspr(DisasContext *ctx)
} else {
/* Privilege exception */
qemu_log("Trying to write privileged spr %d %03x at "
ADDRX "\n", sprn, sprn, ctx->nip);
printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
sprn, sprn, ctx->nip);
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
"\n", sprn, sprn, ctx->nip);
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
/* Not defined */
qemu_log("Trying to write invalid spr %d %03x at "
ADDRX "\n", sprn, sprn, ctx->nip);
printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
sprn, sprn, ctx->nip);
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
}
......@@ -8839,10 +8839,12 @@ void cpu_dump_state (CPUState *env, FILE *f,
int i;
cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
env->nip, env->lr, env->ctr, env->xer);
cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
TARGET_FMT_lx " XER %08x\n", env->nip, env->lr, env->ctr,
env->xer);
cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
env->hflags, env->mmu_idx);
#if !defined(NO_TIMER_DUMP)
cpu_fprintf(f, "TB %08x %08x "
#if !defined(CONFIG_USER_ONLY)
......@@ -8876,7 +8878,8 @@ void cpu_dump_state (CPUState *env, FILE *f,
a = 'E';
cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
}
cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve_addr);
cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
env->reserve_addr);
for (i = 0; i < 32; i++) {
if ((i & (RFPL - 1)) == 0)
cpu_fprintf(f, "FPR%02d", i);
......@@ -8886,8 +8889,9 @@ void cpu_dump_state (CPUState *env, FILE *f,
}
cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
#if !defined(CONFIG_USER_ONLY)
cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
cpu_fprintf(f, "SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx " SDR1 "
TARGET_FMT_lx "\n", env->spr[SPR_SRR0], env->spr[SPR_SRR1],
env->sdr1);
#endif
#undef RGPL
......@@ -9016,7 +9020,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
gen_opc_icount[lj] = num_insns;
}
LOG_DISAS("----------------\n");
LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
......@@ -9044,12 +9048,12 @@ static inline void gen_intermediate_code_internal(CPUState *env,
if (unlikely(handler->handler == &gen_invalid)) {
if (qemu_log_enabled()) {
qemu_log("invalid/unsupported opcode: "
"%02x - %02x - %02x (%08x) " ADDRX " %d\n",
opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
"%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
} else {
printf("invalid/unsupported opcode: "
"%02x - %02x - %02x (%08x) " ADDRX " %d\n",
"%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
}
......@@ -9057,13 +9061,13 @@ static inline void gen_intermediate_code_internal(CPUState *env,
if (unlikely((ctx.opcode & handler->inval) != 0)) {
if (qemu_log_enabled()) {
qemu_log("invalid bits: %08x for opcode: "
"%02x - %02x - %02x (%08x) " ADDRX "\n",
ctx.opcode & handler->inval, opc1(ctx.opcode),
opc2(ctx.opcode), opc3(ctx.opcode),
ctx.opcode, ctx.nip - 4);
"%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
ctx.opcode & handler->inval, opc1(ctx.opcode),
opc2(ctx.opcode), opc3(ctx.opcode),
ctx.opcode, ctx.nip - 4);
} else {
printf("invalid bits: %08x for opcode: "
"%02x - %02x - %02x (%08x) " ADDRX "\n",
"%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
ctx.opcode & handler->inval, opc1(ctx.opcode),
opc2(ctx.opcode), opc3(ctx.opcode),
ctx.opcode, ctx.nip - 4);
......
target-ppc/translate_init.c
浏览文件 @ 90e189ec
......@@ -543,8 +543,8 @@ static inline void spr_register (CPUPPCState *env, int num,
exit(1);
}
#if defined(PPC_DEBUG_SPR)
printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
initial_value);
printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
name, initial_value);
#endif
spr->name = name;
spr->uea_read = uea_read;
......
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