1. 15 6月, 2012 1 次提交
  2. 14 6月, 2012 1 次提交
  3. 15 3月, 2012 1 次提交
  4. 29 2月, 2012 1 次提交
  5. 12 12月, 2011 1 次提交
  6. 07 8月, 2011 1 次提交
  7. 27 6月, 2011 1 次提交
  8. 18 9月, 2010 1 次提交
  9. 16 9月, 2010 1 次提交
  10. 05 7月, 2010 2 次提交
  11. 19 3月, 2010 1 次提交
  12. 17 3月, 2010 1 次提交
    • P
      Large page TLB flush · d4c430a8
      Paul Brook 提交于
      QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
      pages then we effectively split these into multiple smaller pages, and
      populate the corresponding TLB entries on demand.
      
      When the guest invalidates the TLB by virtual address we must invalidate
      all entries covered by the large page.  However the address used to
      invalidate the entry may not be present in the QEMU TLB, so we do not
      know which regions to clear.
      
      Implementing a full vaiable size TLB is hard and slow, so just keep a
      simple address/mask pair to record which addresses may have been mapped by
      large pages.  If the guest invalidates this region then flush the
      whole TLB.
      Signed-off-by: NPaul Brook <paul@codesourcery.com>
      d4c430a8
  13. 13 3月, 2010 1 次提交
  14. 15 2月, 2010 1 次提交
  15. 10 10月, 2009 1 次提交
  16. 08 10月, 2009 1 次提交
  17. 02 10月, 2009 2 次提交
  18. 17 7月, 2009 1 次提交
  19. 25 4月, 2009 1 次提交
  20. 16 1月, 2009 2 次提交
  21. 05 1月, 2009 1 次提交
  22. 08 10月, 2008 2 次提交
  23. 06 9月, 2008 1 次提交
  24. 03 9月, 2008 1 次提交
  25. 10 6月, 2008 1 次提交
  26. 28 5月, 2008 1 次提交
  27. 13 5月, 2008 1 次提交
  28. 06 5月, 2008 1 次提交
  29. 03 5月, 2008 1 次提交
    • E
      CRIS updates: · b41f7df0
      edgar_igl 提交于
      * Support both the I and D MMUs and improve the accuracy of the MMU model.
      * Handle the automatic user/kernel stack pointer switching when leaving or entering user mode.
      * Move the CCS evaluation into helper funcs.
      * Make sure user-mode cannot change flags only writeable in kernel mode.
      * More conversion of the translator into TCG.
      * Handle exceptions while in a delayslot.
      
      
      git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4299 c046a42c-6fe2-441c-8c8c-71466251a162
      b41f7df0
  30. 14 3月, 2008 1 次提交
  31. 02 3月, 2008 1 次提交
  32. 28 2月, 2008 1 次提交
  33. 28 10月, 2007 1 次提交
  34. 14 10月, 2007 1 次提交
    • J
      Replace is_user variable with mmu_idx in softmmu core, · 6ebbf390
      j_mayer 提交于
        allowing support of more than 2 mmu access modes.
      Add backward compatibility is_user variable in targets code when needed.
      Implement per target cpu_mmu_index function, avoiding duplicated code
        and #ifdef TARGET_xxx in softmmu core functions.
      Implement per target mmu modes definitions. As an example, add PowerPC
        hypervisor mode definition and Alpha executive and kernel modes definitions.
      Optimize PowerPC case, precomputing mmu_idx when MSR register changes
        and using the same definition in code translation code.
      
      
      git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
      6ebbf390
  35. 08 10月, 2007 1 次提交