Skip to content

Q
qemu

openeuler / qemu

通知 10
Star 0
Fork 0
Q
qemu

体验新版 GitCode，发现更多精彩内容 >>

切换分支/标签
  1. 21 5月, 2010 1 次提交
  3. 20 5月, 2010 2 次提交
  5. 16 5月, 2010 2 次提交
  7. 10 5月, 2010 1 次提交
  9. 07 5月, 2010 2 次提交
  11. 24 4月, 2010 1 次提交
  13. 13 3月, 2010 1 次提交
  15. 23 1月, 2010 1 次提交
  17. 16 1月, 2010 1 次提交
    • A
      sparc32 do_unassigned_access overhaul v2 · 576c2cdc
      由 Artyom Tarasenko 提交于 
      According to pages 9-31 - 9-34 of "SuperSPARC & MultiCache Controller
User's Manual":

1. "A lower priority fault may not overwrite the
    MFSR status of a higher priority fault."
2. The MFAR is overwritten according to the policy defined for the MFSR
3. The overwrite bit is asserted if the fault status register (MFSR)
   has been written more than once by faults of the same class
4. SuperSPARC will never place instruction fault addresses in the MFAR.

Implementation of points 1-3 allows booting Solaris 2.6 and 2.5.1.

v2: CODING_STYLE fixes
Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      576c2cdc
  19. 09 1月, 2010 4 次提交
  21. 08 1月, 2010 1 次提交
  23. 07 1月, 2010 1 次提交
  25. 03 1月, 2010 2 次提交
  27. 05 11月, 2009 1 次提交
  29. 14 10月, 2009 1 次提交
  31. 02 10月, 2009 2 次提交
  33. 24 9月, 2009 1 次提交
    • I
      sparc64-8bit-asi · 01b5d4e5
      由 Igor V. Kovalenko 提交于 
      Sparc64 alternate space load/store helpers expect 8 bit ASI value,
while wrasi implementation sign-extends ASI operand causing
for example 0x80 to appear as 0xFFFFFF80. Resulting value falls
out of switch in helpers and causes obscure load/store faults.

- correct wrasi by masking lower 8 bits of xor result
- use lower 8 bits of ASI register in helpers
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      01b5d4e5
  35. 05 8月, 2009 1 次提交
    • I
      Sparc64: replace tsptr with helper routine · 8194f35a
      由 Igor Kovalenko 提交于 
      tl and tsptr of members sparc64 cpu state must be changed
simultaneously to keep trap state window in sync with current
trap level. Currently translation of store to tl does not change
tsptr, which leads to corrupt trap state on corresponding
trap level.

This patch removes tsptr from sparc64 cpu state and replaces
all uses with call to helper routine.

Changes v0->v1:
- reimplemented helper routine with tcg generator
- on cpu reset trap type and pstate are populated with power-on reset
values, including tl=maxtl

Signed-off-by: igor.v.kovalenko@gmail.com
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      8194f35a
  37. 28 7月, 2009 1 次提交
  39. 27 7月, 2009 2 次提交
    • I
      sparc64 really implement itlb/dtlb automatic replacement writes · f707726e
      由 Igor Kovalenko 提交于 
      - implement "used" bit in tlb translation entry
- mark tlb entry used if qemu code/data translation succeeds
- fold i/d mmu replacement writes code into replace_tlb_1bit_lru which
adds 1bit lru replacement algorithm; previously code tried to replace
first unlocked entry only

- extract more bitmasks to named macros
- add "immu" or "dmmu" type name to debugging output where appropriate

Signed-off-by: igor.v.kovalenko@gmail.com

--
Kind regards,
Igor V. Kovalenko
      f707726e
    • I
      sparc64 name mmu registers and general cleanup · 6e8e7d4c
      由 Igor Kovalenko 提交于 
      - add names to mmu registers, this helps understanding the code which
uses/modifies them.
- fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries
- extract demap_tlb routine (code duplication)
- extract replace_tlb routine (code duplication)

- flush qemu tlb translations when replacing sparc64 mmu tlb entries

I have no test case which demands flushing qemu translations,
and this patch should have no other visible changes to runtime.

Signed-off-by: igor.v.kovalenko@gmail.com

--
Kind regards,
Igor V. Kovalenko
      6e8e7d4c
  41. 21 7月, 2009 1 次提交
  43. 12 7月, 2009 2 次提交
    • I
      sparc64: trap handling corrections · 5210977a
      由 Igor Kovalenko 提交于 
      On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
> On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
>> Good trap handling is required to process interrupts.
>>  This patch fixes the following:
>>
>>  - sparc64 has no wim register
>>  - sparc64 has no psret register, use IE bit of pstate
>>   extract IE checking code to cpu_interrupts_enabled
>>  - alternate globals are not available if cpu has GL feature
>>   in this case bit AG of pstate is constant zero
>>  - write to pstate must actually write pstate
>>   even if cpu has GL feature
>>
>>  Also timer interrupt is handled using do_interrupt.
>
> A bit too much for one patch. Please also remove the code instead of
> commenting out.

I now excluded timer interrupt related part.
To my mind other changes are essentially tied together.

> PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32.

Fixed, please find attached the updated version.

--
Kind regards,
Igor V. Kovalenko
      5210977a
    • I
      sparc64: fix helper_st_asi little endian case typo · 5b0f0bec
      由 Igor Kovalenko 提交于 
      On Sun, Jul 12, 2009 at 12:43 AM, Stuart Brady<sdbrady@ntlworld.com> wrote:
> On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote:
>> It is clear that intention is to byte-swap value to be written, not
>> the target address.
>
> @@ -1949,13 +1949,13 @@ void helper_st_asi(target_ulong addr, ta
>     case 0x89: // Secondary LE
>         switch(size) {
>         case 2:
> -            addr = bswap16(addr);
> +            addr = bswap16(val);
>             ^^^^
> Shouldn't that be 'val = bswap16(val)' (and likewise for the 32-bit and
> 64-bit cases)?  Also needs a 'signed-off-by:'...
>
> Cheers,
> --
> Stuart Brady
>

Thanks, that part I did not runtime-tested.
Not sure if those asi stores are of any use for user-mode emulator.

Please find attached the corrected version.

Signed-off-by: igor.v.kovalenko@gmail.com

--
Kind regards,
Igor V. Kovalenko
      5b0f0bec
  45. 14 5月, 2009 1 次提交
  47. 10 5月, 2009 7 次提交