1. 17 12月, 2018 3 次提交
  2. 16 6月, 2018 1 次提交
    • R
      tcg: Reduce max TB opcode count · 9f754620
      Richard Henderson 提交于
      Also, assert that we don't overflow any of two different offsets into
      the TB. Both unwind and goto_tb both record a uint16_t for later use.
      
      This fixes an arm-softmmu test case utilizing NEON in which there is
      a TB generated that runs to 7800 opcodes, and compiles to 96k on an
      x86_64 host.  This overflows the 16-bit offset in which we record the
      goto_tb reset offset.  Because of that overflow, we install a jump
      destination that goes to neverland.  Boom.
      
      With this reduced op count, the same TB compiles to about 48k for
      aarch64, ppc64le, and x86_64 hosts, and neither assertion fires.
      
      Cc: qemu-stable@nongnu.org
      Reported-by: N"Jason A. Donenfeld" <Jason@zx2c4.com>
      Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
      9f754620
  3. 16 4月, 2018 1 次提交
    • P
      tcg/mips: Handle large offsets from target env to tlb_table · 161dfd1e
      Peter Maydell 提交于
      The MIPS TCG target makes the assumption that the offset from the
      target env pointer to the tlb_table is less than about 64K. This
      used to be true, but gradual addition of features to the Arm
      target means that it's no longer true there. This results in
      the build-time assertion failing:
      
      In file included from /home/pm215/qemu/include/qemu/osdep.h:36:0,
                       from /home/pm215/qemu/tcg/tcg.c:28:
      /home/pm215/qemu/tcg/mips/tcg-target.inc.c: In function ‘tcg_out_tlb_load’:
      /home/pm215/qemu/include/qemu/compiler.h:90:36: error: static assertion failed: "not expecting: offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) > 0x7ff0 + 0x7fff"
       #define QEMU_BUILD_BUG_MSG(x, msg) _Static_assert(!(x), msg)
                                          ^
      /home/pm215/qemu/include/qemu/compiler.h:98:30: note: in expansion of macro ‘QEMU_BUILD_BUG_MSG’
       #define QEMU_BUILD_BUG_ON(x) QEMU_BUILD_BUG_MSG(x, "not expecting: " #x)
                                    ^
      /home/pm215/qemu/tcg/mips/tcg-target.inc.c:1236:9: note: in expansion of macro ‘QEMU_BUILD_BUG_ON’
               QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
               ^
      /home/pm215/qemu/rules.mak:66: recipe for target 'tcg/tcg.o' failed
      
      An ideal long term approach would be to rearrange the CPU state
      so that the tlb_table was not so far along it, but this is tricky
      because it would move it from the "not cleared on CPU reset" part
      of the struct to the "cleared on CPU reset" part. As a simple fix
      for the 2.12 release, make the MIPS TCG target handle an arbitrary
      offset by emitting more add instructions. This will mean an extra
      instruction in the fastpath for TCG loads and stores for the
      affected guests (currently just aarch64-softmmu).
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Acked-by: NMichael S. Tsirkin <mst@redhat.com>
      Message-id: 20180413142336.32163-1-peter.maydell@linaro.org
      161dfd1e
  4. 11 10月, 2017 1 次提交
  5. 10 10月, 2017 1 次提交
  6. 17 9月, 2017 3 次提交
  7. 08 9月, 2017 2 次提交
    • R
      tcg: Rearrange ldst label tracking · 659ef5cb
      Richard Henderson 提交于
      Dispense with TCGBackendData, as it has never been used for more than
      holding a single pointer.  Use a define in the cpu/tcg-target.h to
      signal requirement for TCGLabelQemuLdst, so that we can drop the no-op
      tcg-be-null.h stubs.  Rename tcg-be-ldst.h to tcg-ldst.inc.c.
      Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      659ef5cb
    • R
      tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h · a8583393
      Richard Henderson 提交于
      Replace the USE_DIRECT_JUMP ifdef with a TCG_TARGET_HAS_direct_jump
      boolean test.  Replace the tb_set_jmp_target1 ifdef with an unconditional
      function tb_target_set_jmp_target.
      
      While we're touching all backends, add a parameter for tb->tc_ptr;
      we're going to need it shortly for some backends.
      
      Move tb_set_jmp_target and tb_add_jump from exec-all.h to cpu-exec.c.
      
      This opens the possibility for TCG_TARGET_HAS_direct_jump to be
      a runtime decision -- based on host cpu capabilities, the size of
      code_gen_buffer, or a future debugging switch.
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      a8583393
  8. 20 7月, 2017 1 次提交
  9. 10 7月, 2017 1 次提交
  10. 06 6月, 2017 1 次提交
  11. 06 5月, 2017 1 次提交
  12. 11 1月, 2017 4 次提交
  13. 07 1月, 2017 10 次提交
  14. 16 9月, 2016 2 次提交
  15. 06 7月, 2016 1 次提交
    • R
      tcg: Optimize spills of constants · 59d7c14e
      Richard Henderson 提交于
      While we can store constants via constrants on INDEX_op_st_i32 et al,
      we weren't able to spill constants to backing store.
      
      Add a new backend interface, tcg_out_sti, which may store the constant
      (and is allowed to fail).  Rearrange the temp_* helpers so that we only
      attempt to directly store a constant when the temp is becoming dead/free.
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      59d7c14e
  16. 13 5月, 2016 2 次提交
  17. 21 4月, 2016 2 次提交
  18. 06 4月, 2016 1 次提交
    • J
      tcg/mips: Fix type of tcg_target_reg_alloc_order[] · 2dc7553d
      James Hogan 提交于
      The MIPS TCG backend is the only one to have
      tcg_target_reg_alloc_order[] elements of type TCGReg rather than int.
      This resulted in commit 91478cef ("tcg: Allocate indirect_base
      temporaries in a different order") breaking the build on MIPS since the
      type differed from indirect_reg_alloc_order[]:
      
      tcg/tcg.c:1725:44: error: pointer type mismatch in conditional expression [-Werror]
           order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order;
                                                  ^
      
      Make it an array of ints to fix the build and match other architectures.
      
      Fixes: 91478cef ("tcg: Allocate indirect_base temporaries in a different order")
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NAurelien Jarno <aurelien@aurel32.net>
      Message-Id: <1459522179-6584-1-git-send-email-james.hogan@imgtec.com>
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      2dc7553d
  19. 24 2月, 2016 2 次提交
反馈
建议
客服 返回
顶部