op.c 58.2 KB
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/*
 *  MIPS emulation micro-operations for qemu.
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 *
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 *  Copyright (c) 2004-2005 Jocelyn Mayer
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 *  Copyright (c) 2006 Marius Groeger (FPU operations)
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 *  Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
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 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include "config.h"
#include "exec.h"

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#ifndef CALL_FROM_TB0
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#define CALL_FROM_TB0(func) func()
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#endif
#ifndef CALL_FROM_TB1
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#define CALL_FROM_TB1(func, arg0) func(arg0)
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#endif
#ifndef CALL_FROM_TB1_CONST16
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#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
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#endif
#ifndef CALL_FROM_TB2
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#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
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#endif
#ifndef CALL_FROM_TB2_CONST16
#define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
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        CALL_FROM_TB2(func, arg0, arg1)
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#endif
#ifndef CALL_FROM_TB3
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#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
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#endif
#ifndef CALL_FROM_TB4
#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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        func(arg0, arg1, arg2, arg3)
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#endif

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#define REG 1
#include "op_template.c"
#undef REG
#define REG 2
#include "op_template.c"
#undef REG
#define REG 3
#include "op_template.c"
#undef REG
#define REG 4
#include "op_template.c"
#undef REG
#define REG 5
#include "op_template.c"
#undef REG
#define REG 6
#include "op_template.c"
#undef REG
#define REG 7
#include "op_template.c"
#undef REG
#define REG 8
#include "op_template.c"
#undef REG
#define REG 9
#include "op_template.c"
#undef REG
#define REG 10
#include "op_template.c"
#undef REG
#define REG 11
#include "op_template.c"
#undef REG
#define REG 12
#include "op_template.c"
#undef REG
#define REG 13
#include "op_template.c"
#undef REG
#define REG 14
#include "op_template.c"
#undef REG
#define REG 15
#include "op_template.c"
#undef REG
#define REG 16
#include "op_template.c"
#undef REG
#define REG 17
#include "op_template.c"
#undef REG
#define REG 18
#include "op_template.c"
#undef REG
#define REG 19
#include "op_template.c"
#undef REG
#define REG 20
#include "op_template.c"
#undef REG
#define REG 21
#include "op_template.c"
#undef REG
#define REG 22
#include "op_template.c"
#undef REG
#define REG 23
#include "op_template.c"
#undef REG
#define REG 24
#include "op_template.c"
#undef REG
#define REG 25
#include "op_template.c"
#undef REG
#define REG 26
#include "op_template.c"
#undef REG
#define REG 27
#include "op_template.c"
#undef REG
#define REG 28
#include "op_template.c"
#undef REG
#define REG 29
#include "op_template.c"
#undef REG
#define REG 30
#include "op_template.c"
#undef REG
#define REG 31
#include "op_template.c"
#undef REG

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#define TN
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#include "op_template.c"
#undef TN

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#define FREG 0
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#include "fop_template.c"
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#undef FREG
#define FREG 1
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#include "fop_template.c"
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#undef FREG
#define FREG 2
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#include "fop_template.c"
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#undef FREG
#define FREG 3
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#include "fop_template.c"
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#undef FREG
#define FREG 4
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#include "fop_template.c"
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#undef FREG
#define FREG 5
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#include "fop_template.c"
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#undef FREG
#define FREG 6
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#include "fop_template.c"
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#undef FREG
#define FREG 7
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#include "fop_template.c"
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#undef FREG
#define FREG 8
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#include "fop_template.c"
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#undef FREG
#define FREG 9
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#include "fop_template.c"
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#undef FREG
#define FREG 10
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#include "fop_template.c"
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#undef FREG
#define FREG 11
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#include "fop_template.c"
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#undef FREG
#define FREG 12
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#include "fop_template.c"
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#undef FREG
#define FREG 13
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#include "fop_template.c"
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#undef FREG
#define FREG 14
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#include "fop_template.c"
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#undef FREG
#define FREG 15
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#include "fop_template.c"
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#undef FREG
#define FREG 16
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#include "fop_template.c"
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#undef FREG
#define FREG 17
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#include "fop_template.c"
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#undef FREG
#define FREG 18
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#include "fop_template.c"
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#undef FREG
#define FREG 19
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#include "fop_template.c"
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#undef FREG
#define FREG 20
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#include "fop_template.c"
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#undef FREG
#define FREG 21
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#include "fop_template.c"
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#undef FREG
#define FREG 22
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#include "fop_template.c"
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#undef FREG
#define FREG 23
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#include "fop_template.c"
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#undef FREG
#define FREG 24
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#include "fop_template.c"
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#undef FREG
#define FREG 25
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#include "fop_template.c"
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#undef FREG
#define FREG 26
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#include "fop_template.c"
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#undef FREG
#define FREG 27
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#include "fop_template.c"
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#undef FREG
#define FREG 28
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#include "fop_template.c"
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#undef FREG
#define FREG 29
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#include "fop_template.c"
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#undef FREG
#define FREG 30
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#include "fop_template.c"
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#undef FREG
#define FREG 31
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#include "fop_template.c"
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#undef FREG
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#define FTN
#include "fop_template.c"
#undef FTN

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void op_dup_T0 (void)
{
    T2 = T0;
    RETURN();
}

void op_load_HI (void)
{
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    T0 = env->HI[PARAM1][env->current_tc];
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    RETURN();
}

void op_store_HI (void)
{
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    env->HI[PARAM1][env->current_tc] = T0;
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    RETURN();
}

void op_load_LO (void)
{
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    T0 = env->LO[PARAM1][env->current_tc];
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    RETURN();
}

void op_store_LO (void)
{
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    env->LO[PARAM1][env->current_tc] = T0;
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    RETURN();
}

/* Load and store */
#define MEMSUFFIX _raw
#include "op_mem.c"
#undef MEMSUFFIX
#if !defined(CONFIG_USER_ONLY)
#define MEMSUFFIX _user
#include "op_mem.c"
#undef MEMSUFFIX

#define MEMSUFFIX _kernel
#include "op_mem.c"
#undef MEMSUFFIX
#endif

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/* Addresses computation */
void op_addr_add (void)
{
/* For compatibility with 32-bit code, data reference in user mode
   with Status_UX = 0 should be casted to 32-bit and sign extended.
   See the MIPS64 PRA manual, section 4.10. */
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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    if ((env->hflags & MIPS_HFLAG_UM) &&
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        !(env->CP0_Status & (1 << CP0St_UX)))
        T0 = (int64_t)(int32_t)(T0 + T1);
    else
#endif
        T0 += T1;
    RETURN();
}

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/* Arithmetic */
void op_add (void)
{
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    T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
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    RETURN();
}

void op_addo (void)
{
    target_ulong tmp;

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    tmp = (int32_t)T0;
    T0 = (int32_t)T0 + (int32_t)T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
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        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
}

void op_sub (void)
{
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    T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
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    RETURN();
}

void op_subo (void)
{
    target_ulong tmp;

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    tmp = (int32_t)T0;
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    T0 = (int32_t)T0 - (int32_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
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        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
}

void op_mul (void)
{
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    T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
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    RETURN();
}

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#if HOST_LONG_BITS < 64
void op_div (void)
{
    CALL_FROM_TB0(do_div);
    RETURN();
}
#else
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void op_div (void)
{
    if (T1 != 0) {
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        env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
        env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
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    }
    RETURN();
}
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#endif
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void op_divu (void)
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{
    if (T1 != 0) {
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        env->LO[0][env->current_tc] = (int32_t)((uint32_t)T0 / (uint32_t)T1);
        env->HI[0][env->current_tc] = (int32_t)((uint32_t)T0 % (uint32_t)T1);
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    }
    RETURN();
}

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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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/* Arithmetic */
void op_dadd (void)
{
    T0 += T1;
    RETURN();
}

void op_daddo (void)
{
    target_long tmp;

    tmp = T0;
    T0 += T1;
    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
    RETURN();
}

void op_dsub (void)
{
    T0 -= T1;
    RETURN();
}

void op_dsubo (void)
{
    target_long tmp;

    tmp = T0;
    T0 = (int64_t)T0 - (int64_t)T1;
    if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
    RETURN();
}

void op_dmul (void)
{
    T0 = (int64_t)T0 * (int64_t)T1;
    RETURN();
}

/* Those might call libgcc functions.  */
void op_ddiv (void)
{
    do_ddiv();
    RETURN();
}

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#if TARGET_LONG_BITS > HOST_LONG_BITS
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void op_ddivu (void)
{
    do_ddivu();
    RETURN();
}
#else
void op_ddivu (void)
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{
    if (T1 != 0) {
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        env->LO[0][env->current_tc] = T0 / T1;
        env->HI[0][env->current_tc] = T0 % T1;
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    }
    RETURN();
}
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#endif
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#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
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/* Logical */
void op_and (void)
{
    T0 &= T1;
    RETURN();
}

void op_nor (void)
{
    T0 = ~(T0 | T1);
    RETURN();
}

void op_or (void)
{
    T0 |= T1;
    RETURN();
}

void op_xor (void)
{
    T0 ^= T1;
    RETURN();
}

void op_sll (void)
{
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    T0 = (int32_t)((uint32_t)T0 << T1);
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    RETURN();
}

void op_sra (void)
{
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    T0 = (int32_t)((int32_t)T0 >> T1);
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    RETURN();
}

void op_srl (void)
{
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    T0 = (int32_t)((uint32_t)T0 >> T1);
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    RETURN();
}

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void op_rotr (void)
{
    target_ulong tmp;

    if (T1) {
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       tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
       T0 = (int32_t)((uint32_t)T0 >> T1) | tmp;
    }
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    RETURN();
}

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void op_sllv (void)
{
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    T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
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    RETURN();
}

void op_srav (void)
{
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    T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
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    RETURN();
}

void op_srlv (void)
{
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    T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
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    RETURN();
}

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void op_rotrv (void)
{
    target_ulong tmp;

    T0 &= 0x1F;
    if (T0) {
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       tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
       T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
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    } else
       T0 = T1;
    RETURN();
}

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void op_clo (void)
{
    int n;

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    if (T0 == ~((target_ulong)0)) {
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        T0 = 32;
    } else {
        for (n = 0; n < 32; n++) {
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            if (!(((int32_t)T0) & (1 << 31)))
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                break;
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            T0 <<= 1;
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        }
        T0 = n;
    }
    RETURN();
}

void op_clz (void)
{
    int n;

    if (T0 == 0) {
        T0 = 32;
    } else {
        for (n = 0; n < 32; n++) {
            if (T0 & (1 << 31))
                break;
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            T0 <<= 1;
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        }
        T0 = n;
    }
    RETURN();
}

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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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#if TARGET_LONG_BITS > HOST_LONG_BITS
/* Those might call libgcc functions.  */
void op_dsll (void)
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{
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    CALL_FROM_TB0(do_dsll);
    RETURN();
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}

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void op_dsll32 (void)
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{
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    CALL_FROM_TB0(do_dsll32);
    RETURN();
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}

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void op_dsra (void)
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{
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    CALL_FROM_TB0(do_dsra);
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    RETURN();
}

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void op_dsra32 (void)
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{
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    CALL_FROM_TB0(do_dsra32);
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    RETURN();
}

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void op_dsrl (void)
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{
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    CALL_FROM_TB0(do_dsrl);
    RETURN();
}
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void op_dsrl32 (void)
{
    CALL_FROM_TB0(do_dsrl32);
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    RETURN();
}

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void op_drotr (void)
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{
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    CALL_FROM_TB0(do_drotr);
    RETURN();
}
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void op_drotr32 (void)
{
    CALL_FROM_TB0(do_drotr32);
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    RETURN();
}

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void op_dsllv (void)
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{
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    CALL_FROM_TB0(do_dsllv);
    RETURN();
}
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void op_dsrav (void)
{
    CALL_FROM_TB0(do_dsrav);
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    RETURN();
}

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void op_dsrlv (void)
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{
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    CALL_FROM_TB0(do_dsrlv);
    RETURN();
}
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void op_drotrv (void)
{
    CALL_FROM_TB0(do_drotrv);
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    RETURN();
}
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#else /* TARGET_LONG_BITS > HOST_LONG_BITS */

void op_dsll (void)
{
    T0 = T0 << T1;
    RETURN();
}

void op_dsll32 (void)
{
    T0 = T0 << (T1 + 32);
    RETURN();
}

void op_dsra (void)
{
    T0 = (int64_t)T0 >> T1;
    RETURN();
}

void op_dsra32 (void)
{
    T0 = (int64_t)T0 >> (T1 + 32);
    RETURN();
}

void op_dsrl (void)
{
    T0 = T0 >> T1;
    RETURN();
}

void op_dsrl32 (void)
{
    T0 = T0 >> (T1 + 32);
    RETURN();
}

void op_drotr (void)
{
    target_ulong tmp;

    if (T1) {
       tmp = T0 << (0x40 - T1);
       T0 = (T0 >> T1) | tmp;
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    }
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    RETURN();
}

void op_drotr32 (void)
{
    target_ulong tmp;

    if (T1) {
       tmp = T0 << (0x40 - (32 + T1));
       T0 = (T0 >> (32 + T1)) | tmp;
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    }
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    RETURN();
}

void op_dsllv (void)
{
    T0 = T1 << (T0 & 0x3F);
    RETURN();
}

void op_dsrav (void)
{
    T0 = (int64_t)T1 >> (T0 & 0x3F);
    RETURN();
}

void op_dsrlv (void)
{
    T0 = T1 >> (T0 & 0x3F);
    RETURN();
}

void op_drotrv (void)
{
    target_ulong tmp;

    T0 &= 0x3F;
    if (T0) {
       tmp = T1 << (0x40 - T0);
       T0 = (T1 >> T0) | tmp;
    } else
       T0 = T1;
    RETURN();
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */

void op_dclo (void)
{
    int n;

    if (T0 == ~((target_ulong)0)) {
        T0 = 64;
    } else {
        for (n = 0; n < 64; n++) {
            if (!(T0 & (1ULL << 63)))
                break;
750
            T0 <<= 1;
751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766
        }
        T0 = n;
    }
    RETURN();
}

void op_dclz (void)
{
    int n;

    if (T0 == 0) {
        T0 = 64;
    } else {
        for (n = 0; n < 64; n++) {
            if (T0 & (1ULL << 63))
                break;
767
            T0 <<= 1;
768 769 770 771 772
        }
        T0 = n;
    }
    RETURN();
}
773
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
774 775 776

/* 64 bits arithmetic */
#if TARGET_LONG_BITS > HOST_LONG_BITS
B
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void op_mult (void)
{
    CALL_FROM_TB0(do_mult);
    RETURN();
}

void op_multu (void)
{
    CALL_FROM_TB0(do_multu);
    RETURN();
}

void op_madd (void)
{
    CALL_FROM_TB0(do_madd);
    RETURN();
}

void op_maddu (void)
{
    CALL_FROM_TB0(do_maddu);
    RETURN();
}

void op_msub (void)
{
    CALL_FROM_TB0(do_msub);
    RETURN();
}

void op_msubu (void)
{
    CALL_FROM_TB0(do_msubu);
    RETURN();
}
812 813 814

#else /* TARGET_LONG_BITS > HOST_LONG_BITS */

815
static always_inline uint64_t get_HILO (void)
816
{
817 818
    return ((uint64_t)env->HI[0][env->current_tc] << 32) |
            ((uint64_t)(uint32_t)env->LO[0][env->current_tc]);
819 820
}

821
static always_inline void set_HILO (uint64_t HILO)
822
{
823 824
    env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
    env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
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}

void op_mult (void)
{
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    RETURN();
}

void op_multu (void)
{
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    RETURN();
}

void op_madd (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() + tmp);
    RETURN();
}

void op_maddu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() + tmp);
    RETURN();
}

void op_msub (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() - tmp);
    RETURN();
}

void op_msubu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() - tmp);
    RETURN();
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */

876
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
877 878
void op_dmult (void)
{
879
    CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
880 881 882 883 884
    RETURN();
}

void op_dmultu (void)
{
885
    CALL_FROM_TB4(mulu64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
886 887
    RETURN();
}
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#endif

/* Conditional moves */
void op_movn (void)
{
    if (T1 != 0)
894
        env->gpr[PARAM1][env->current_tc] = T0;
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    RETURN();
}

void op_movz (void)
{
    if (T1 == 0)
901
        env->gpr[PARAM1][env->current_tc] = T0;
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    RETURN();
}

905 906
void op_movf (void)
{
907
    if (!(env->fpu->fcr31 & PARAM1))
908
        T0 = T1;
909 910 911 912 913
    RETURN();
}

void op_movt (void)
{
914
    if (env->fpu->fcr31 & PARAM1)
915
        T0 = T1;
916 917 918
    RETURN();
}

B
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/* Tests */
#define OP_COND(name, cond) \
void glue(op_, name) (void) \
{                           \
    if (cond) {             \
        T0 = 1;             \
    } else {                \
        T0 = 0;             \
    }                       \
    RETURN();               \
}

OP_COND(eq, T0 == T1);
OP_COND(ne, T0 != T1);
933
OP_COND(ge, (target_long)T0 >= (target_long)T1);
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OP_COND(geu, T0 >= T1);
935
OP_COND(lt, (target_long)T0 < (target_long)T1);
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OP_COND(ltu, T0 < T1);
937 938 939 940
OP_COND(gez, (target_long)T0 >= 0);
OP_COND(gtz, (target_long)T0 > 0);
OP_COND(lez, (target_long)T0 <= 0);
OP_COND(ltz, (target_long)T0 < 0);
B
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941

942
/* Branches */
B
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void OPPROTO op_goto_tb0(void)
{
    GOTO_TB(op_goto_tb0, PARAM1, 0);
946
    RETURN();
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}

void OPPROTO op_goto_tb1(void)
{
    GOTO_TB(op_goto_tb1, PARAM1, 1);
952
    RETURN();
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}
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/* Branch to register */
void op_save_breg_target (void)
{
    env->btarget = T2;
959
    RETURN();
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}

void op_restore_breg_target (void)
{
    T2 = env->btarget;
965
    RETURN();
B
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}

void op_breg (void)
{
970
    env->PC[env->current_tc] = T2;
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    RETURN();
}

void op_save_btarget (void)
{
    env->btarget = PARAM1;
    RETURN();
}

980
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
981 982 983 984 985 986 987
void op_save_btarget64 (void)
{
    env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
    RETURN();
}
#endif

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/* Conditional branch */
void op_set_bcond (void)
{
    T2 = T0;
    RETURN();
}

void op_save_bcond (void)
{
    env->bcond = T2;
    RETURN();
}

void op_restore_bcond (void)
{
    T2 = env->bcond;
    RETURN();
}

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void op_jnz_T2 (void)
B
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1008
{
B
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    if (T2)
        GOTO_LABEL_PARAM(1);
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    RETURN();
}

/* CP0 functions */
1015
void op_mfc0_index (void)
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1016
{
T
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    T0 = env->CP0_Index;
1018 1019 1020
    RETURN();
}

1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
void op_mfc0_mvpcontrol (void)
{
    T0 = env->mvp->CP0_MVPControl;
    RETURN();
}

void op_mfc0_mvpconf0 (void)
{
    T0 = env->mvp->CP0_MVPConf0;
    RETURN();
}

void op_mfc0_mvpconf1 (void)
{
    T0 = env->mvp->CP0_MVPConf1;
    RETURN();
}

1039 1040 1041 1042 1043 1044
void op_mfc0_random (void)
{
    CALL_FROM_TB0(do_mfc0_random);
    RETURN();
}

1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086
void op_mfc0_vpecontrol (void)
{
    T0 = env->CP0_VPEControl;
    RETURN();
}

void op_mfc0_vpeconf0 (void)
{
    T0 = env->CP0_VPEConf0;
    RETURN();
}

void op_mfc0_vpeconf1 (void)
{
    T0 = env->CP0_VPEConf1;
    RETURN();
}

void op_mfc0_yqmask (void)
{
    T0 = env->CP0_YQMask;
    RETURN();
}

void op_mfc0_vpeschedule (void)
{
    T0 = env->CP0_VPESchedule;
    RETURN();
}

void op_mfc0_vpeschefback (void)
{
    T0 = env->CP0_VPEScheFBack;
    RETURN();
}

void op_mfc0_vpeopt (void)
{
    T0 = env->CP0_VPEOpt;
    RETURN();
}

1087 1088
void op_mfc0_entrylo0 (void)
{
T
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    T0 = (int32_t)env->CP0_EntryLo0;
1090 1091 1092
    RETURN();
}

1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190
void op_mfc0_tcstatus (void)
{
    T0 = env->CP0_TCStatus[env->current_tc];
    RETURN();
}

void op_mftc0_tcstatus(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCStatus[other_tc];
    RETURN();
}

void op_mfc0_tcbind (void)
{
    T0 = env->CP0_TCBind[env->current_tc];
    RETURN();
}

void op_mftc0_tcbind(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCBind[other_tc];
    RETURN();
}

void op_mfc0_tcrestart (void)
{
    T0 = env->PC[env->current_tc];
    RETURN();
}

void op_mftc0_tcrestart(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->PC[other_tc];
    RETURN();
}

void op_mfc0_tchalt (void)
{
    T0 = env->CP0_TCHalt[env->current_tc];
    RETURN();
}

void op_mftc0_tchalt(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCHalt[other_tc];
    RETURN();
}

void op_mfc0_tccontext (void)
{
    T0 = env->CP0_TCContext[env->current_tc];
    RETURN();
}

void op_mftc0_tccontext(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCContext[other_tc];
    RETURN();
}

void op_mfc0_tcschedule (void)
{
    T0 = env->CP0_TCSchedule[env->current_tc];
    RETURN();
}

void op_mftc0_tcschedule(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCSchedule[other_tc];
    RETURN();
}

void op_mfc0_tcschefback (void)
{
    T0 = env->CP0_TCScheFBack[env->current_tc];
    RETURN();
}

void op_mftc0_tcschefback(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCScheFBack[other_tc];
    RETURN();
}

1191 1192
void op_mfc0_entrylo1 (void)
{
T
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1193
    T0 = (int32_t)env->CP0_EntryLo1;
1194 1195 1196 1197 1198
    RETURN();
}

void op_mfc0_context (void)
{
T
ths 已提交
1199
    T0 = (int32_t)env->CP0_Context;
1200 1201 1202 1203 1204
    RETURN();
}

void op_mfc0_pagemask (void)
{
T
ths 已提交
1205
    T0 = env->CP0_PageMask;
1206 1207 1208
    RETURN();
}

1209 1210
void op_mfc0_pagegrain (void)
{
T
ths 已提交
1211
    T0 = env->CP0_PageGrain;
1212 1213 1214
    RETURN();
}

1215 1216
void op_mfc0_wired (void)
{
T
ths 已提交
1217
    T0 = env->CP0_Wired;
1218 1219 1220
    RETURN();
}

1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250
void op_mfc0_srsconf0 (void)
{
    T0 = env->CP0_SRSConf0;
    RETURN();
}

void op_mfc0_srsconf1 (void)
{
    T0 = env->CP0_SRSConf1;
    RETURN();
}

void op_mfc0_srsconf2 (void)
{
    T0 = env->CP0_SRSConf2;
    RETURN();
}

void op_mfc0_srsconf3 (void)
{
    T0 = env->CP0_SRSConf3;
    RETURN();
}

void op_mfc0_srsconf4 (void)
{
    T0 = env->CP0_SRSConf4;
    RETURN();
}

1251 1252
void op_mfc0_hwrena (void)
{
T
ths 已提交
1253
    T0 = env->CP0_HWREna;
1254 1255 1256
    RETURN();
}

1257 1258
void op_mfc0_badvaddr (void)
{
T
ths 已提交
1259
    T0 = (int32_t)env->CP0_BadVAddr;
1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270
    RETURN();
}

void op_mfc0_count (void)
{
    CALL_FROM_TB0(do_mfc0_count);
    RETURN();
}

void op_mfc0_entryhi (void)
{
T
ths 已提交
1271
    T0 = (int32_t)env->CP0_EntryHi;
1272 1273 1274
    RETURN();
}

1275 1276 1277 1278 1279 1280 1281 1282
void op_mftc0_entryhi(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
    RETURN();
}

1283 1284
void op_mfc0_compare (void)
{
T
ths 已提交
1285
    T0 = env->CP0_Compare;
1286 1287 1288 1289 1290
    RETURN();
}

void op_mfc0_status (void)
{
T
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1291
    T0 = env->CP0_Status;
1292 1293 1294
    RETURN();
}

1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306
void op_mftc0_status(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
    uint32_t tcstatus = env->CP0_TCStatus[other_tc];

    T0 = env->CP0_Status & ~0xf1000018;
    T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
    T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
    T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_R0);
    RETURN();
}

1307 1308
void op_mfc0_intctl (void)
{
T
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1309
    T0 = env->CP0_IntCtl;
1310 1311 1312 1313 1314
    RETURN();
}

void op_mfc0_srsctl (void)
{
T
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1315 1316 1317 1318 1319 1320 1321
    T0 = env->CP0_SRSCtl;
    RETURN();
}

void op_mfc0_srsmap (void)
{
    T0 = env->CP0_SRSMap;
1322 1323 1324
    RETURN();
}

1325 1326
void op_mfc0_cause (void)
{
T
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1327
    T0 = env->CP0_Cause;
1328 1329 1330 1331 1332
    RETURN();
}

void op_mfc0_epc (void)
{
T
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1333
    T0 = (int32_t)env->CP0_EPC;
1334 1335 1336 1337 1338
    RETURN();
}

void op_mfc0_prid (void)
{
T
ths 已提交
1339
    T0 = env->CP0_PRid;
1340 1341 1342
    RETURN();
}

1343 1344
void op_mfc0_ebase (void)
{
1345
    T0 = env->CP0_EBase;
1346 1347 1348
    RETURN();
}

1349 1350
void op_mfc0_config0 (void)
{
T
ths 已提交
1351
    T0 = env->CP0_Config0;
1352 1353 1354 1355 1356
    RETURN();
}

void op_mfc0_config1 (void)
{
T
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1357
    T0 = env->CP0_Config1;
1358 1359 1360
    RETURN();
}

1361 1362
void op_mfc0_config2 (void)
{
T
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1363
    T0 = env->CP0_Config2;
1364 1365 1366 1367 1368
    RETURN();
}

void op_mfc0_config3 (void)
{
T
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1369
    T0 = env->CP0_Config3;
1370 1371 1372
    RETURN();
}

1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384
void op_mfc0_config6 (void)
{
    T0 = env->CP0_Config6;
    RETURN();
}

void op_mfc0_config7 (void)
{
    T0 = env->CP0_Config7;
    RETURN();
}

1385 1386
void op_mfc0_lladdr (void)
{
T
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1387
    T0 = (int32_t)env->CP0_LLAddr >> 4;
1388 1389 1390
    RETURN();
}

1391
void op_mfc0_watchlo (void)
1392
{
1393
    T0 = (int32_t)env->CP0_WatchLo[PARAM1];
1394 1395 1396
    RETURN();
}

1397
void op_mfc0_watchhi (void)
1398
{
1399
    T0 = env->CP0_WatchHi[PARAM1];
1400 1401 1402
    RETURN();
}

1403 1404
void op_mfc0_xcontext (void)
{
T
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1405
    T0 = (int32_t)env->CP0_XContext;
1406 1407 1408 1409 1410 1411 1412 1413 1414
    RETURN();
}

void op_mfc0_framemask (void)
{
    T0 = env->CP0_Framemask;
    RETURN();
}

1415 1416
void op_mfc0_debug (void)
{
T
ths 已提交
1417
    T0 = env->CP0_Debug;
1418 1419 1420 1421 1422
    if (env->hflags & MIPS_HFLAG_DM)
        T0 |= 1 << CP0DB_DM;
    RETURN();
}

1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433
void op_mftc0_debug(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    /* XXX: Might be wrong, check with EJTAG spec. */
    T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
         (env->CP0_Debug_tcstatus[other_tc] &
          ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
    RETURN();
}

1434 1435
void op_mfc0_depc (void)
{
T
ths 已提交
1436
    T0 = (int32_t)env->CP0_DEPC;
1437 1438 1439
    RETURN();
}

1440 1441
void op_mfc0_performance0 (void)
{
T
ths 已提交
1442
    T0 = env->CP0_Performance0;
1443 1444 1445
    RETURN();
}

1446 1447
void op_mfc0_taglo (void)
{
T
ths 已提交
1448
    T0 = env->CP0_TagLo;
1449 1450 1451 1452 1453
    RETURN();
}

void op_mfc0_datalo (void)
{
T
ths 已提交
1454
    T0 = env->CP0_DataLo;
1455 1456 1457
    RETURN();
}

1458 1459
void op_mfc0_taghi (void)
{
T
ths 已提交
1460
    T0 = env->CP0_TagHi;
1461 1462 1463 1464 1465
    RETURN();
}

void op_mfc0_datahi (void)
{
T
ths 已提交
1466
    T0 = env->CP0_DataHi;
1467 1468 1469
    RETURN();
}

1470 1471
void op_mfc0_errorepc (void)
{
T
ths 已提交
1472
    T0 = (int32_t)env->CP0_ErrorEPC;
1473 1474 1475 1476 1477
    RETURN();
}

void op_mfc0_desave (void)
{
T
ths 已提交
1478
    T0 = env->CP0_DESAVE;
B
bellard 已提交
1479 1480 1481
    RETURN();
}

1482
void op_mtc0_index (void)
B
bellard 已提交
1483
{
T
ths 已提交
1484 1485 1486 1487 1488 1489 1490 1491
    int num = 1;
    unsigned int tmp = env->tlb->nb_tlb;

    do {
        tmp >>= 1;
        num <<= 1;
    } while (tmp);
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589
    RETURN();
}

void op_mtc0_mvpcontrol (void)
{
    uint32_t mask = 0;
    uint32_t newval;

    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
        mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
                (1 << CP0MVPCo_EVP);
    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (1 << CP0MVPCo_STLB);
    newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);

    // TODO: Enable/disable shared TLB, enable/disable VPEs.

    env->mvp->CP0_MVPControl = newval;
    RETURN();
}

void op_mtc0_vpecontrol (void)
{
    uint32_t mask;
    uint32_t newval;

    mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
           (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
    newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);

    /* Yield scheduler intercept not implemented. */
    /* Gating storage scheduler intercept not implemented. */

    // TODO: Enable/disable TCs.

    env->CP0_VPEControl = newval;
    RETURN();
}

void op_mtc0_vpeconf0 (void)
{
    uint32_t mask = 0;
    uint32_t newval;

    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
        if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
            mask |= (0xff << CP0VPEC0_XTC);
        mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
    }
    newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);

    // TODO: TC exclusive handling due to ERL/EXL.

    env->CP0_VPEConf0 = newval;
    RETURN();
}

void op_mtc0_vpeconf1 (void)
{
    uint32_t mask = 0;
    uint32_t newval;

    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
                (0xff << CP0VPEC1_NCP1);
    newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);

    /* UDI not implemented. */
    /* CP2 not implemented. */

    // TODO: Handle FPU (CP1) binding.

    env->CP0_VPEConf1 = newval;
    RETURN();
}

void op_mtc0_yqmask (void)
{
    /* Yield qualifier inputs not implemented. */
    env->CP0_YQMask = 0x00000000;
    RETURN();
}

void op_mtc0_vpeschedule (void)
{
    env->CP0_VPESchedule = T0;
    RETURN();
}

void op_mtc0_vpeschefback (void)
{
    env->CP0_VPEScheFBack = T0;
    RETURN();
}

void op_mtc0_vpeopt (void)
{
    env->CP0_VPEOpt = T0 & 0x0000ffff;
1590 1591 1592 1593 1594
    RETURN();
}

void op_mtc0_entrylo0 (void)
{
1595 1596
    /* Large physaddr not implemented */
    /* 1k pages not implemented */
1597
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1598 1599 1600
    RETURN();
}

1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729
void op_mtc0_tcstatus (void)
{
    uint32_t mask = env->CP0_TCStatus_rw_bitmask;
    uint32_t newval;

    newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);

    // TODO: Sync with CP0_Status.

    env->CP0_TCStatus[env->current_tc] = newval;
    RETURN();
}

void op_mttc0_tcstatus (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    // TODO: Sync with CP0_Status.

    env->CP0_TCStatus[other_tc] = T0;
    RETURN();
}

void op_mtc0_tcbind (void)
{
    uint32_t mask = (1 << CP0TCBd_TBE);
    uint32_t newval;

    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (1 << CP0TCBd_CurVPE);
    newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
    env->CP0_TCBind[env->current_tc] = newval;
    RETURN();
}

void op_mttc0_tcbind (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
    uint32_t mask = (1 << CP0TCBd_TBE);
    uint32_t newval;

    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
        mask |= (1 << CP0TCBd_CurVPE);
    newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
    env->CP0_TCBind[other_tc] = newval;
    RETURN();
}

void op_mtc0_tcrestart (void)
{
    env->PC[env->current_tc] = T0;
    env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
    env->CP0_LLAddr = 0ULL;
    /* MIPS16 not implemented. */
    RETURN();
}

void op_mttc0_tcrestart (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->PC[other_tc] = T0;
    env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
    env->CP0_LLAddr = 0ULL;
    /* MIPS16 not implemented. */
    RETURN();
}

void op_mtc0_tchalt (void)
{
    env->CP0_TCHalt[env->current_tc] = T0 & 0x1;

    // TODO: Halt TC / Restart (if allocated+active) TC.

    RETURN();
}

void op_mttc0_tchalt (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    // TODO: Halt TC / Restart (if allocated+active) TC.

    env->CP0_TCHalt[other_tc] = T0;
    RETURN();
}

void op_mtc0_tccontext (void)
{
    env->CP0_TCContext[env->current_tc] = T0;
    RETURN();
}

void op_mttc0_tccontext (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->CP0_TCContext[other_tc] = T0;
    RETURN();
}

void op_mtc0_tcschedule (void)
{
    env->CP0_TCSchedule[env->current_tc] = T0;
    RETURN();
}

void op_mttc0_tcschedule (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->CP0_TCSchedule[other_tc] = T0;
    RETURN();
}

void op_mtc0_tcschefback (void)
{
    env->CP0_TCScheFBack[env->current_tc] = T0;
    RETURN();
}

void op_mttc0_tcschefback (void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->CP0_TCScheFBack[other_tc] = T0;
    RETURN();
}

1730 1731
void op_mtc0_entrylo1 (void)
{
1732 1733
    /* Large physaddr not implemented */
    /* 1k pages not implemented */
1734
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1735 1736 1737 1738 1739
    RETURN();
}

void op_mtc0_context (void)
{
1740
    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1741 1742 1743 1744 1745
    RETURN();
}

void op_mtc0_pagemask (void)
{
1746
    /* 1k pages not implemented */
T
ths 已提交
1747
    env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1748 1749 1750 1751 1752 1753 1754 1755 1756
    RETURN();
}

void op_mtc0_pagegrain (void)
{
    /* SmartMIPS not implemented */
    /* Large physaddr not implemented */
    /* 1k pages not implemented */
    env->CP0_PageGrain = 0;
1757 1758 1759 1760 1761
    RETURN();
}

void op_mtc0_wired (void)
{
1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792
    env->CP0_Wired = T0 % env->tlb->nb_tlb;
    RETURN();
}

void op_mtc0_srsconf0 (void)
{
    env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
    RETURN();
}

void op_mtc0_srsconf1 (void)
{
    env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
    RETURN();
}

void op_mtc0_srsconf2 (void)
{
    env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
    RETURN();
}

void op_mtc0_srsconf3 (void)
{
    env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
    RETURN();
}

void op_mtc0_srsconf4 (void)
{
    env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
1793 1794 1795 1796 1797 1798
    RETURN();
}

void op_mtc0_hwrena (void)
{
    env->CP0_HWREna = T0 & 0x0000000F;
1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809
    RETURN();
}

void op_mtc0_count (void)
{
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
    RETURN();
}

void op_mtc0_entryhi (void)
{
T
ths 已提交
1810
    target_ulong old, val;
1811

1812
    /* 1k pages not implemented */
1813
    val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1814
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
T
ths 已提交
1815
    val &= env->SEGMask;
1816
#endif
1817 1818
    old = env->CP0_EntryHi;
    env->CP0_EntryHi = val;
1819 1820 1821 1822
    if (env->CP0_Config3 & (1 << CP0C3_MT)) {
        uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
        env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
    }
1823 1824 1825 1826 1827 1828
    /* If the ASID changes, flush qemu's TLB.  */
    if ((old & 0xFF) != (val & 0xFF))
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
    RETURN();
}

1829 1830 1831 1832 1833 1834 1835 1836 1837
void op_mttc0_entryhi(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
    env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
    RETURN();
}

1838 1839 1840 1841 1842 1843 1844 1845
void op_mtc0_compare (void)
{
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
    RETURN();
}

void op_mtc0_status (void)
{
1846
    uint32_t val, old;
1847
    uint32_t mask = env->CP0_Status_rw_bitmask;
1848

1849
    val = T0 & mask;
1850
    old = env->CP0_Status;
1851
    env->CP0_Status = (env->CP0_Status & ~mask) | val;
1852
    CALL_FROM_TB1(compute_hflags, env);
1853 1854
    if (loglevel & CPU_LOG_EXEC)
        CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1855
    CALL_FROM_TB1(cpu_mips_update_irq, env);
1856 1857 1858
    RETURN();
}

1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871
void op_mttc0_status(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
    uint32_t tcstatus = env->CP0_TCStatus[other_tc];

    env->CP0_Status = T0 & ~0xf1000018;
    tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));
    tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
    tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_R0)) << (CP0TCSt_TKSU - CP0St_R0));
    env->CP0_TCStatus[other_tc] = tcstatus;
    RETURN();
}

1872 1873
void op_mtc0_intctl (void)
{
1874 1875
    /* vectored interrupts not implemented, no performance counters. */
    env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);
1876 1877 1878 1879 1880
    RETURN();
}

void op_mtc0_srsctl (void)
{
1881 1882
    uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
    env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);
1883 1884 1885
    RETURN();
}

T
ths 已提交
1886 1887
void op_mtc0_srsmap (void)
{
1888
    env->CP0_SRSMap = T0;
T
ths 已提交
1889 1890 1891
    RETURN();
}

1892 1893
void op_mtc0_cause (void)
{
1894
    uint32_t mask = 0x00C00300;
1895
    uint32_t old = env->CP0_Cause;
1896

1897
    if (env->insn_flags & ISA_MIPS32R2)
1898 1899
        mask |= 1 << CP0Ca_DC;

1900
    env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
1901

1902 1903 1904 1905 1906 1907 1908
    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
        if (env->CP0_Cause & (1 << CP0Ca_DC))
            CALL_FROM_TB1(cpu_mips_stop_count, env);
        else
            CALL_FROM_TB1(cpu_mips_start_count, env);
    }

1909 1910 1911 1912
    /* Handle the software interrupt as an hardware one, as they
       are very similar */
    if (T0 & CP0Ca_IP_mask) {
        CALL_FROM_TB1(cpu_mips_update_irq, env);
1913 1914 1915 1916 1917 1918
    }
    RETURN();
}

void op_mtc0_epc (void)
{
1919
    env->CP0_EPC = T0;
1920 1921 1922
    RETURN();
}

1923 1924 1925 1926
void op_mtc0_ebase (void)
{
    /* vectored interrupts not implemented */
    /* Multi-CPU not implemented */
1927
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1928 1929 1930
    RETURN();
}

1931 1932
void op_mtc0_config0 (void)
{
1933
    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
1934 1935 1936
    RETURN();
}

1937 1938 1939 1940 1941 1942 1943
void op_mtc0_config2 (void)
{
    /* tertiary/secondary caches not implemented */
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
    RETURN();
}

1944
void op_mtc0_watchlo (void)
1945
{
T
ths 已提交
1946 1947
    /* Watch exceptions for instructions, data loads, data stores
       not implemented. */
1948
    env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
1949 1950 1951
    RETURN();
}

1952
void op_mtc0_watchhi (void)
1953
{
1954 1955
    env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
    env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
1956 1957 1958
    RETURN();
}

1959 1960 1961 1962 1963 1964 1965
void op_mtc0_xcontext (void)
{
    target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
    env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
    RETURN();
}

1966 1967 1968 1969 1970 1971
void op_mtc0_framemask (void)
{
    env->CP0_Framemask = T0; /* XXX */
    RETURN();
}

1972 1973 1974 1975 1976 1977 1978 1979 1980 1981
void op_mtc0_debug (void)
{
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
    if (T0 & (1 << CP0DB_DM))
        env->hflags |= MIPS_HFLAG_DM;
    else
        env->hflags &= ~MIPS_HFLAG_DM;
    RETURN();
}

1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992
void op_mttc0_debug(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    /* XXX: Might be wrong, check with EJTAG spec. */
    env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
    env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
                     (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
    RETURN();
}

1993 1994
void op_mtc0_depc (void)
{
1995
    env->CP0_DEPC = T0;
1996 1997 1998
    RETURN();
}

1999 2000 2001 2002 2003 2004
void op_mtc0_performance0 (void)
{
    env->CP0_Performance0 = T0; /* XXX */
    RETURN();
}

2005 2006
void op_mtc0_taglo (void)
{
T
ths 已提交
2007
    env->CP0_TagLo = T0 & 0xFFFFFCF6;
2008 2009 2010
    RETURN();
}

2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028
void op_mtc0_datalo (void)
{
    env->CP0_DataLo = T0; /* XXX */
    RETURN();
}

void op_mtc0_taghi (void)
{
    env->CP0_TagHi = T0; /* XXX */
    RETURN();
}

void op_mtc0_datahi (void)
{
    env->CP0_DataHi = T0; /* XXX */
    RETURN();
}

2029 2030
void op_mtc0_errorepc (void)
{
2031
    env->CP0_ErrorEPC = T0;
2032 2033 2034 2035 2036 2037
    RETURN();
}

void op_mtc0_desave (void)
{
    env->CP0_DESAVE = T0;
B
bellard 已提交
2038 2039 2040
    RETURN();
}

2041
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
2042
void op_dmfc0_yqmask (void)
2043
{
2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056
    T0 = env->CP0_YQMask;
    RETURN();
}

void op_dmfc0_vpeschedule (void)
{
    T0 = env->CP0_VPESchedule;
    RETURN();
}

void op_dmfc0_vpeschefback (void)
{
    T0 = env->CP0_VPEScheFBack;
2057 2058 2059
    RETURN();
}

T
ths 已提交
2060 2061 2062 2063 2064 2065
void op_dmfc0_entrylo0 (void)
{
    T0 = env->CP0_EntryLo0;
    RETURN();
}

2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
void op_dmfc0_tcrestart (void)
{
    T0 = env->PC[env->current_tc];
    RETURN();
}

void op_dmfc0_tchalt (void)
{
    T0 = env->CP0_TCHalt[env->current_tc];
    RETURN();
}

void op_dmfc0_tccontext (void)
{
    T0 = env->CP0_TCContext[env->current_tc];
    RETURN();
}

void op_dmfc0_tcschedule (void)
{
    T0 = env->CP0_TCSchedule[env->current_tc];
    RETURN();
}

void op_dmfc0_tcschefback (void)
{
    T0 = env->CP0_TCScheFBack[env->current_tc];
    RETURN();
}

T
ths 已提交
2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131
void op_dmfc0_entrylo1 (void)
{
    T0 = env->CP0_EntryLo1;
    RETURN();
}

void op_dmfc0_context (void)
{
    T0 = env->CP0_Context;
    RETURN();
}

void op_dmfc0_badvaddr (void)
{
    T0 = env->CP0_BadVAddr;
    RETURN();
}

void op_dmfc0_entryhi (void)
{
    T0 = env->CP0_EntryHi;
    RETURN();
}

void op_dmfc0_epc (void)
{
    T0 = env->CP0_EPC;
    RETURN();
}

void op_dmfc0_lladdr (void)
{
    T0 = env->CP0_LLAddr >> 4;
    RETURN();
}

2132
void op_dmfc0_watchlo (void)
T
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2133
{
2134
    T0 = env->CP0_WatchLo[PARAM1];
T
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2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154
    RETURN();
}

void op_dmfc0_xcontext (void)
{
    T0 = env->CP0_XContext;
    RETURN();
}

void op_dmfc0_depc (void)
{
    T0 = env->CP0_DEPC;
    RETURN();
}

void op_dmfc0_errorepc (void)
{
    T0 = env->CP0_ErrorEPC;
    RETURN();
}
2155
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
T
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2156

2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307
/* MIPS MT functions */
void op_mftgpr(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->gpr[PARAM1][other_tc];
    RETURN();
}

void op_mftlo(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->LO[PARAM1][other_tc];
    RETURN();
}

void op_mfthi(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->HI[PARAM1][other_tc];
    RETURN();
}

void op_mftacx(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->ACX[PARAM1][other_tc];
    RETURN();
}

void op_mftdsp(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->DSPControl[other_tc];
    RETURN();
}

void op_mttgpr(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->gpr[PARAM1][other_tc];
    RETURN();
}

void op_mttlo(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->LO[PARAM1][other_tc];
    RETURN();
}

void op_mtthi(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->HI[PARAM1][other_tc];
    RETURN();
}

void op_mttacx(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->ACX[PARAM1][other_tc];
    RETURN();
}

void op_mttdsp(void)
{
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->DSPControl[other_tc];
    RETURN();
}


void op_dmt(void)
{
    // TODO
    T0 = 0;
    // rt = T0
    RETURN();
}

void op_emt(void)
{
    // TODO
    T0 = 0;
    // rt = T0
    RETURN();
}

void op_dvpe(void)
{
    // TODO
    T0 = 0;
    // rt = T0
    RETURN();
}

void op_evpe(void)
{
    // TODO
    T0 = 0;
    // rt = T0
    RETURN();
}

void op_fork(void)
{
    // T0 = rt, T1 = rs
    T0 = 0;
    // TODO: store to TC register
    RETURN();
}

void op_yield(void)
{
    if (T0 < 0) {
        /* No scheduling policy implemented. */
        if (T0 != -2) {
            if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
                env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
                env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
                env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
                CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
            }
        }
    } else if (T0 == 0) {
	if (0 /* TODO: TC underflow */) {
            env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
            CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
        } else {
            // TODO: Deallocate TC
        }
    } else if (T0 > 0) {
        /* Yield qualifier inputs not implemented. */
        env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
        env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
        CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
    }
    T0 = env->CP0_YQMask;
    RETURN();
}

2308
/* CP1 functions */
B
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2309 2310 2311 2312 2313 2314
#if 0
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
#else
# define DEBUG_FPU_STATE() do { } while(0)
#endif

2315 2316
void op_cfc1 (void)
{
2317
    CALL_FROM_TB1(do_cfc1, PARAM1);
2318 2319 2320 2321 2322 2323
    DEBUG_FPU_STATE();
    RETURN();
}

void op_ctc1 (void)
{
2324
    CALL_FROM_TB1(do_ctc1, PARAM1);
B
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2325 2326 2327 2328 2329 2330
    DEBUG_FPU_STATE();
    RETURN();
}

void op_mfc1 (void)
{
2331
    T0 = (int32_t)WT0;
B
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2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342
    DEBUG_FPU_STATE();
    RETURN();
}

void op_mtc1 (void)
{
    WT0 = T0;
    DEBUG_FPU_STATE();
    RETURN();
}

2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358
void op_dmfc1 (void)
{
    T0 = DT0;
    DEBUG_FPU_STATE();
    RETURN();
}

void op_dmtc1 (void)
{
    DT0 = T0;
    DEBUG_FPU_STATE();
    RETURN();
}

void op_mfhc1 (void)
{
2359
    T0 = (int32_t)WTH0;
2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370
    DEBUG_FPU_STATE();
    RETURN();
}

void op_mthc1 (void)
{
    WTH0 = T0;
    DEBUG_FPU_STATE();
    RETURN();
}

B
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/* Float support.
   Single precition routines have a "s" suffix, double precision a
2373 2374
   "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
   paired single lowwer "pl", paired single upper "pu".  */
B
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2375 2376 2377

#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)

2378 2379
FLOAT_OP(cvtd, s)
{
2380
    CALL_FROM_TB0(do_float_cvtd_s);
2381 2382 2383
    DEBUG_FPU_STATE();
    RETURN();
}
B
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2384 2385
FLOAT_OP(cvtd, w)
{
2386
    CALL_FROM_TB0(do_float_cvtd_w);
2387 2388 2389 2390 2391
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvtd, l)
{
2392
    CALL_FROM_TB0(do_float_cvtd_l);
2393 2394 2395 2396 2397
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvtl, d)
{
2398
    CALL_FROM_TB0(do_float_cvtl_d);
2399 2400 2401 2402 2403
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvtl, s)
{
2404
    CALL_FROM_TB0(do_float_cvtl_s);
2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvtps, s)
{
    WT2 = WT0;
    WTH2 = WT1;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvtps, pw)
{
2417
    CALL_FROM_TB0(do_float_cvtps_pw);
2418 2419 2420 2421 2422
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvtpw, ps)
{
2423
    CALL_FROM_TB0(do_float_cvtpw_ps);
B
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2424 2425 2426
    DEBUG_FPU_STATE();
    RETURN();
}
2427 2428
FLOAT_OP(cvts, d)
{
2429
    CALL_FROM_TB0(do_float_cvts_d);
2430 2431 2432
    DEBUG_FPU_STATE();
    RETURN();
}
B
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2433 2434
FLOAT_OP(cvts, w)
{
2435
    CALL_FROM_TB0(do_float_cvts_w);
2436 2437 2438 2439 2440
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvts, l)
{
2441
    CALL_FROM_TB0(do_float_cvts_l);
2442 2443 2444 2445 2446
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvts, pl)
{
2447
    CALL_FROM_TB0(do_float_cvts_pl);
2448 2449 2450 2451 2452
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvts, pu)
{
2453
    CALL_FROM_TB0(do_float_cvts_pu);
B
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    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvtw, s)
{
2459
    CALL_FROM_TB0(do_float_cvtw_s);
B
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2460 2461 2462 2463 2464
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(cvtw, d)
{
2465
    CALL_FROM_TB0(do_float_cvtw_d);
2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490
    DEBUG_FPU_STATE();
    RETURN();
}

FLOAT_OP(pll, ps)
{
    DT2 = ((uint64_t)WT0 << 32) | WT1;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(plu, ps)
{
    DT2 = ((uint64_t)WT0 << 32) | WTH1;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(pul, ps)
{
    DT2 = ((uint64_t)WTH0 << 32) | WT1;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(puu, ps)
{
    DT2 = ((uint64_t)WTH0 << 32) | WTH1;
B
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    DEBUG_FPU_STATE();
    RETURN();
}

2495 2496 2497 2498 2499 2500
#define FLOAT_ROUNDOP(op, ttype, stype)                    \
FLOAT_OP(op ## ttype, stype)                               \
{                                                          \
    CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \
    DEBUG_FPU_STATE();                                     \
    RETURN();                                              \
B
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}

2503 2504 2505 2506
FLOAT_ROUNDOP(round, l, d)
FLOAT_ROUNDOP(round, l, s)
FLOAT_ROUNDOP(round, w, d)
FLOAT_ROUNDOP(round, w, s)
B
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2508 2509 2510 2511
FLOAT_ROUNDOP(trunc, l, d)
FLOAT_ROUNDOP(trunc, l, s)
FLOAT_ROUNDOP(trunc, w, d)
FLOAT_ROUNDOP(trunc, w, s)
B
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2513 2514 2515 2516 2517 2518 2519 2520 2521 2522
FLOAT_ROUNDOP(ceil, l, d)
FLOAT_ROUNDOP(ceil, l, s)
FLOAT_ROUNDOP(ceil, w, d)
FLOAT_ROUNDOP(ceil, w, s)

FLOAT_ROUNDOP(floor, l, d)
FLOAT_ROUNDOP(floor, l, s)
FLOAT_ROUNDOP(floor, w, d)
FLOAT_ROUNDOP(floor, w, s)
#undef FLOAR_ROUNDOP
B
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2523

2524 2525
FLOAT_OP(movf, d)
{
2526
    if (!(env->fpu->fcr31 & PARAM1))
2527 2528 2529 2530 2531 2532
        DT2 = DT0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movf, s)
{
2533
    if (!(env->fpu->fcr31 & PARAM1))
2534 2535 2536 2537 2538 2539
        WT2 = WT0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movf, ps)
{
2540
    if (!(env->fpu->fcr31 & PARAM1)) {
2541 2542 2543 2544 2545 2546 2547 2548
        WT2 = WT0;
        WTH2 = WTH0;
    }
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movt, d)
{
2549
    if (env->fpu->fcr31 & PARAM1)
2550 2551 2552 2553 2554 2555
        DT2 = DT0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movt, s)
{
2556
    if (env->fpu->fcr31 & PARAM1)
2557 2558 2559 2560 2561 2562
        WT2 = WT0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movt, ps)
{
2563
    if (env->fpu->fcr31 & PARAM1) {
2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616
        WT2 = WT0;
        WTH2 = WTH0;
    }
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movz, d)
{
    if (!T0)
        DT2 = DT0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movz, s)
{
    if (!T0)
        WT2 = WT0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movz, ps)
{
    if (!T0) {
        WT2 = WT0;
        WTH2 = WTH0;
    }
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movn, d)
{
    if (T0)
        DT2 = DT0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movn, s)
{
    if (T0)
        WT2 = WT0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(movn, ps)
{
    if (T0) {
        WT2 = WT0;
        WTH2 = WTH0;
    }
    DEBUG_FPU_STATE();
    RETURN();
}

T
ths 已提交
2617 2618
/* operations calling helpers, for s, d and ps */
#define FLOAT_HOP(name) \
B
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2619 2620
FLOAT_OP(name, d)         \
{                         \
2621
    CALL_FROM_TB0(do_float_ ## name ## _d);  \
B
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2622
    DEBUG_FPU_STATE();    \
2623
    RETURN();             \
B
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2624 2625 2626
}                         \
FLOAT_OP(name, s)         \
{                         \
2627
    CALL_FROM_TB0(do_float_ ## name ## _s);  \
2628
    DEBUG_FPU_STATE();    \
2629
    RETURN();             \
2630 2631 2632
}                         \
FLOAT_OP(name, ps)        \
{                         \
2633
    CALL_FROM_TB0(do_float_ ## name ## _ps); \
B
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2634
    DEBUG_FPU_STATE();    \
2635
    RETURN();             \
B
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2636
}
T
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2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663
FLOAT_HOP(add)
FLOAT_HOP(sub)
FLOAT_HOP(mul)
FLOAT_HOP(div)
FLOAT_HOP(recip2)
FLOAT_HOP(rsqrt2)
FLOAT_HOP(rsqrt1)
FLOAT_HOP(recip1)
#undef FLOAT_HOP

/* operations calling helpers, for s and d */
#define FLOAT_HOP(name)   \
FLOAT_OP(name, d)         \
{                         \
    CALL_FROM_TB0(do_float_ ## name ## _d);  \
    DEBUG_FPU_STATE();    \
    RETURN();             \
}                         \
FLOAT_OP(name, s)         \
{                         \
    CALL_FROM_TB0(do_float_ ## name ## _s);  \
    DEBUG_FPU_STATE();    \
    RETURN();             \
}
FLOAT_HOP(rsqrt)
FLOAT_HOP(recip)
#undef FLOAT_HOP
B
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2664

T
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2665 2666 2667 2668 2669 2670 2671
/* operations calling helpers, for ps */
#define FLOAT_HOP(name)   \
FLOAT_OP(name, ps)        \
{                         \
    CALL_FROM_TB0(do_float_ ## name ## _ps); \
    DEBUG_FPU_STATE();    \
    RETURN();             \
2672
}
T
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2673 2674 2675
FLOAT_HOP(addr)
FLOAT_HOP(mulr)
#undef FLOAT_HOP
2676

2677 2678 2679 2680
/* ternary operations */
#define FLOAT_TERNOP(name1, name2) \
FLOAT_OP(name1 ## name2, d)        \
{                                  \
2681 2682
    FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status);    \
    FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status);    \
2683
    DEBUG_FPU_STATE();             \
2684
    RETURN();                      \
2685 2686 2687
}                                  \
FLOAT_OP(name1 ## name2, s)        \
{                                  \
2688 2689
    FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
    FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2690
    DEBUG_FPU_STATE();             \
2691
    RETURN();                      \
2692 2693 2694
}                                  \
FLOAT_OP(name1 ## name2, ps)       \
{                                  \
2695 2696 2697 2698
    FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
    FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
    FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
    FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2699
    DEBUG_FPU_STATE();             \
2700
    RETURN();                      \
2701 2702 2703 2704 2705
}
FLOAT_TERNOP(mul, add)
FLOAT_TERNOP(mul, sub)
#undef FLOAT_TERNOP

2706 2707 2708 2709
/* negated ternary operations */
#define FLOAT_NTERNOP(name1, name2) \
FLOAT_OP(n ## name1 ## name2, d)    \
{                                   \
2710 2711
    FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status);    \
    FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status);    \
2712 2713 2714 2715 2716 2717
    FDT2 ^= 1ULL << 63;             \
    DEBUG_FPU_STATE();              \
    RETURN();                       \
}                                   \
FLOAT_OP(n ## name1 ## name2, s)    \
{                                   \
2718 2719
    FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
    FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2720 2721 2722 2723 2724 2725
    FST2 ^= 1 << 31;                \
    DEBUG_FPU_STATE();              \
    RETURN();                       \
}                                   \
FLOAT_OP(n ## name1 ## name2, ps)   \
{                                   \
2726 2727 2728 2729
    FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
    FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
    FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
    FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2730 2731 2732 2733 2734 2735 2736 2737 2738
    FST2 ^= 1 << 31;                \
    FSTH2 ^= 1 << 31;               \
    DEBUG_FPU_STATE();              \
    RETURN();                       \
}
FLOAT_NTERNOP(mul, add)
FLOAT_NTERNOP(mul, sub)
#undef FLOAT_NTERNOP

B
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2739 2740 2741 2742
/* unary operations, modifying fp status  */
#define FLOAT_UNOP(name)  \
FLOAT_OP(name, d)         \
{                         \
2743
    FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status);   \
B
bellard 已提交
2744
    DEBUG_FPU_STATE();    \
2745
    RETURN();                      \
B
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2746 2747 2748
}                         \
FLOAT_OP(name, s)         \
{                         \
2749
    FST2 = float32_ ## name(FST0, &env->fpu->fp_status);   \
B
bellard 已提交
2750
    DEBUG_FPU_STATE();    \
T
ths 已提交
2751
    RETURN();             \
B
bellard 已提交
2752 2753 2754 2755 2756 2757 2758 2759 2760 2761
}
FLOAT_UNOP(sqrt)
#undef FLOAT_UNOP

/* unary operations, not modifying fp status  */
#define FLOAT_UNOP(name)  \
FLOAT_OP(name, d)         \
{                         \
    FDT2 = float64_ ## name(FDT0);   \
    DEBUG_FPU_STATE();    \
2762
    RETURN();             \
B
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2763 2764 2765 2766 2767
}                         \
FLOAT_OP(name, s)         \
{                         \
    FST2 = float32_ ## name(FST0);   \
    DEBUG_FPU_STATE();    \
2768
    RETURN();             \
2769 2770 2771 2772 2773 2774
}                         \
FLOAT_OP(name, ps)        \
{                         \
    FST2 = float32_ ## name(FST0);   \
    FSTH2 = float32_ ## name(FSTH0); \
    DEBUG_FPU_STATE();    \
2775
    RETURN();             \
B
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2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792
}
FLOAT_UNOP(abs)
FLOAT_UNOP(chs)
#undef FLOAT_UNOP

FLOAT_OP(mov, d)
{
    FDT2 = FDT0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(mov, s)
{
    FST2 = FST0;
    DEBUG_FPU_STATE();
    RETURN();
}
2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821
FLOAT_OP(mov, ps)
{
    FST2 = FST0;
    FSTH2 = FSTH0;
    DEBUG_FPU_STATE();
    RETURN();
}
FLOAT_OP(alnv, ps)
{
    switch (T0 & 0x7) {
    case 0:
        FST2 = FST0;
        FSTH2 = FSTH0;
        break;
    case 4:
#ifdef TARGET_WORDS_BIGENDIAN
        FSTH2 = FST0;
        FST2 = FSTH1;
#else
        FSTH2 = FST1;
        FST2 = FSTH0;
#endif
        break;
    default: /* unpredictable */
        break;
    }
    DEBUG_FPU_STATE();
    RETURN();
}
B
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2822 2823 2824

#ifdef CONFIG_SOFTFLOAT
#define clear_invalid() do {                                \
2825
    int flags = get_float_exception_flags(&env->fpu->fp_status); \
B
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2826
    flags &= ~float_flag_invalid;                           \
2827
    set_float_exception_flags(flags, &env->fpu->fp_status);      \
B
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2828 2829 2830 2831 2832 2833 2834
} while(0)
#else
#define clear_invalid() do { } while(0)
#endif

extern void dump_fpu_s(CPUState *env);

2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870
#define CMP_OP(fmt, op)                                \
void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void)       \
{                                                      \
    CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \
    DEBUG_FPU_STATE();                                 \
    RETURN();                                          \
}                                                      \
void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void)    \
{                                                      \
    CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \
    DEBUG_FPU_STATE();                                 \
    RETURN();                                          \
}
#define CMP_OPS(op)   \
CMP_OP(d, op)         \
CMP_OP(s, op)         \
CMP_OP(ps, op)

CMP_OPS(f)
CMP_OPS(un)
CMP_OPS(eq)
CMP_OPS(ueq)
CMP_OPS(olt)
CMP_OPS(ult)
CMP_OPS(ole)
CMP_OPS(ule)
CMP_OPS(sf)
CMP_OPS(ngle)
CMP_OPS(seq)
CMP_OPS(ngl)
CMP_OPS(lt)
CMP_OPS(nge)
CMP_OPS(le)
CMP_OPS(ngt)
#undef CMP_OPS
#undef CMP_OP
B
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2871 2872 2873

void op_bc1f (void)
{
2874
    T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1));
2875 2876 2877
    DEBUG_FPU_STATE();
    RETURN();
}
2878
void op_bc1any2f (void)
2879
{
2880
    T0 = !!(~GET_FP_COND(env->fpu) & (0x3 << PARAM1));
2881 2882 2883
    DEBUG_FPU_STATE();
    RETURN();
}
2884
void op_bc1any4f (void)
2885
{
2886
    T0 = !!(~GET_FP_COND(env->fpu) & (0xf << PARAM1));
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    DEBUG_FPU_STATE();
    RETURN();
}

void op_bc1t (void)
{
2893
    T0 = !!(GET_FP_COND(env->fpu) & (0x1 << PARAM1));
2894 2895 2896
    DEBUG_FPU_STATE();
    RETURN();
}
2897
void op_bc1any2t (void)
2898
{
2899
    T0 = !!(GET_FP_COND(env->fpu) & (0x3 << PARAM1));
2900 2901 2902
    DEBUG_FPU_STATE();
    RETURN();
}
2903
void op_bc1any4t (void)
2904
{
2905
    T0 = !!(GET_FP_COND(env->fpu) & (0xf << PARAM1));
B
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    DEBUG_FPU_STATE();
    RETURN();
}

B
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void op_tlbwi (void)
{
2912
    CALL_FROM_TB0(env->tlb->do_tlbwi);
B
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    RETURN();
}

void op_tlbwr (void)
{
2918
    CALL_FROM_TB0(env->tlb->do_tlbwr);
B
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    RETURN();
}

void op_tlbp (void)
{
2924
    CALL_FROM_TB0(env->tlb->do_tlbp);
B
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    RETURN();
}

void op_tlbr (void)
{
2930
    CALL_FROM_TB0(env->tlb->do_tlbr);
B
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    RETURN();
}

/* Specials */
2935 2936 2937
#if defined (CONFIG_USER_ONLY)
void op_tls_value (void)
{
2938
    T0 = env->tls_value;
2939 2940 2941
}
#endif

B
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void op_pmon (void)
{
    CALL_FROM_TB1(do_pmon, PARAM1);
2945 2946 2947 2948 2949 2950
    RETURN();
}

void op_di (void)
{
    T0 = env->CP0_Status;
2951 2952
    env->CP0_Status = T0 & ~(1 << CP0St_IE);
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2953 2954 2955 2956 2957 2958
    RETURN();
}

void op_ei (void)
{
    T0 = env->CP0_Status;
2959 2960
    env->CP0_Status = T0 | (1 << CP0St_IE);
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2961
    RETURN();
B
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}

void op_trap (void)
{
    if (T0) {
2967
        CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
B
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2968 2969 2970 2971
    }
    RETURN();
}

B
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2972 2973
void op_debug (void)
{
2974 2975
    CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
    RETURN();
B
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}

B
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2978 2979 2980
void op_set_lladdr (void)
{
    env->CP0_LLAddr = T2;
2981
    RETURN();
B
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2982 2983
}

2984 2985
void debug_pre_eret (void);
void debug_post_eret (void);
B
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2986 2987
void op_eret (void)
{
2988 2989
    if (loglevel & CPU_LOG_EXEC)
        CALL_FROM_TB0(debug_pre_eret);
T
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2990
    if (env->CP0_Status & (1 << CP0St_ERL)) {
2991
        env->PC[env->current_tc] = env->CP0_ErrorEPC;
T
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2992
        env->CP0_Status &= ~(1 << CP0St_ERL);
B
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2993
    } else {
2994
        env->PC[env->current_tc] = env->CP0_EPC;
T
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2995
        env->CP0_Status &= ~(1 << CP0St_EXL);
B
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2996
    }
2997
    CALL_FROM_TB1(compute_hflags, env);
2998 2999
    if (loglevel & CPU_LOG_EXEC)
        CALL_FROM_TB0(debug_post_eret);
B
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3000
    env->CP0_LLAddr = 1;
3001
    RETURN();
B
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3002 3003 3004 3005
}

void op_deret (void)
{
3006 3007
    if (loglevel & CPU_LOG_EXEC)
        CALL_FROM_TB0(debug_pre_eret);
3008
    env->PC[env->current_tc] = env->CP0_DEPC;
3009 3010
    env->hflags &= MIPS_HFLAG_DM;
    CALL_FROM_TB1(compute_hflags, env);
3011 3012
    if (loglevel & CPU_LOG_EXEC)
        CALL_FROM_TB0(debug_post_eret);
T
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3013
    env->CP0_LLAddr = 1;
3014 3015 3016 3017 3018
    RETURN();
}

void op_rdhwr_cpunum(void)
{
3019 3020
    if ((env->hflags & MIPS_HFLAG_CP0) ||
        (env->CP0_HWREna & (1 << 0)))
3021
        T0 = env->CP0_EBase & 0x3ff;
3022
    else
3023
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3024 3025 3026 3027 3028
    RETURN();
}

void op_rdhwr_synci_step(void)
{
3029 3030
    if ((env->hflags & MIPS_HFLAG_CP0) ||
        (env->CP0_HWREna & (1 << 1)))
3031
        T0 = env->SYNCI_Step;
3032
    else
3033
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3034 3035 3036 3037 3038
    RETURN();
}

void op_rdhwr_cc(void)
{
3039 3040
    if ((env->hflags & MIPS_HFLAG_CP0) ||
        (env->CP0_HWREna & (1 << 2)))
3041
        T0 = env->CP0_Count;
3042
    else
3043
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3044 3045 3046 3047 3048
    RETURN();
}

void op_rdhwr_ccres(void)
{
3049 3050
    if ((env->hflags & MIPS_HFLAG_CP0) ||
        (env->CP0_HWREna & (1 << 3)))
3051
        T0 = env->CCRes;
3052
    else
3053 3054 3055 3056
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
    RETURN();
}

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void op_save_state (void)
{
    env->hflags = PARAM1;
    RETURN();
}

void op_save_pc (void)
{
3065
    env->PC[env->current_tc] = PARAM1;
B
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3066 3067 3068
    RETURN();
}

3069
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
3070 3071
void op_save_pc64 (void)
{
3072
    env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
3073 3074 3075 3076
    RETURN();
}
#endif

T
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3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089
void op_interrupt_restart (void)
{
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM) &&
        (env->CP0_Status & (1 << CP0St_IE)) &&
        (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
        env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
        CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT);
    }
    RETURN();
}

B
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3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104
void op_raise_exception (void)
{
    CALL_FROM_TB1(do_raise_exception, PARAM1);
    RETURN();
}

void op_raise_exception_err (void)
{
    CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
    RETURN();
}

void op_exit_tb (void)
{
    EXIT_TB();
3105
    RETURN();
B
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3106 3107
}

B
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3108 3109 3110 3111
void op_wait (void)
{
    env->halted = 1;
    CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
3112 3113 3114 3115 3116 3117 3118 3119 3120
    RETURN();
}

/* Bitfield operations. */
void op_ext(void)
{
    unsigned int pos = PARAM1;
    unsigned int size = PARAM2;

T
ths 已提交
3121
    T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
3122 3123 3124 3125 3126 3127 3128
    RETURN();
}

void op_ins(void)
{
    unsigned int pos = PARAM1;
    unsigned int size = PARAM2;
T
ths 已提交
3129
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
3130

3131
    T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
3132 3133 3134 3135 3136 3137 3138 3139 3140
    RETURN();
}

void op_wsbh(void)
{
    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
    RETURN();
}

3141
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
3142 3143 3144 3145 3146
void op_dext(void)
{
    unsigned int pos = PARAM1;
    unsigned int size = PARAM2;

T
ths 已提交
3147
    T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
3148 3149 3150 3151 3152 3153 3154
    RETURN();
}

void op_dins(void)
{
    unsigned int pos = PARAM1;
    unsigned int size = PARAM2;
T
ths 已提交
3155
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
3156

3157
    T0 = (T0 & ~mask) | ((T1 << pos) & mask);
3158 3159 3160
    RETURN();
}

3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171
void op_dsbh(void)
{
    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
    RETURN();
}

void op_dshd(void)
{
    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
    RETURN();
}
3172
#endif
3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183

void op_seb(void)
{
    T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
    RETURN();
}

void op_seh(void)
{
    T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
    RETURN();
B
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3184
}