cirrus_vga.c 89.4 KB
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/*
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 * QEMU Cirrus CLGD 54xx VGA Emulator.
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 *
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 * Copyright (c) 2004 Fabrice Bellard
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 * Copyright (c) 2004 Makoto Suzuki (suzu)
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
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/*
 * Reference: Finn Thogersons' VGADOC4b
 *   available at http://home.worldonline.dk/~finth/
 */
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#include "hw.h"
#include "pci.h"
#include "console.h"
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#include "vga_int.h"
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#include "loader.h"
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/*
 * TODO:
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 *    - destination write mask support not complete (bits 5..7)
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 *    - optimize linear mappings
 *    - optimize bitblt functions
 */

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//#define DEBUG_CIRRUS
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//#define DEBUG_BITBLT
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/***************************************
 *
 *  definitions
 *
 ***************************************/

// ID
#define CIRRUS_ID_CLGD5422  (0x23<<2)
#define CIRRUS_ID_CLGD5426  (0x24<<2)
#define CIRRUS_ID_CLGD5424  (0x25<<2)
#define CIRRUS_ID_CLGD5428  (0x26<<2)
#define CIRRUS_ID_CLGD5430  (0x28<<2)
#define CIRRUS_ID_CLGD5434  (0x2A<<2)
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#define CIRRUS_ID_CLGD5436  (0x2B<<2)
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#define CIRRUS_ID_CLGD5446  (0x2E<<2)

// sequencer 0x07
#define CIRRUS_SR7_BPP_VGA            0x00
#define CIRRUS_SR7_BPP_SVGA           0x01
#define CIRRUS_SR7_BPP_MASK           0x0e
#define CIRRUS_SR7_BPP_8              0x00
#define CIRRUS_SR7_BPP_16_DOUBLEVCLK  0x02
#define CIRRUS_SR7_BPP_24             0x04
#define CIRRUS_SR7_BPP_16             0x06
#define CIRRUS_SR7_BPP_32             0x08
#define CIRRUS_SR7_ISAADDR_MASK       0xe0

// sequencer 0x0f
#define CIRRUS_MEMSIZE_512k        0x08
#define CIRRUS_MEMSIZE_1M          0x10
#define CIRRUS_MEMSIZE_2M          0x18
#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80	// bank switching is enabled.

// sequencer 0x12
#define CIRRUS_CURSOR_SHOW         0x01
#define CIRRUS_CURSOR_HIDDENPEL    0x02
#define CIRRUS_CURSOR_LARGE        0x04	// 64x64 if set, 32x32 if clear

// sequencer 0x17
#define CIRRUS_BUSTYPE_VLBFAST   0x10
#define CIRRUS_BUSTYPE_PCI       0x20
#define CIRRUS_BUSTYPE_VLBSLOW   0x30
#define CIRRUS_BUSTYPE_ISA       0x38
#define CIRRUS_MMIO_ENABLE       0x04
#define CIRRUS_MMIO_USE_PCIADDR  0x40	// 0xb8000 if cleared.
#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80

// control 0x0b
#define CIRRUS_BANKING_DUAL             0x01
#define CIRRUS_BANKING_GRANULARITY_16K  0x20	// set:16k, clear:4k

// control 0x30
#define CIRRUS_BLTMODE_BACKWARDS        0x01
#define CIRRUS_BLTMODE_MEMSYSDEST       0x02
#define CIRRUS_BLTMODE_MEMSYSSRC        0x04
#define CIRRUS_BLTMODE_TRANSPARENTCOMP  0x08
#define CIRRUS_BLTMODE_PATTERNCOPY      0x40
#define CIRRUS_BLTMODE_COLOREXPAND      0x80
#define CIRRUS_BLTMODE_PIXELWIDTHMASK   0x30
#define CIRRUS_BLTMODE_PIXELWIDTH8      0x00
#define CIRRUS_BLTMODE_PIXELWIDTH16     0x10
#define CIRRUS_BLTMODE_PIXELWIDTH24     0x20
#define CIRRUS_BLTMODE_PIXELWIDTH32     0x30

// control 0x31
#define CIRRUS_BLT_BUSY                 0x01
#define CIRRUS_BLT_START                0x02
#define CIRRUS_BLT_RESET                0x04
#define CIRRUS_BLT_FIFOUSED             0x10
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#define CIRRUS_BLT_AUTOSTART            0x80
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// control 0x32
#define CIRRUS_ROP_0                    0x00
#define CIRRUS_ROP_SRC_AND_DST          0x05
#define CIRRUS_ROP_NOP                  0x06
#define CIRRUS_ROP_SRC_AND_NOTDST       0x09
#define CIRRUS_ROP_NOTDST               0x0b
#define CIRRUS_ROP_SRC                  0x0d
#define CIRRUS_ROP_1                    0x0e
#define CIRRUS_ROP_NOTSRC_AND_DST       0x50
#define CIRRUS_ROP_SRC_XOR_DST          0x59
#define CIRRUS_ROP_SRC_OR_DST           0x6d
#define CIRRUS_ROP_NOTSRC_OR_NOTDST     0x90
#define CIRRUS_ROP_SRC_NOTXOR_DST       0x95
#define CIRRUS_ROP_SRC_OR_NOTDST        0xad
#define CIRRUS_ROP_NOTSRC               0xd0
#define CIRRUS_ROP_NOTSRC_OR_DST        0xd6
#define CIRRUS_ROP_NOTSRC_AND_NOTDST    0xda

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#define CIRRUS_ROP_NOP_INDEX 2
#define CIRRUS_ROP_SRC_INDEX 5

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// control 0x33
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#define CIRRUS_BLTMODEEXT_SOLIDFILL        0x04
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#define CIRRUS_BLTMODEEXT_COLOREXPINV      0x02
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#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
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// memory-mapped IO
#define CIRRUS_MMIO_BLTBGCOLOR        0x00	// dword
#define CIRRUS_MMIO_BLTFGCOLOR        0x04	// dword
#define CIRRUS_MMIO_BLTWIDTH          0x08	// word
#define CIRRUS_MMIO_BLTHEIGHT         0x0a	// word
#define CIRRUS_MMIO_BLTDESTPITCH      0x0c	// word
#define CIRRUS_MMIO_BLTSRCPITCH       0x0e	// word
#define CIRRUS_MMIO_BLTDESTADDR       0x10	// dword
#define CIRRUS_MMIO_BLTSRCADDR        0x14	// dword
#define CIRRUS_MMIO_BLTWRITEMASK      0x17	// byte
#define CIRRUS_MMIO_BLTMODE           0x18	// byte
#define CIRRUS_MMIO_BLTROP            0x1a	// byte
#define CIRRUS_MMIO_BLTMODEEXT        0x1b	// byte
#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c	// word?
#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20	// word?
#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24	// word
#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26	// word
#define CIRRUS_MMIO_LINEARDRAW_END_X  0x28	// word
#define CIRRUS_MMIO_LINEARDRAW_END_Y  0x2a	// word
#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c	// byte
#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d	// byte
#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e	// byte
#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f	// byte
#define CIRRUS_MMIO_BRESENHAM_K1      0x30	// word
#define CIRRUS_MMIO_BRESENHAM_K3      0x32	// word
#define CIRRUS_MMIO_BRESENHAM_ERROR   0x34	// word
#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36	// word
#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38	// byte
#define CIRRUS_MMIO_LINEDRAW_MODE     0x39	// byte
#define CIRRUS_MMIO_BLTSTATUS         0x40	// byte

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#define CIRRUS_PNPMMIO_SIZE         0x1000
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#define BLTUNSAFE(s) \
    ( \
        ( /* check dst is within bounds */ \
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            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
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                + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
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                    (s)->vga.vram_size \
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        ) || \
        ( /* check src is within bounds */ \
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            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
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                + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
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                    (s)->vga.vram_size \
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        ) \
    )

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struct CirrusVGAState;
typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
                                     uint8_t * dst, const uint8_t * src,
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				     int dstpitch, int srcpitch,
				     int bltwidth, int bltheight);
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typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
                              uint8_t *dst, int dst_pitch, int width, int height);
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typedef struct CirrusVGAState {
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    VGACommonState vga;
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    MemoryRegion cirrus_vga_io;
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    MemoryRegion cirrus_linear_io;
    MemoryRegion cirrus_linear_bitblt_io;
    MemoryRegion cirrus_mmio_io;
    MemoryRegion pci_bar;
    bool linear_vram;  /* vga.vram mapped over cirrus_linear_io */
    MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
    MemoryRegion low_mem;           /* always mapped, overridden by: */
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    MemoryRegion cirrus_bank[2];    /*   aliases at 0xa0000-0xb0000  */
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    uint32_t cirrus_addr_mask;
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    uint32_t linear_mmio_mask;
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    uint8_t cirrus_shadow_gr0;
    uint8_t cirrus_shadow_gr1;
    uint8_t cirrus_hidden_dac_lockindex;
    uint8_t cirrus_hidden_dac_data;
    uint32_t cirrus_bank_base[2];
    uint32_t cirrus_bank_limit[2];
    uint8_t cirrus_hidden_palette[48];
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    uint32_t hw_cursor_x;
    uint32_t hw_cursor_y;
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    int cirrus_blt_pixelwidth;
    int cirrus_blt_width;
    int cirrus_blt_height;
    int cirrus_blt_dstpitch;
    int cirrus_blt_srcpitch;
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    uint32_t cirrus_blt_fgcol;
    uint32_t cirrus_blt_bgcol;
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    uint32_t cirrus_blt_dstaddr;
    uint32_t cirrus_blt_srcaddr;
    uint8_t cirrus_blt_mode;
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    uint8_t cirrus_blt_modeext;
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    cirrus_bitblt_rop_t cirrus_rop;
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#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
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    uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
    uint8_t *cirrus_srcptr;
    uint8_t *cirrus_srcptr_end;
    uint32_t cirrus_srccounter;
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    /* hwcursor display state */
    int last_hw_cursor_size;
    int last_hw_cursor_x;
    int last_hw_cursor_y;
    int last_hw_cursor_y_start;
    int last_hw_cursor_y_end;
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    int real_vram_size; /* XXX: suppress that */
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    int device_id;
    int bustype;
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} CirrusVGAState;

typedef struct PCICirrusVGAState {
    PCIDevice dev;
    CirrusVGAState cirrus_vga;
} PCICirrusVGAState;

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typedef struct ISACirrusVGAState {
    ISADevice dev;
    CirrusVGAState cirrus_vga;
} ISACirrusVGAState;

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static uint8_t rop_to_index[256];
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/***************************************
 *
 *  prototypes.
 *
 ***************************************/


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static void cirrus_bitblt_reset(CirrusVGAState *s);
static void cirrus_update_memory_access(CirrusVGAState *s);
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/***************************************
 *
 *  raster operations
 *
 ***************************************/

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static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
                                  uint8_t *dst,const uint8_t *src,
                                  int dstpitch,int srcpitch,
                                  int bltwidth,int bltheight)
{
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}

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static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
                                   uint8_t *dst,
                                   int dstpitch, int bltwidth,int bltheight)
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{
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}
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#define ROP_NAME 0
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#define ROP_FN(d, s) 0
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#include "cirrus_vga_rop.h"
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#define ROP_NAME src_and_dst
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#define ROP_FN(d, s) (s) & (d)
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#include "cirrus_vga_rop.h"
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#define ROP_NAME src_and_notdst
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#define ROP_FN(d, s) (s) & (~(d))
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#include "cirrus_vga_rop.h"
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#define ROP_NAME notdst
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#define ROP_FN(d, s) ~(d)
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#include "cirrus_vga_rop.h"
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#define ROP_NAME src
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#define ROP_FN(d, s) s
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#include "cirrus_vga_rop.h"
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#define ROP_NAME 1
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#define ROP_FN(d, s) ~0
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#include "cirrus_vga_rop.h"

#define ROP_NAME notsrc_and_dst
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#define ROP_FN(d, s) (~(s)) & (d)
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#include "cirrus_vga_rop.h"

#define ROP_NAME src_xor_dst
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#define ROP_FN(d, s) (s) ^ (d)
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#include "cirrus_vga_rop.h"

#define ROP_NAME src_or_dst
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#define ROP_FN(d, s) (s) | (d)
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#include "cirrus_vga_rop.h"

#define ROP_NAME notsrc_or_notdst
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#define ROP_FN(d, s) (~(s)) | (~(d))
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#include "cirrus_vga_rop.h"

#define ROP_NAME src_notxor_dst
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#define ROP_FN(d, s) ~((s) ^ (d))
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#include "cirrus_vga_rop.h"
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#define ROP_NAME src_or_notdst
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#define ROP_FN(d, s) (s) | (~(d))
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#include "cirrus_vga_rop.h"

#define ROP_NAME notsrc
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#define ROP_FN(d, s) (~(s))
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#include "cirrus_vga_rop.h"

#define ROP_NAME notsrc_or_dst
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#define ROP_FN(d, s) (~(s)) | (d)
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#include "cirrus_vga_rop.h"

#define ROP_NAME notsrc_and_notdst
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#define ROP_FN(d, s) (~(s)) & (~(d))
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#include "cirrus_vga_rop.h"

static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
    cirrus_bitblt_rop_fwd_0,
    cirrus_bitblt_rop_fwd_src_and_dst,
    cirrus_bitblt_rop_nop,
    cirrus_bitblt_rop_fwd_src_and_notdst,
    cirrus_bitblt_rop_fwd_notdst,
    cirrus_bitblt_rop_fwd_src,
    cirrus_bitblt_rop_fwd_1,
    cirrus_bitblt_rop_fwd_notsrc_and_dst,
    cirrus_bitblt_rop_fwd_src_xor_dst,
    cirrus_bitblt_rop_fwd_src_or_dst,
    cirrus_bitblt_rop_fwd_notsrc_or_notdst,
    cirrus_bitblt_rop_fwd_src_notxor_dst,
    cirrus_bitblt_rop_fwd_src_or_notdst,
    cirrus_bitblt_rop_fwd_notsrc,
    cirrus_bitblt_rop_fwd_notsrc_or_dst,
    cirrus_bitblt_rop_fwd_notsrc_and_notdst,
};

static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
    cirrus_bitblt_rop_bkwd_0,
    cirrus_bitblt_rop_bkwd_src_and_dst,
    cirrus_bitblt_rop_nop,
    cirrus_bitblt_rop_bkwd_src_and_notdst,
    cirrus_bitblt_rop_bkwd_notdst,
    cirrus_bitblt_rop_bkwd_src,
    cirrus_bitblt_rop_bkwd_1,
    cirrus_bitblt_rop_bkwd_notsrc_and_dst,
    cirrus_bitblt_rop_bkwd_src_xor_dst,
    cirrus_bitblt_rop_bkwd_src_or_dst,
    cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
    cirrus_bitblt_rop_bkwd_src_notxor_dst,
    cirrus_bitblt_rop_bkwd_src_or_notdst,
    cirrus_bitblt_rop_bkwd_notsrc,
    cirrus_bitblt_rop_bkwd_notsrc_or_dst,
    cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
};
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#define TRANSP_ROP(name) {\
    name ## _8,\
    name ## _16,\
        }
#define TRANSP_NOP(func) {\
    func,\
    func,\
        }

static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
    TRANSP_NOP(cirrus_bitblt_rop_nop),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
};

static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
    TRANSP_NOP(cirrus_bitblt_rop_nop),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
};

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#define ROP2(name) {\
    name ## _8,\
    name ## _16,\
    name ## _24,\
    name ## _32,\
        }

#define ROP_NOP2(func) {\
    func,\
    func,\
    func,\
    func,\
        }

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static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
    ROP2(cirrus_patternfill_0),
    ROP2(cirrus_patternfill_src_and_dst),
    ROP_NOP2(cirrus_bitblt_rop_nop),
    ROP2(cirrus_patternfill_src_and_notdst),
    ROP2(cirrus_patternfill_notdst),
    ROP2(cirrus_patternfill_src),
    ROP2(cirrus_patternfill_1),
    ROP2(cirrus_patternfill_notsrc_and_dst),
    ROP2(cirrus_patternfill_src_xor_dst),
    ROP2(cirrus_patternfill_src_or_dst),
    ROP2(cirrus_patternfill_notsrc_or_notdst),
    ROP2(cirrus_patternfill_src_notxor_dst),
    ROP2(cirrus_patternfill_src_or_notdst),
    ROP2(cirrus_patternfill_notsrc),
    ROP2(cirrus_patternfill_notsrc_or_dst),
    ROP2(cirrus_patternfill_notsrc_and_notdst),
};

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static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
    ROP2(cirrus_colorexpand_transp_0),
    ROP2(cirrus_colorexpand_transp_src_and_dst),
    ROP_NOP2(cirrus_bitblt_rop_nop),
    ROP2(cirrus_colorexpand_transp_src_and_notdst),
    ROP2(cirrus_colorexpand_transp_notdst),
    ROP2(cirrus_colorexpand_transp_src),
    ROP2(cirrus_colorexpand_transp_1),
    ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
    ROP2(cirrus_colorexpand_transp_src_xor_dst),
    ROP2(cirrus_colorexpand_transp_src_or_dst),
    ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
    ROP2(cirrus_colorexpand_transp_src_notxor_dst),
    ROP2(cirrus_colorexpand_transp_src_or_notdst),
    ROP2(cirrus_colorexpand_transp_notsrc),
    ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
    ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
};

static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
    ROP2(cirrus_colorexpand_0),
    ROP2(cirrus_colorexpand_src_and_dst),
    ROP_NOP2(cirrus_bitblt_rop_nop),
    ROP2(cirrus_colorexpand_src_and_notdst),
    ROP2(cirrus_colorexpand_notdst),
    ROP2(cirrus_colorexpand_src),
    ROP2(cirrus_colorexpand_1),
    ROP2(cirrus_colorexpand_notsrc_and_dst),
    ROP2(cirrus_colorexpand_src_xor_dst),
    ROP2(cirrus_colorexpand_src_or_dst),
    ROP2(cirrus_colorexpand_notsrc_or_notdst),
    ROP2(cirrus_colorexpand_src_notxor_dst),
    ROP2(cirrus_colorexpand_src_or_notdst),
    ROP2(cirrus_colorexpand_notsrc),
    ROP2(cirrus_colorexpand_notsrc_or_dst),
    ROP2(cirrus_colorexpand_notsrc_and_notdst),
};

B
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505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
    ROP2(cirrus_colorexpand_pattern_transp_0),
    ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
    ROP_NOP2(cirrus_bitblt_rop_nop),
    ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
    ROP2(cirrus_colorexpand_pattern_transp_notdst),
    ROP2(cirrus_colorexpand_pattern_transp_src),
    ROP2(cirrus_colorexpand_pattern_transp_1),
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
    ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
    ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
    ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
    ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
    ROP2(cirrus_colorexpand_pattern_transp_notsrc),
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
};

static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
    ROP2(cirrus_colorexpand_pattern_0),
    ROP2(cirrus_colorexpand_pattern_src_and_dst),
    ROP_NOP2(cirrus_bitblt_rop_nop),
    ROP2(cirrus_colorexpand_pattern_src_and_notdst),
    ROP2(cirrus_colorexpand_pattern_notdst),
    ROP2(cirrus_colorexpand_pattern_src),
    ROP2(cirrus_colorexpand_pattern_1),
    ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
    ROP2(cirrus_colorexpand_pattern_src_xor_dst),
    ROP2(cirrus_colorexpand_pattern_src_or_dst),
    ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
    ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
    ROP2(cirrus_colorexpand_pattern_src_or_notdst),
    ROP2(cirrus_colorexpand_pattern_notsrc),
    ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
    ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
};

543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562
static const cirrus_fill_t cirrus_fill[16][4] = {
    ROP2(cirrus_fill_0),
    ROP2(cirrus_fill_src_and_dst),
    ROP_NOP2(cirrus_bitblt_fill_nop),
    ROP2(cirrus_fill_src_and_notdst),
    ROP2(cirrus_fill_notdst),
    ROP2(cirrus_fill_src),
    ROP2(cirrus_fill_1),
    ROP2(cirrus_fill_notsrc_and_dst),
    ROP2(cirrus_fill_src_xor_dst),
    ROP2(cirrus_fill_src_or_dst),
    ROP2(cirrus_fill_notsrc_or_notdst),
    ROP2(cirrus_fill_src_notxor_dst),
    ROP2(cirrus_fill_src_or_notdst),
    ROP2(cirrus_fill_notsrc),
    ROP2(cirrus_fill_notsrc_or_dst),
    ROP2(cirrus_fill_notsrc_and_notdst),
};

static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
563
{
564 565 566 567 568 569
    unsigned int color;
    switch (s->cirrus_blt_pixelwidth) {
    case 1:
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
        break;
    case 2:
570
        color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
571 572 573
        s->cirrus_blt_fgcol = le16_to_cpu(color);
        break;
    case 3:
574
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
575
            (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
576 577 578
        break;
    default:
    case 4:
579 580
        color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
            (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
581 582
        s->cirrus_blt_fgcol = le32_to_cpu(color);
        break;
583 584 585
    }
}

586
static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
587
{
588
    unsigned int color;
589 590
    switch (s->cirrus_blt_pixelwidth) {
    case 1:
591 592
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
        break;
593
    case 2:
594
        color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
595 596
        s->cirrus_blt_bgcol = le16_to_cpu(color);
        break;
597
    case 3:
598
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
599
            (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
600
        break;
601
    default:
602
    case 4:
603 604
        color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
            (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
605 606
        s->cirrus_blt_bgcol = le32_to_cpu(color);
        break;
607 608 609 610 611 612 613 614 615 616 617 618 619
    }
}

static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
				     int off_pitch, int bytesperline,
				     int lines)
{
    int y;
    int off_cur;
    int off_cur_end;

    for (y = 0; y < lines; y++) {
	off_cur = off_begin;
620
	off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
621
        memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
622 623 624 625 626 627 628 629 630
	off_begin += off_pitch;
    }
}

static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
					    const uint8_t * src)
{
    uint8_t *dst;

631
    dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
632 633 634 635

    if (BLTUNSAFE(s))
        return 0;

B
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636
    (*s->cirrus_rop) (s, dst, src,
637
                      s->cirrus_blt_dstpitch, 0,
B
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638
                      s->cirrus_blt_width, s->cirrus_blt_height);
639
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
B
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640 641
                             s->cirrus_blt_dstpitch, s->cirrus_blt_width,
                             s->cirrus_blt_height);
642 643 644
    return 1;
}

645 646
/* fill */

647
static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
648
{
649
    cirrus_fill_t rop_func;
650

651 652
    if (BLTUNSAFE(s))
        return 0;
653
    rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
654
    rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
655 656
             s->cirrus_blt_dstpitch,
             s->cirrus_blt_width, s->cirrus_blt_height);
657 658 659 660 661 662 663
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
			     s->cirrus_blt_dstpitch, s->cirrus_blt_width,
			     s->cirrus_blt_height);
    cirrus_bitblt_reset(s);
    return 1;
}

664 665 666 667 668 669 670 671 672
/***************************************
 *
 *  bitblt (video-to-video)
 *
 ***************************************/

static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
{
    return cirrus_bitblt_common_patterncopy(s,
673
					    s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
674
                                            s->cirrus_addr_mask));
675 676
}

B
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static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
678
{
A
Aurelien Jarno 已提交
679 680 681
    int sx = 0, sy = 0;
    int dx = 0, dy = 0;
    int depth = 0;
B
bellard 已提交
682 683
    int notify = 0;

684 685 686
    /* make sure to only copy if it's a plain copy ROP */
    if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
        *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
B
bellard 已提交
687

688 689 690 691 692 693 694 695 696 697
        int width, height;

        depth = s->vga.get_bpp(&s->vga) / 8;
        s->vga.get_resolution(&s->vga, &width, &height);

        /* extra x, y */
        sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
        sy = (src / ABS(s->cirrus_blt_srcpitch));
        dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
        dy = (dst / ABS(s->cirrus_blt_dstpitch));
B
bellard 已提交
698

699 700
        /* normalize width */
        w /= depth;
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701

702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718
        /* if we're doing a backward copy, we have to adjust
           our x/y to be the upper left corner (instead of the lower
           right corner) */
        if (s->cirrus_blt_dstpitch < 0) {
            sx -= (s->cirrus_blt_width / depth) - 1;
            dx -= (s->cirrus_blt_width / depth) - 1;
            sy -= s->cirrus_blt_height - 1;
            dy -= s->cirrus_blt_height - 1;
        }

        /* are we in the visible portion of memory? */
        if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
            (sx + w) <= width && (sy + h) <= height &&
            (dx + w) <= width && (dy + h) <= height) {
            notify = 1;
        }
    }
B
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719 720 721 722 723 724

    /* we have to flush all pending changes so that the copy
       is generated at the appropriate moment in time */
    if (notify)
	vga_hw_update();

725
    (*s->cirrus_rop) (s, s->vga.vram_ptr +
726
		      (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
727
		      s->vga.vram_ptr +
728
		      (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
729 730
		      s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
		      s->cirrus_blt_width, s->cirrus_blt_height);
B
bellard 已提交
731 732

    if (notify)
733
	qemu_console_copy(s->vga.ds,
734 735 736
			  sx, sy, dx, dy,
			  s->cirrus_blt_width / depth,
			  s->cirrus_blt_height);
B
bellard 已提交
737 738

    /* we don't have to notify the display that this portion has
739
       changed since qemu_console_copy implies this */
B
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740

741 742 743
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
				s->cirrus_blt_dstpitch, s->cirrus_blt_width,
				s->cirrus_blt_height);
B
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744 745 746 747
}

static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
{
748 749 750
    if (BLTUNSAFE(s))
        return 0;

751 752
    cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
            s->cirrus_blt_srcaddr - s->vga.start_addr,
753
            s->cirrus_blt_width, s->cirrus_blt_height);
B
bellard 已提交
754

755 756 757 758 759 760 761 762 763 764 765 766
    return 1;
}

/***************************************
 *
 *  bitblt (cpu-to-video)
 *
 ***************************************/

static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
{
    int copy_count;
767
    uint8_t *end_ptr;
768

769
    if (s->cirrus_srccounter > 0) {
770 771 772 773 774 775 776 777
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
            cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
        the_end:
            s->cirrus_srccounter = 0;
            cirrus_bitblt_reset(s);
        } else {
            /* at least one scan line */
            do {
778
                (*s->cirrus_rop)(s, s->vga.vram_ptr +
779 780
                                 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
                                  s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
781 782 783 784 785 786
                cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
                                         s->cirrus_blt_width, 1);
                s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
                s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
                if (s->cirrus_srccounter <= 0)
                    goto the_end;
D
Dong Xu Wang 已提交
787
                /* more bytes than needed can be transferred because of
788 789 790 791 792 793 794 795 796
                   word alignment, so we keep them for the next line */
                /* XXX: keep alignment to speed up transfer */
                end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
                copy_count = s->cirrus_srcptr_end - end_ptr;
                memmove(s->cirrus_bltbuf, end_ptr, copy_count);
                s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
                s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
            } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
        }
797 798 799 800 801 802 803 804 805 806 807
    }
}

/***************************************
 *
 *  bitblt wrapper
 *
 ***************************************/

static void cirrus_bitblt_reset(CirrusVGAState * s)
{
808 809
    int need_update;

810
    s->vga.gr[0x31] &=
811
	~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
812 813
    need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
        || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
814 815 816
    s->cirrus_srcptr = &s->cirrus_bltbuf[0];
    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
    s->cirrus_srccounter = 0;
817 818
    if (!need_update)
        return;
B
bellard 已提交
819
    cirrus_update_memory_access(s);
820 821 822 823
}

static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
{
824 825
    int w;

826 827 828 829 830 831
    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
    s->cirrus_srcptr = &s->cirrus_bltbuf[0];
    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];

    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
	if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
832
	    s->cirrus_blt_srcpitch = 8;
833
	} else {
B
bellard 已提交
834
            /* XXX: check for 24 bpp */
835
	    s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
836
	}
837
	s->cirrus_srccounter = s->cirrus_blt_srcpitch;
838 839
    } else {
	if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
840
            w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
841
            if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
842 843 844
                s->cirrus_blt_srcpitch = ((w + 31) >> 5);
            else
                s->cirrus_blt_srcpitch = ((w + 7) >> 3);
845
	} else {
B
bellard 已提交
846 847
            /* always align input size to 32 bits */
	    s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
848
	}
849
        s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
850
    }
851 852
    s->cirrus_srcptr = s->cirrus_bltbuf;
    s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
B
bellard 已提交
853
    cirrus_update_memory_access(s);
854 855 856 857 858 859
    return 1;
}

static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
{
    /* XXX */
860
#ifdef DEBUG_BITBLT
861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883
    printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
#endif
    return 0;
}

static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
{
    int ret;

    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
	ret = cirrus_bitblt_videotovideo_patterncopy(s);
    } else {
	ret = cirrus_bitblt_videotovideo_copy(s);
    }
    if (ret)
	cirrus_bitblt_reset(s);
    return ret;
}

static void cirrus_bitblt_start(CirrusVGAState * s)
{
    uint8_t blt_rop;

884
    s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
885

886 887 888 889
    s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
    s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
    s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
    s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
890
    s->cirrus_blt_dstaddr =
891
	(s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
892
    s->cirrus_blt_srcaddr =
893 894 895 896
	(s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
    s->cirrus_blt_mode = s->vga.gr[0x30];
    s->cirrus_blt_modeext = s->vga.gr[0x33];
    blt_rop = s->vga.gr[0x32];
897

898
#ifdef DEBUG_BITBLT
B
bellard 已提交
899
    printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
900
           blt_rop,
901
           s->cirrus_blt_mode,
902
           s->cirrus_blt_modeext,
903 904 905 906 907
           s->cirrus_blt_width,
           s->cirrus_blt_height,
           s->cirrus_blt_dstpitch,
           s->cirrus_blt_srcpitch,
           s->cirrus_blt_dstaddr,
908
           s->cirrus_blt_srcaddr,
909
           s->vga.gr[0x2f]);
910 911
#endif

912 913 914 915 916 917 918 919 920 921 922 923 924 925
    switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
    case CIRRUS_BLTMODE_PIXELWIDTH8:
	s->cirrus_blt_pixelwidth = 1;
	break;
    case CIRRUS_BLTMODE_PIXELWIDTH16:
	s->cirrus_blt_pixelwidth = 2;
	break;
    case CIRRUS_BLTMODE_PIXELWIDTH24:
	s->cirrus_blt_pixelwidth = 3;
	break;
    case CIRRUS_BLTMODE_PIXELWIDTH32:
	s->cirrus_blt_pixelwidth = 4;
	break;
    default:
926
#ifdef DEBUG_BITBLT
927 928 929 930 931 932 933 934 935 936
	printf("cirrus: bitblt - pixel width is unknown\n");
#endif
	goto bitblt_ignore;
    }
    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;

    if ((s->
	 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
			    CIRRUS_BLTMODE_MEMSYSDEST))
	== (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
937
#ifdef DEBUG_BITBLT
938 939 940 941 942
	printf("cirrus: bitblt - memory-to-memory copy is requested\n");
#endif
	goto bitblt_ignore;
    }

943
    if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
944
        (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
945
                               CIRRUS_BLTMODE_TRANSPARENTCOMP |
946 947
                               CIRRUS_BLTMODE_PATTERNCOPY |
                               CIRRUS_BLTMODE_COLOREXPAND)) ==
948
         (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
949 950
        cirrus_bitblt_fgcol(s);
        cirrus_bitblt_solidfill(s, blt_rop);
951
    } else {
952 953
        if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
                                   CIRRUS_BLTMODE_PATTERNCOPY)) ==
954 955 956
            CIRRUS_BLTMODE_COLOREXPAND) {

            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
B
bellard 已提交
957
                if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
B
bellard 已提交
958
                    cirrus_bitblt_bgcol(s);
B
bellard 已提交
959
                else
B
bellard 已提交
960
                    cirrus_bitblt_fgcol(s);
B
bellard 已提交
961
                s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
962 963 964 965 966
            } else {
                cirrus_bitblt_fgcol(s);
                cirrus_bitblt_bgcol(s);
                s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
            }
B
bellard 已提交
967
        } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
B
bellard 已提交
968 969 970 971 972 973 974 975 976 977 978 979 980 981 982
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
                    if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
                        cirrus_bitblt_bgcol(s);
                    else
                        cirrus_bitblt_fgcol(s);
                    s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
                } else {
                    cirrus_bitblt_fgcol(s);
                    cirrus_bitblt_bgcol(s);
                    s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
                }
            } else {
                s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
            }
983
        } else {
984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005
	    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
		if (s->cirrus_blt_pixelwidth > 2) {
		    printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
		    goto bitblt_ignore;
		}
		if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
		    s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
		    s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
		    s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
		} else {
		    s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
		}
	    } else {
		if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
		    s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
		    s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
		    s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
		} else {
		    s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
		}
	    }
	}
1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016
        // setup bitblt engine.
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
            if (!cirrus_bitblt_cputovideo(s))
                goto bitblt_ignore;
        } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
            if (!cirrus_bitblt_videotocpu(s))
                goto bitblt_ignore;
        } else {
            if (!cirrus_bitblt_videotovideo(s))
                goto bitblt_ignore;
        }
1017 1018 1019 1020 1021 1022 1023 1024 1025 1026
    }
    return;
  bitblt_ignore:;
    cirrus_bitblt_reset(s);
}

static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
{
    unsigned old_value;

1027 1028
    old_value = s->vga.gr[0x31];
    s->vga.gr[0x31] = reg_value;
1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045

    if (((old_value & CIRRUS_BLT_RESET) != 0) &&
	((reg_value & CIRRUS_BLT_RESET) == 0)) {
	cirrus_bitblt_reset(s);
    } else if (((old_value & CIRRUS_BLT_START) == 0) &&
	       ((reg_value & CIRRUS_BLT_START) != 0)) {
	cirrus_bitblt_start(s);
    }
}


/***************************************
 *
 *  basic parameters
 *
 ***************************************/

1046
static void cirrus_get_offsets(VGACommonState *s1,
1047 1048 1049
                               uint32_t *pline_offset,
                               uint32_t *pstart_addr,
                               uint32_t *pline_compare)
1050
{
1051
    CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1052
    uint32_t start_addr, line_offset, line_compare;
1053

1054 1055
    line_offset = s->vga.cr[0x13]
	| ((s->vga.cr[0x1b] & 0x10) << 4);
1056 1057 1058
    line_offset <<= 3;
    *pline_offset = line_offset;

1059 1060 1061 1062 1063
    start_addr = (s->vga.cr[0x0c] << 8)
	| s->vga.cr[0x0d]
	| ((s->vga.cr[0x1b] & 0x01) << 16)
	| ((s->vga.cr[0x1b] & 0x0c) << 15)
	| ((s->vga.cr[0x1d] & 0x80) << 12);
1064
    *pstart_addr = start_addr;
1065

1066 1067 1068
    line_compare = s->vga.cr[0x18] |
        ((s->vga.cr[0x07] & 0x10) << 4) |
        ((s->vga.cr[0x09] & 0x40) << 3);
1069
    *pline_compare = line_compare;
1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093
}

static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
{
    uint32_t ret = 16;

    switch (s->cirrus_hidden_dac_data & 0xf) {
    case 0:
	ret = 15;
	break;			/* Sierra HiColor */
    case 1:
	ret = 16;
	break;			/* XGA HiColor */
    default:
#ifdef DEBUG_CIRRUS
	printf("cirrus: invalid DAC value %x in 16bpp\n",
	       (s->cirrus_hidden_dac_data & 0xf));
#endif
	ret = 15;		/* XXX */
	break;
    }
    return ret;
}

1094
static int cirrus_get_bpp(VGACommonState *s1)
1095
{
1096
    CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1097 1098
    uint32_t ret = 8;

1099
    if ((s->vga.sr[0x07] & 0x01) != 0) {
1100
	/* Cirrus SVGA */
1101
	switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
	case CIRRUS_SR7_BPP_8:
	    ret = 8;
	    break;
	case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
	    ret = cirrus_get_bpp16_depth(s);
	    break;
	case CIRRUS_SR7_BPP_24:
	    ret = 24;
	    break;
	case CIRRUS_SR7_BPP_16:
	    ret = cirrus_get_bpp16_depth(s);
	    break;
	case CIRRUS_SR7_BPP_32:
	    ret = 32;
	    break;
	default:
#ifdef DEBUG_CIRRUS
1119
	    printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1120 1121 1122 1123 1124 1125
#endif
	    ret = 8;
	    break;
	}
    } else {
	/* VGA */
B
bellard 已提交
1126
	ret = 0;
1127 1128 1129 1130 1131
    }

    return ret;
}

1132
static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1133 1134
{
    int width, height;
1135

1136
    width = (s->cr[0x01] + 1) * 8;
1137 1138
    height = s->cr[0x12] |
        ((s->cr[0x07] & 0x02) << 7) |
1139 1140 1141 1142 1143 1144 1145 1146 1147
        ((s->cr[0x07] & 0x40) << 3);
    height = (height + 1);
    /* interlace support */
    if (s->cr[0x1a] & 0x01)
        height = height * 2;
    *pwidth = width;
    *pheight = height;
}

1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158
/***************************************
 *
 * bank memory
 *
 ***************************************/

static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
{
    unsigned offset;
    unsigned limit;

1159 1160
    if ((s->vga.gr[0x0b] & 0x01) != 0)	/* dual bank */
	offset = s->vga.gr[0x09 + bank_index];
1161
    else			/* single bank */
1162
	offset = s->vga.gr[0x09];
1163

1164
    if ((s->vga.gr[0x0b] & 0x20) != 0)
1165 1166 1167 1168
	offset <<= 14;
    else
	offset <<= 12;

1169
    if (s->real_vram_size <= offset)
1170 1171
	limit = 0;
    else
1172
	limit = s->real_vram_size - offset;
1173

1174
    if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197
	if (limit > 0x8000) {
	    offset += 0x8000;
	    limit -= 0x8000;
	} else {
	    limit = 0;
	}
    }

    if (limit > 0) {
	s->cirrus_bank_base[bank_index] = offset;
	s->cirrus_bank_limit[bank_index] = limit;
    } else {
	s->cirrus_bank_base[bank_index] = 0;
	s->cirrus_bank_limit[bank_index] = 0;
    }
}

/***************************************
 *
 *  I/O access between 0x3c4-0x3c5
 *
 ***************************************/

1198
static int cirrus_vga_read_sr(CirrusVGAState * s)
1199
{
1200
    switch (s->vga.sr_index) {
1201 1202 1203 1204 1205
    case 0x00:			// Standard VGA
    case 0x01:			// Standard VGA
    case 0x02:			// Standard VGA
    case 0x03:			// Standard VGA
    case 0x04:			// Standard VGA
1206
	return s->vga.sr[s->vga.sr_index];
1207
    case 0x06:			// Unlock Cirrus extensions
1208
	return s->vga.sr[s->vga.sr_index];
1209 1210 1211 1212 1213 1214 1215 1216
    case 0x10:
    case 0x30:
    case 0x50:
    case 0x70:			// Graphics Cursor X
    case 0x90:
    case 0xb0:
    case 0xd0:
    case 0xf0:			// Graphics Cursor X
1217
	return s->vga.sr[0x10];
1218 1219 1220 1221 1222 1223 1224
    case 0x11:
    case 0x31:
    case 0x51:
    case 0x71:			// Graphics Cursor Y
    case 0x91:
    case 0xb1:
    case 0xd1:
1225
    case 0xf1:			// Graphics Cursor Y
1226
	return s->vga.sr[0x11];
B
bellard 已提交
1227 1228 1229 1230 1231 1232 1233 1234 1235 1236
    case 0x05:			// ???
    case 0x07:			// Extended Sequencer Mode
    case 0x08:			// EEPROM Control
    case 0x09:			// Scratch Register 0
    case 0x0a:			// Scratch Register 1
    case 0x0b:			// VCLK 0
    case 0x0c:			// VCLK 1
    case 0x0d:			// VCLK 2
    case 0x0e:			// VCLK 3
    case 0x0f:			// DRAM Control
1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251
    case 0x12:			// Graphics Cursor Attribute
    case 0x13:			// Graphics Cursor Pattern Address
    case 0x14:			// Scratch Register 2
    case 0x15:			// Scratch Register 3
    case 0x16:			// Performance Tuning Register
    case 0x17:			// Configuration Readback and Extended Control
    case 0x18:			// Signature Generator Control
    case 0x19:			// Signal Generator Result
    case 0x1a:			// Signal Generator Result
    case 0x1b:			// VCLK 0 Denominator & Post
    case 0x1c:			// VCLK 1 Denominator & Post
    case 0x1d:			// VCLK 2 Denominator & Post
    case 0x1e:			// VCLK 3 Denominator & Post
    case 0x1f:			// BIOS Write Enable and MCLK select
#ifdef DEBUG_CIRRUS
1252
	printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1253
#endif
1254
	return s->vga.sr[s->vga.sr_index];
1255 1256
    default:
#ifdef DEBUG_CIRRUS
1257
	printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1258
#endif
1259
	return 0xff;
1260 1261 1262 1263
	break;
    }
}

1264
static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1265
{
1266
    switch (s->vga.sr_index) {
1267 1268 1269 1270 1271
    case 0x00:			// Standard VGA
    case 0x01:			// Standard VGA
    case 0x02:			// Standard VGA
    case 0x03:			// Standard VGA
    case 0x04:			// Standard VGA
1272 1273 1274 1275
	s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
	if (s->vga.sr_index == 1)
            s->vga.update_retrace_info(&s->vga);
        break;
1276
    case 0x06:			// Unlock Cirrus extensions
1277 1278 1279
	val &= 0x17;
	if (val == 0x12) {
	    s->vga.sr[s->vga.sr_index] = 0x12;
1280
	} else {
1281
	    s->vga.sr[s->vga.sr_index] = 0x0f;
1282 1283 1284 1285 1286 1287 1288 1289 1290 1291
	}
	break;
    case 0x10:
    case 0x30:
    case 0x50:
    case 0x70:			// Graphics Cursor X
    case 0x90:
    case 0xb0:
    case 0xd0:
    case 0xf0:			// Graphics Cursor X
1292 1293
	s->vga.sr[0x10] = val;
	s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1294 1295 1296 1297 1298 1299 1300 1301 1302
	break;
    case 0x11:
    case 0x31:
    case 0x51:
    case 0x71:			// Graphics Cursor Y
    case 0x91:
    case 0xb1:
    case 0xd1:
    case 0xf1:			// Graphics Cursor Y
1303 1304
	s->vga.sr[0x11] = val;
	s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1305 1306
	break;
    case 0x07:			// Extended Sequencer Mode
A
aliguori 已提交
1307
    cirrus_update_memory_access(s);
1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328
    case 0x08:			// EEPROM Control
    case 0x09:			// Scratch Register 0
    case 0x0a:			// Scratch Register 1
    case 0x0b:			// VCLK 0
    case 0x0c:			// VCLK 1
    case 0x0d:			// VCLK 2
    case 0x0e:			// VCLK 3
    case 0x0f:			// DRAM Control
    case 0x12:			// Graphics Cursor Attribute
    case 0x13:			// Graphics Cursor Pattern Address
    case 0x14:			// Scratch Register 2
    case 0x15:			// Scratch Register 3
    case 0x16:			// Performance Tuning Register
    case 0x18:			// Signature Generator Control
    case 0x19:			// Signature Generator Result
    case 0x1a:			// Signature Generator Result
    case 0x1b:			// VCLK 0 Denominator & Post
    case 0x1c:			// VCLK 1 Denominator & Post
    case 0x1d:			// VCLK 2 Denominator & Post
    case 0x1e:			// VCLK 3 Denominator & Post
    case 0x1f:			// BIOS Write Enable and MCLK select
1329
	s->vga.sr[s->vga.sr_index] = val;
1330 1331
#ifdef DEBUG_CIRRUS
	printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1332
	       s->vga.sr_index, val);
1333 1334
#endif
	break;
B
bellard 已提交
1335
    case 0x17:			// Configuration Readback and Extended Control
1336 1337
	s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
                                   | (val & 0xc7);
B
bellard 已提交
1338 1339
        cirrus_update_memory_access(s);
        break;
1340 1341
    default:
#ifdef DEBUG_CIRRUS
1342 1343
	printf("cirrus: outport sr_index %02x, sr_value %02x\n",
               s->vga.sr_index, val);
1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354
#endif
	break;
    }
}

/***************************************
 *
 *  I/O access at 0x3c6
 *
 ***************************************/

1355
static int cirrus_read_hidden_dac(CirrusVGAState * s)
1356
{
1357
    if (++s->cirrus_hidden_dac_lockindex == 5) {
1358 1359
        s->cirrus_hidden_dac_lockindex = 0;
        return s->cirrus_hidden_dac_data;
1360
    }
1361
    return 0xff;
1362 1363 1364 1365 1366 1367
}

static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
{
    if (s->cirrus_hidden_dac_lockindex == 4) {
	s->cirrus_hidden_dac_data = reg_value;
1368
#if defined(DEBUG_CIRRUS)
1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380
	printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
#endif
    }
    s->cirrus_hidden_dac_lockindex = 0;
}

/***************************************
 *
 *  I/O access at 0x3c9
 *
 ***************************************/

1381
static int cirrus_vga_read_palette(CirrusVGAState * s)
1382
{
1383 1384 1385 1386 1387 1388 1389 1390
    int val;

    if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
        val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
                                       s->vga.dac_sub_index];
    } else {
        val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
    }
1391 1392 1393
    if (++s->vga.dac_sub_index == 3) {
	s->vga.dac_sub_index = 0;
	s->vga.dac_read_index++;
1394
    }
1395
    return val;
1396 1397
}

1398
static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1399
{
1400 1401
    s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
    if (++s->vga.dac_sub_index == 3) {
1402 1403 1404 1405 1406 1407
        if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
            memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
                   s->vga.dac_cache, 3);
        } else {
            memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
        }
1408
        /* XXX update cursor */
1409 1410
	s->vga.dac_sub_index = 0;
	s->vga.dac_write_index++;
1411 1412 1413 1414 1415 1416 1417 1418 1419
    }
}

/***************************************
 *
 *  I/O access between 0x3ce-0x3cf
 *
 ***************************************/

1420
static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1421 1422
{
    switch (reg_index) {
B
bellard 已提交
1423
    case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1424
        return s->cirrus_shadow_gr0;
B
bellard 已提交
1425
    case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1426
        return s->cirrus_shadow_gr1;
1427 1428 1429 1430 1431 1432
    case 0x02:			// Standard VGA
    case 0x03:			// Standard VGA
    case 0x04:			// Standard VGA
    case 0x06:			// Standard VGA
    case 0x07:			// Standard VGA
    case 0x08:			// Standard VGA
1433
        return s->vga.gr[s->vga.gr_index];
1434 1435 1436 1437 1438 1439
    case 0x05:			// Standard VGA, Cirrus extended mode
    default:
	break;
    }

    if (reg_index < 0x3a) {
1440
	return s->vga.gr[reg_index];
1441 1442 1443 1444
    } else {
#ifdef DEBUG_CIRRUS
	printf("cirrus: inport gr_index %02x\n", reg_index);
#endif
1445
	return 0xff;
1446 1447 1448
    }
}

1449 1450
static void
cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1451
{
1452 1453 1454
#if defined(DEBUG_BITBLT) && 0
    printf("gr%02x: %02x\n", reg_index, reg_value);
#endif
1455 1456
    switch (reg_index) {
    case 0x00:			// Standard VGA, BGCOLOR 0x000000ff
1457
	s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
B
bellard 已提交
1458
	s->cirrus_shadow_gr0 = reg_value;
1459
	break;
1460
    case 0x01:			// Standard VGA, FGCOLOR 0x000000ff
1461
	s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
B
bellard 已提交
1462
	s->cirrus_shadow_gr1 = reg_value;
1463
	break;
1464 1465 1466 1467 1468 1469
    case 0x02:			// Standard VGA
    case 0x03:			// Standard VGA
    case 0x04:			// Standard VGA
    case 0x06:			// Standard VGA
    case 0x07:			// Standard VGA
    case 0x08:			// Standard VGA
1470 1471
	s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
        break;
1472
    case 0x05:			// Standard VGA, Cirrus extended mode
1473
	s->vga.gr[reg_index] = reg_value & 0x7f;
B
bellard 已提交
1474
        cirrus_update_memory_access(s);
1475 1476 1477
	break;
    case 0x09:			// bank offset #0
    case 0x0A:			// bank offset #1
1478
	s->vga.gr[reg_index] = reg_value;
B
bellard 已提交
1479 1480
	cirrus_update_bank_ptr(s, 0);
	cirrus_update_bank_ptr(s, 1);
A
aliguori 已提交
1481
        cirrus_update_memory_access(s);
B
bellard 已提交
1482
        break;
1483
    case 0x0B:
1484
	s->vga.gr[reg_index] = reg_value;
1485 1486
	cirrus_update_bank_ptr(s, 0);
	cirrus_update_bank_ptr(s, 1);
B
bellard 已提交
1487
        cirrus_update_memory_access(s);
1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502
	break;
    case 0x10:			// BGCOLOR 0x0000ff00
    case 0x11:			// FGCOLOR 0x0000ff00
    case 0x12:			// BGCOLOR 0x00ff0000
    case 0x13:			// FGCOLOR 0x00ff0000
    case 0x14:			// BGCOLOR 0xff000000
    case 0x15:			// FGCOLOR 0xff000000
    case 0x20:			// BLT WIDTH 0x0000ff
    case 0x22:			// BLT HEIGHT 0x0000ff
    case 0x24:			// BLT DEST PITCH 0x0000ff
    case 0x26:			// BLT SRC PITCH 0x0000ff
    case 0x28:			// BLT DEST ADDR 0x0000ff
    case 0x29:			// BLT DEST ADDR 0x00ff00
    case 0x2c:			// BLT SRC ADDR 0x0000ff
    case 0x2d:			// BLT SRC ADDR 0x00ff00
1503
    case 0x2f:                  // BLT WRITEMASK
1504 1505
    case 0x30:			// BLT MODE
    case 0x32:			// RASTER OP
1506
    case 0x33:			// BLT MODEEXT
1507 1508 1509 1510
    case 0x34:			// BLT TRANSPARENT COLOR 0x00ff
    case 0x35:			// BLT TRANSPARENT COLOR 0xff00
    case 0x38:			// BLT TRANSPARENT COLOR MASK 0x00ff
    case 0x39:			// BLT TRANSPARENT COLOR MASK 0xff00
1511
	s->vga.gr[reg_index] = reg_value;
1512 1513 1514 1515 1516
	break;
    case 0x21:			// BLT WIDTH 0x001f00
    case 0x23:			// BLT HEIGHT 0x001f00
    case 0x25:			// BLT DEST PITCH 0x001f00
    case 0x27:			// BLT SRC PITCH 0x001f00
1517
	s->vga.gr[reg_index] = reg_value & 0x1f;
1518 1519
	break;
    case 0x2a:			// BLT DEST ADDR 0x3f0000
1520
	s->vga.gr[reg_index] = reg_value & 0x3f;
1521
        /* if auto start mode, starts bit blt now */
1522
        if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1523 1524 1525
            cirrus_bitblt_start(s);
        }
	break;
1526
    case 0x2e:			// BLT SRC ADDR 0x3f0000
1527
	s->vga.gr[reg_index] = reg_value & 0x3f;
1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546
	break;
    case 0x31:			// BLT STATUS/START
	cirrus_write_bitblt(s, reg_value);
	break;
    default:
#ifdef DEBUG_CIRRUS
	printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
	       reg_value);
#endif
	break;
    }
}

/***************************************
 *
 *  I/O access between 0x3d4-0x3d5
 *
 ***************************************/

1547
static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574
{
    switch (reg_index) {
    case 0x00:			// Standard VGA
    case 0x01:			// Standard VGA
    case 0x02:			// Standard VGA
    case 0x03:			// Standard VGA
    case 0x04:			// Standard VGA
    case 0x05:			// Standard VGA
    case 0x06:			// Standard VGA
    case 0x07:			// Standard VGA
    case 0x08:			// Standard VGA
    case 0x09:			// Standard VGA
    case 0x0a:			// Standard VGA
    case 0x0b:			// Standard VGA
    case 0x0c:			// Standard VGA
    case 0x0d:			// Standard VGA
    case 0x0e:			// Standard VGA
    case 0x0f:			// Standard VGA
    case 0x10:			// Standard VGA
    case 0x11:			// Standard VGA
    case 0x12:			// Standard VGA
    case 0x13:			// Standard VGA
    case 0x14:			// Standard VGA
    case 0x15:			// Standard VGA
    case 0x16:			// Standard VGA
    case 0x17:			// Standard VGA
    case 0x18:			// Standard VGA
1575
	return s->vga.cr[s->vga.cr_index];
1576
    case 0x24:			// Attribute Controller Toggle Readback (R)
1577
        return (s->vga.ar_flip_flop << 7);
1578 1579 1580 1581 1582 1583 1584 1585
    case 0x19:			// Interlace End
    case 0x1a:			// Miscellaneous Control
    case 0x1b:			// Extended Display Control
    case 0x1c:			// Sync Adjust and Genlock
    case 0x1d:			// Overlay Extended Control
    case 0x22:			// Graphics Data Latches Readback (R)
    case 0x25:			// Part Status
    case 0x27:			// Part ID (R)
1586
	return s->vga.cr[s->vga.cr_index];
1587
    case 0x26:			// Attribute Controller Index Readback (R)
1588
	return s->vga.ar_index & 0x3f;
1589 1590 1591 1592 1593
	break;
    default:
#ifdef DEBUG_CIRRUS
	printf("cirrus: inport cr_index %02x\n", reg_index);
#endif
1594
	return 0xff;
1595 1596 1597
    }
}

1598
static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1599
{
1600
    switch (s->vga.cr_index) {
1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625
    case 0x00:			// Standard VGA
    case 0x01:			// Standard VGA
    case 0x02:			// Standard VGA
    case 0x03:			// Standard VGA
    case 0x04:			// Standard VGA
    case 0x05:			// Standard VGA
    case 0x06:			// Standard VGA
    case 0x07:			// Standard VGA
    case 0x08:			// Standard VGA
    case 0x09:			// Standard VGA
    case 0x0a:			// Standard VGA
    case 0x0b:			// Standard VGA
    case 0x0c:			// Standard VGA
    case 0x0d:			// Standard VGA
    case 0x0e:			// Standard VGA
    case 0x0f:			// Standard VGA
    case 0x10:			// Standard VGA
    case 0x11:			// Standard VGA
    case 0x12:			// Standard VGA
    case 0x13:			// Standard VGA
    case 0x14:			// Standard VGA
    case 0x15:			// Standard VGA
    case 0x16:			// Standard VGA
    case 0x17:			// Standard VGA
    case 0x18:			// Standard VGA
1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645
	/* handle CR0-7 protection */
	if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
	    /* can always write bit 4 of CR7 */
	    if (s->vga.cr_index == 7)
		s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
	    return;
	}
	s->vga.cr[s->vga.cr_index] = reg_value;
	switch(s->vga.cr_index) {
	case 0x00:
	case 0x04:
	case 0x05:
	case 0x06:
	case 0x07:
	case 0x11:
	case 0x17:
	    s->vga.update_retrace_info(&s->vga);
	    break;
	}
        break;
1646 1647 1648 1649
    case 0x19:			// Interlace End
    case 0x1a:			// Miscellaneous Control
    case 0x1b:			// Extended Display Control
    case 0x1c:			// Sync Adjust and Genlock
1650
    case 0x1d:			// Overlay Extended Control
1651
	s->vga.cr[s->vga.cr_index] = reg_value;
1652 1653
#ifdef DEBUG_CIRRUS
	printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1654
	       s->vga.cr_index, reg_value);
1655 1656 1657 1658 1659 1660 1661 1662 1663 1664
#endif
	break;
    case 0x22:			// Graphics Data Latches Readback (R)
    case 0x24:			// Attribute Controller Toggle Readback (R)
    case 0x26:			// Attribute Controller Index Readback (R)
    case 0x27:			// Part ID (R)
	break;
    case 0x25:			// Part Status
    default:
#ifdef DEBUG_CIRRUS
1665 1666
	printf("cirrus: outport cr_index %02x, cr_value %02x\n",
               s->vga.cr_index, reg_value);
1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683
#endif
	break;
    }
}

/***************************************
 *
 *  memory-mapped I/O (bitblt)
 *
 ***************************************/

static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
{
    int value = 0xff;

    switch (address) {
    case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1684
	value = cirrus_vga_read_gr(s, 0x00);
1685 1686
	break;
    case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1687
	value = cirrus_vga_read_gr(s, 0x10);
1688 1689
	break;
    case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1690
	value = cirrus_vga_read_gr(s, 0x12);
1691 1692
	break;
    case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1693
	value = cirrus_vga_read_gr(s, 0x14);
1694 1695
	break;
    case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1696
	value = cirrus_vga_read_gr(s, 0x01);
1697 1698
	break;
    case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1699
	value = cirrus_vga_read_gr(s, 0x11);
1700 1701
	break;
    case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1702
	value = cirrus_vga_read_gr(s, 0x13);
1703 1704
	break;
    case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1705
	value = cirrus_vga_read_gr(s, 0x15);
1706 1707
	break;
    case (CIRRUS_MMIO_BLTWIDTH + 0):
1708
	value = cirrus_vga_read_gr(s, 0x20);
1709 1710
	break;
    case (CIRRUS_MMIO_BLTWIDTH + 1):
1711
	value = cirrus_vga_read_gr(s, 0x21);
1712 1713
	break;
    case (CIRRUS_MMIO_BLTHEIGHT + 0):
1714
	value = cirrus_vga_read_gr(s, 0x22);
1715 1716
	break;
    case (CIRRUS_MMIO_BLTHEIGHT + 1):
1717
	value = cirrus_vga_read_gr(s, 0x23);
1718 1719
	break;
    case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1720
	value = cirrus_vga_read_gr(s, 0x24);
1721 1722
	break;
    case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1723
	value = cirrus_vga_read_gr(s, 0x25);
1724 1725
	break;
    case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1726
	value = cirrus_vga_read_gr(s, 0x26);
1727 1728
	break;
    case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1729
	value = cirrus_vga_read_gr(s, 0x27);
1730 1731
	break;
    case (CIRRUS_MMIO_BLTDESTADDR + 0):
1732
	value = cirrus_vga_read_gr(s, 0x28);
1733 1734
	break;
    case (CIRRUS_MMIO_BLTDESTADDR + 1):
1735
	value = cirrus_vga_read_gr(s, 0x29);
1736 1737
	break;
    case (CIRRUS_MMIO_BLTDESTADDR + 2):
1738
	value = cirrus_vga_read_gr(s, 0x2a);
1739 1740
	break;
    case (CIRRUS_MMIO_BLTSRCADDR + 0):
1741
	value = cirrus_vga_read_gr(s, 0x2c);
1742 1743
	break;
    case (CIRRUS_MMIO_BLTSRCADDR + 1):
1744
	value = cirrus_vga_read_gr(s, 0x2d);
1745 1746
	break;
    case (CIRRUS_MMIO_BLTSRCADDR + 2):
1747
	value = cirrus_vga_read_gr(s, 0x2e);
1748 1749
	break;
    case CIRRUS_MMIO_BLTWRITEMASK:
1750
	value = cirrus_vga_read_gr(s, 0x2f);
1751 1752
	break;
    case CIRRUS_MMIO_BLTMODE:
1753
	value = cirrus_vga_read_gr(s, 0x30);
1754 1755
	break;
    case CIRRUS_MMIO_BLTROP:
1756
	value = cirrus_vga_read_gr(s, 0x32);
1757
	break;
1758
    case CIRRUS_MMIO_BLTMODEEXT:
1759
	value = cirrus_vga_read_gr(s, 0x33);
1760
	break;
1761
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1762
	value = cirrus_vga_read_gr(s, 0x34);
1763 1764
	break;
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1765
	value = cirrus_vga_read_gr(s, 0x35);
1766 1767
	break;
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1768
	value = cirrus_vga_read_gr(s, 0x38);
1769 1770
	break;
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1771
	value = cirrus_vga_read_gr(s, 0x39);
1772 1773
	break;
    case CIRRUS_MMIO_BLTSTATUS:
1774
	value = cirrus_vga_read_gr(s, 0x31);
1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790
	break;
    default:
#ifdef DEBUG_CIRRUS
	printf("cirrus: mmio read - address 0x%04x\n", address);
#endif
	break;
    }

    return (uint8_t) value;
}

static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
				  uint8_t value)
{
    switch (address) {
    case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1791
	cirrus_vga_write_gr(s, 0x00, value);
1792 1793
	break;
    case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1794
	cirrus_vga_write_gr(s, 0x10, value);
1795 1796
	break;
    case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1797
	cirrus_vga_write_gr(s, 0x12, value);
1798 1799
	break;
    case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1800
	cirrus_vga_write_gr(s, 0x14, value);
1801 1802
	break;
    case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1803
	cirrus_vga_write_gr(s, 0x01, value);
1804 1805
	break;
    case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1806
	cirrus_vga_write_gr(s, 0x11, value);
1807 1808
	break;
    case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1809
	cirrus_vga_write_gr(s, 0x13, value);
1810 1811
	break;
    case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1812
	cirrus_vga_write_gr(s, 0x15, value);
1813 1814
	break;
    case (CIRRUS_MMIO_BLTWIDTH + 0):
1815
	cirrus_vga_write_gr(s, 0x20, value);
1816 1817
	break;
    case (CIRRUS_MMIO_BLTWIDTH + 1):
1818
	cirrus_vga_write_gr(s, 0x21, value);
1819 1820
	break;
    case (CIRRUS_MMIO_BLTHEIGHT + 0):
1821
	cirrus_vga_write_gr(s, 0x22, value);
1822 1823
	break;
    case (CIRRUS_MMIO_BLTHEIGHT + 1):
1824
	cirrus_vga_write_gr(s, 0x23, value);
1825 1826
	break;
    case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1827
	cirrus_vga_write_gr(s, 0x24, value);
1828 1829
	break;
    case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1830
	cirrus_vga_write_gr(s, 0x25, value);
1831 1832
	break;
    case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1833
	cirrus_vga_write_gr(s, 0x26, value);
1834 1835
	break;
    case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1836
	cirrus_vga_write_gr(s, 0x27, value);
1837 1838
	break;
    case (CIRRUS_MMIO_BLTDESTADDR + 0):
1839
	cirrus_vga_write_gr(s, 0x28, value);
1840 1841
	break;
    case (CIRRUS_MMIO_BLTDESTADDR + 1):
1842
	cirrus_vga_write_gr(s, 0x29, value);
1843 1844
	break;
    case (CIRRUS_MMIO_BLTDESTADDR + 2):
1845
	cirrus_vga_write_gr(s, 0x2a, value);
1846 1847 1848 1849 1850
	break;
    case (CIRRUS_MMIO_BLTDESTADDR + 3):
	/* ignored */
	break;
    case (CIRRUS_MMIO_BLTSRCADDR + 0):
1851
	cirrus_vga_write_gr(s, 0x2c, value);
1852 1853
	break;
    case (CIRRUS_MMIO_BLTSRCADDR + 1):
1854
	cirrus_vga_write_gr(s, 0x2d, value);
1855 1856
	break;
    case (CIRRUS_MMIO_BLTSRCADDR + 2):
1857
	cirrus_vga_write_gr(s, 0x2e, value);
1858 1859
	break;
    case CIRRUS_MMIO_BLTWRITEMASK:
1860
	cirrus_vga_write_gr(s, 0x2f, value);
1861 1862
	break;
    case CIRRUS_MMIO_BLTMODE:
1863
	cirrus_vga_write_gr(s, 0x30, value);
1864 1865
	break;
    case CIRRUS_MMIO_BLTROP:
1866
	cirrus_vga_write_gr(s, 0x32, value);
1867
	break;
1868
    case CIRRUS_MMIO_BLTMODEEXT:
1869
	cirrus_vga_write_gr(s, 0x33, value);
1870
	break;
1871
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1872
	cirrus_vga_write_gr(s, 0x34, value);
1873 1874
	break;
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1875
	cirrus_vga_write_gr(s, 0x35, value);
1876 1877
	break;
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1878
	cirrus_vga_write_gr(s, 0x38, value);
1879 1880
	break;
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1881
	cirrus_vga_write_gr(s, 0x39, value);
1882 1883
	break;
    case CIRRUS_MMIO_BLTSTATUS:
1884
	cirrus_vga_write_gr(s, 0x31, value);
1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909
	break;
    default:
#ifdef DEBUG_CIRRUS
	printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
	       address, value);
#endif
	break;
    }
}

/***************************************
 *
 *  write mode 4/5
 *
 ***************************************/

static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
					     unsigned mode,
					     unsigned offset,
					     uint32_t mem_value)
{
    int x;
    unsigned val = mem_value;
    uint8_t *dst;

1910
    dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1911 1912
    for (x = 0; x < 8; x++) {
	if (val & 0x80) {
B
bellard 已提交
1913
	    *dst = s->cirrus_shadow_gr1;
1914
	} else if (mode == 5) {
B
bellard 已提交
1915
	    *dst = s->cirrus_shadow_gr0;
1916 1917
	}
	val <<= 1;
B
bellard 已提交
1918
	dst++;
1919
    }
1920
    memory_region_set_dirty(&s->vga.vram, offset, 8);
1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931
}

static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
					      unsigned mode,
					      unsigned offset,
					      uint32_t mem_value)
{
    int x;
    unsigned val = mem_value;
    uint8_t *dst;

1932
    dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1933 1934
    for (x = 0; x < 8; x++) {
	if (val & 0x80) {
B
bellard 已提交
1935
	    *dst = s->cirrus_shadow_gr1;
1936
	    *(dst + 1) = s->vga.gr[0x11];
1937
	} else if (mode == 5) {
B
bellard 已提交
1938
	    *dst = s->cirrus_shadow_gr0;
1939
	    *(dst + 1) = s->vga.gr[0x10];
1940 1941
	}
	val <<= 1;
B
bellard 已提交
1942
	dst += 2;
1943
    }
1944
    memory_region_set_dirty(&s->vga.vram, offset, 16);
1945 1946 1947 1948 1949 1950 1951 1952
}

/***************************************
 *
 *  memory access between 0xa0000-0xbffff
 *
 ***************************************/

1953
static uint64_t cirrus_vga_mem_read(void *opaque,
A
Avi Kivity 已提交
1954
                                    hwaddr addr,
1955
                                    uint32_t size)
1956 1957 1958 1959 1960 1961
{
    CirrusVGAState *s = opaque;
    unsigned bank_index;
    unsigned bank_offset;
    uint32_t val;

1962
    if ((s->vga.sr[0x07] & 0x01) == 0) {
1963
        return vga_mem_readb(&s->vga, addr);
1964 1965 1966 1967 1968 1969 1970 1971 1972
    }

    if (addr < 0x10000) {
	/* XXX handle bitblt */
	/* video memory */
	bank_index = addr >> 15;
	bank_offset = addr & 0x7fff;
	if (bank_offset < s->cirrus_bank_limit[bank_index]) {
	    bank_offset += s->cirrus_bank_base[bank_index];
1973
	    if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
1974
		bank_offset <<= 4;
1975
	    } else if (s->vga.gr[0x0B] & 0x02) {
1976 1977 1978
		bank_offset <<= 3;
	    }
	    bank_offset &= s->cirrus_addr_mask;
1979
	    val = *(s->vga.vram_ptr + bank_offset);
1980 1981 1982 1983 1984
	} else
	    val = 0xff;
    } else if (addr >= 0x18000 && addr < 0x18100) {
	/* memory-mapped I/O */
	val = 0xff;
1985
	if ((s->vga.sr[0x17] & 0x44) == 0x04) {
1986 1987 1988 1989 1990
	    val = cirrus_mmio_blt_read(s, addr & 0xff);
	}
    } else {
	val = 0xff;
#ifdef DEBUG_CIRRUS
1991
	printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
1992 1993 1994 1995 1996
#endif
    }
    return val;
}

1997
static void cirrus_vga_mem_write(void *opaque,
A
Avi Kivity 已提交
1998
                                 hwaddr addr,
1999 2000
                                 uint64_t mem_value,
                                 uint32_t size)
2001 2002 2003 2004 2005 2006
{
    CirrusVGAState *s = opaque;
    unsigned bank_index;
    unsigned bank_offset;
    unsigned mode;

2007
    if ((s->vga.sr[0x07] & 0x01) == 0) {
2008
        vga_mem_writeb(&s->vga, addr, mem_value);
2009 2010 2011 2012 2013 2014 2015
        return;
    }

    if (addr < 0x10000) {
	if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
	    /* bitblt */
	    *s->cirrus_srcptr++ = (uint8_t) mem_value;
2016
	    if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2017 2018 2019 2020 2021 2022 2023 2024
		cirrus_bitblt_cputovideo_next(s);
	    }
	} else {
	    /* video memory */
	    bank_index = addr >> 15;
	    bank_offset = addr & 0x7fff;
	    if (bank_offset < s->cirrus_bank_limit[bank_index]) {
		bank_offset += s->cirrus_bank_base[bank_index];
2025
		if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2026
		    bank_offset <<= 4;
2027
		} else if (s->vga.gr[0x0B] & 0x02) {
2028 2029 2030
		    bank_offset <<= 3;
		}
		bank_offset &= s->cirrus_addr_mask;
2031 2032 2033
		mode = s->vga.gr[0x05] & 0x7;
		if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
		    *(s->vga.vram_ptr + bank_offset) = mem_value;
2034 2035
                    memory_region_set_dirty(&s->vga.vram, bank_offset,
                                            sizeof(mem_value));
2036
		} else {
2037
		    if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050
			cirrus_mem_writeb_mode4and5_8bpp(s, mode,
							 bank_offset,
							 mem_value);
		    } else {
			cirrus_mem_writeb_mode4and5_16bpp(s, mode,
							  bank_offset,
							  mem_value);
		    }
		}
	    }
	}
    } else if (addr >= 0x18000 && addr < 0x18100) {
	/* memory-mapped I/O */
2051
	if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2052 2053 2054 2055
	    cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
	}
    } else {
#ifdef DEBUG_CIRRUS
2056 2057
        printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
               mem_value);
2058 2059 2060 2061
#endif
    }
}

2062 2063 2064 2065
static const MemoryRegionOps cirrus_vga_mem_ops = {
    .read = cirrus_vga_mem_read,
    .write = cirrus_vga_mem_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
2066 2067 2068 2069
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
2070 2071
};

2072 2073 2074 2075 2076 2077 2078 2079 2080
/***************************************
 *
 *  hardware cursor
 *
 ***************************************/

static inline void invalidate_cursor1(CirrusVGAState *s)
{
    if (s->last_hw_cursor_size) {
2081
        vga_invalidate_scanlines(&s->vga,
2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
    }
}

static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
{
    const uint8_t *src;
    uint32_t content;
    int y, y_min, y_max;

2093 2094 2095
    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
        src += (s->vga.sr[0x13] & 0x3c) * 256;
2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111
        y_min = 64;
        y_max = -1;
        for(y = 0; y < 64; y++) {
            content = ((uint32_t *)src)[0] |
                ((uint32_t *)src)[1] |
                ((uint32_t *)src)[2] |
                ((uint32_t *)src)[3];
            if (content) {
                if (y < y_min)
                    y_min = y;
                if (y > y_max)
                    y_max = y;
            }
            src += 16;
        }
    } else {
2112
        src += (s->vga.sr[0x13] & 0x3f) * 256;
2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137
        y_min = 32;
        y_max = -1;
        for(y = 0; y < 32; y++) {
            content = ((uint32_t *)src)[0] |
                ((uint32_t *)(src + 128))[0];
            if (content) {
                if (y < y_min)
                    y_min = y;
                if (y > y_max)
                    y_max = y;
            }
            src += 4;
        }
    }
    if (y_min > y_max) {
        s->last_hw_cursor_y_start = 0;
        s->last_hw_cursor_y_end = 0;
    } else {
        s->last_hw_cursor_y_start = y_min;
        s->last_hw_cursor_y_end = y_max + 1;
    }
}

/* NOTE: we do not currently handle the cursor bitmap change, so we
   update the cursor only if it moves. */
2138
static void cirrus_cursor_invalidate(VGACommonState *s1)
2139
{
2140
    CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2141 2142
    int size;

2143
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2144 2145
        size = 0;
    } else {
2146
        if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2147 2148 2149 2150 2151 2152 2153 2154 2155 2156
            size = 64;
        else
            size = 32;
    }
    /* invalidate last cursor and new cursor if any change */
    if (s->last_hw_cursor_size != size ||
        s->last_hw_cursor_x != s->hw_cursor_x ||
        s->last_hw_cursor_y != s->hw_cursor_y) {

        invalidate_cursor1(s);
2157

2158 2159 2160 2161 2162 2163 2164 2165 2166
        s->last_hw_cursor_size = size;
        s->last_hw_cursor_x = s->hw_cursor_x;
        s->last_hw_cursor_y = s->hw_cursor_y;
        /* compute the real cursor min and max y */
        cirrus_cursor_compute_yrange(s);
        invalidate_cursor1(s);
    }
}

2167 2168 2169 2170 2171 2172 2173 2174 2175
#define DEPTH 8
#include "cirrus_vga_template.h"

#define DEPTH 16
#include "cirrus_vga_template.h"

#define DEPTH 32
#include "cirrus_vga_template.h"

2176
static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2177
{
2178
    CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2179 2180 2181 2182
    int w, h, bpp, x1, x2, poffset;
    unsigned int color0, color1;
    const uint8_t *palette, *src;
    uint32_t content;
2183

2184
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2185 2186
        return;
    /* fast test to see if the cursor intersects with the scan line */
2187
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2188 2189 2190 2191 2192 2193 2194
        h = 64;
    } else {
        h = 32;
    }
    if (scr_y < s->hw_cursor_y ||
        scr_y >= (s->hw_cursor_y + h))
        return;
2195

2196 2197 2198
    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
        src += (s->vga.sr[0x13] & 0x3c) * 256;
2199 2200 2201 2202 2203 2204 2205
        src += (scr_y - s->hw_cursor_y) * 16;
        poffset = 8;
        content = ((uint32_t *)src)[0] |
            ((uint32_t *)src)[1] |
            ((uint32_t *)src)[2] |
            ((uint32_t *)src)[3];
    } else {
2206
        src += (s->vga.sr[0x13] & 0x3f) * 256;
2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217
        src += (scr_y - s->hw_cursor_y) * 4;
        poffset = 128;
        content = ((uint32_t *)src)[0] |
            ((uint32_t *)(src + 128))[0];
    }
    /* if nothing to draw, no need to continue */
    if (!content)
        return;
    w = h;

    x1 = s->hw_cursor_x;
2218
    if (x1 >= s->vga.last_scr_width)
2219 2220
        return;
    x2 = s->hw_cursor_x + w;
2221 2222
    if (x2 > s->vga.last_scr_width)
        x2 = s->vga.last_scr_width;
2223 2224
    w = x2 - x1;
    palette = s->cirrus_hidden_palette;
2225 2226 2227 2228 2229 2230 2231
    color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
                                 c6_to_8(palette[0x0 * 3 + 1]),
                                 c6_to_8(palette[0x0 * 3 + 2]));
    color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
                                 c6_to_8(palette[0xf * 3 + 1]),
                                 c6_to_8(palette[0xf * 3 + 2]));
    bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
2232
    d1 += x1 * bpp;
2233
    switch(ds_get_bits_per_pixel(s->vga.ds)) {
2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250
    default:
        break;
    case 8:
        vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
        break;
    case 15:
        vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
        break;
    case 16:
        vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
        break;
    case 32:
        vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
        break;
    }
}

2251 2252 2253 2254 2255 2256
/***************************************
 *
 *  LFB memory access
 *
 ***************************************/

A
Avi Kivity 已提交
2257
static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
2258
                                   unsigned size)
2259
{
2260
    CirrusVGAState *s = opaque;
2261 2262 2263 2264
    uint32_t ret;

    addr &= s->cirrus_addr_mask;

2265
    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2266
        ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2267 2268 2269 2270 2271 2272 2273
	/* memory-mapped I/O */
	ret = cirrus_mmio_blt_read(s, addr & 0xff);
    } else if (0) {
	/* XXX handle bitblt */
	ret = 0xff;
    } else {
	/* video memory */
2274
	if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2275
	    addr <<= 4;
2276
	} else if (s->vga.gr[0x0B] & 0x02) {
2277 2278 2279
	    addr <<= 3;
	}
	addr &= s->cirrus_addr_mask;
2280
	ret = *(s->vga.vram_ptr + addr);
2281 2282 2283 2284 2285
    }

    return ret;
}

A
Avi Kivity 已提交
2286
static void cirrus_linear_write(void *opaque, hwaddr addr,
2287
                                uint64_t val, unsigned size)
2288
{
2289
    CirrusVGAState *s = opaque;
2290 2291 2292
    unsigned mode;

    addr &= s->cirrus_addr_mask;
2293

2294
    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2295
        ((addr & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {
2296 2297 2298 2299 2300
	/* memory-mapped I/O */
	cirrus_mmio_blt_write(s, addr & 0xff, val);
    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
	/* bitblt */
	*s->cirrus_srcptr++ = (uint8_t) val;
2301
	if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2302 2303 2304 2305
	    cirrus_bitblt_cputovideo_next(s);
	}
    } else {
	/* video memory */
2306
	if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2307
	    addr <<= 4;
2308
	} else if (s->vga.gr[0x0B] & 0x02) {
2309 2310 2311 2312
	    addr <<= 3;
	}
	addr &= s->cirrus_addr_mask;

2313 2314 2315
	mode = s->vga.gr[0x05] & 0x7;
	if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
	    *(s->vga.vram_ptr + addr) = (uint8_t) val;
2316
            memory_region_set_dirty(&s->vga.vram, addr, 1);
2317
	} else {
2318
	    if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2319 2320 2321 2322 2323 2324 2325 2326
		cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
	    } else {
		cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
	    }
	}
    }
}

2327 2328 2329 2330 2331 2332 2333
/***************************************
 *
 *  system to screen memory access
 *
 ***************************************/


2334
static uint64_t cirrus_linear_bitblt_read(void *opaque,
A
Avi Kivity 已提交
2335
                                          hwaddr addr,
2336
                                          unsigned size)
2337
{
2338
    CirrusVGAState *s = opaque;
2339 2340 2341
    uint32_t ret;

    /* XXX handle bitblt */
2342
    (void)s;
2343 2344 2345 2346
    ret = 0xff;
    return ret;
}

2347
static void cirrus_linear_bitblt_write(void *opaque,
A
Avi Kivity 已提交
2348
                                       hwaddr addr,
2349 2350
                                       uint64_t val,
                                       unsigned size)
2351
{
2352
    CirrusVGAState *s = opaque;
2353 2354 2355 2356 2357 2358 2359 2360 2361 2362

    if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
	/* bitblt */
	*s->cirrus_srcptr++ = (uint8_t) val;
	if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
	    cirrus_bitblt_cputovideo_next(s);
	}
    }
}

2363 2364 2365 2366
static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
    .read = cirrus_linear_bitblt_read,
    .write = cirrus_linear_bitblt_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
2367 2368 2369 2370
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
2371 2372
};

2373 2374
static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
{
2375 2376
    MemoryRegion *mr = &s->cirrus_bank[bank];
    bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2377 2378
        && !((s->vga.sr[0x07] & 0x01) == 0)
        && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2379 2380 2381 2382
        && !(s->vga.gr[0x0B] & 0x02);

    memory_region_set_enabled(mr, enabled);
    memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
2383
}
A
aliguori 已提交
2384

2385 2386
static void map_linear_vram(CirrusVGAState *s)
{
J
Jan Kiszka 已提交
2387
    if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
2388 2389 2390 2391 2392
        s->linear_vram = true;
        memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
    }
    map_linear_vram_bank(s, 0);
    map_linear_vram_bank(s, 1);
A
aliguori 已提交
2393 2394 2395 2396
}

static void unmap_linear_vram(CirrusVGAState *s)
{
J
Jan Kiszka 已提交
2397
    if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
2398 2399
        s->linear_vram = false;
        memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
2400
    }
2401 2402
    memory_region_set_enabled(&s->cirrus_bank[0], false);
    memory_region_set_enabled(&s->cirrus_bank[1], false);
A
aliguori 已提交
2403 2404
}

B
bellard 已提交
2405 2406 2407 2408 2409
/* Compute the memory access functions */
static void cirrus_update_memory_access(CirrusVGAState *s)
{
    unsigned mode;

2410
    memory_region_transaction_begin();
2411
    if ((s->vga.sr[0x17] & 0x44) == 0x44) {
B
bellard 已提交
2412 2413 2414 2415
        goto generic_io;
    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
        goto generic_io;
    } else {
2416
	if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
B
bellard 已提交
2417
            goto generic_io;
2418
	} else if (s->vga.gr[0x0B] & 0x02) {
B
bellard 已提交
2419 2420
            goto generic_io;
        }
2421

2422 2423
	mode = s->vga.gr[0x05] & 0x7;
	if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
A
aliguori 已提交
2424
            map_linear_vram(s);
B
bellard 已提交
2425 2426
        } else {
        generic_io:
A
aliguori 已提交
2427
            unmap_linear_vram(s);
B
bellard 已提交
2428 2429
        }
    }
2430
    memory_region_transaction_commit();
B
bellard 已提交
2431 2432 2433
}


2434 2435
/* I/O ports */

2436 2437
static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
                                       unsigned size)
2438
{
2439 2440
    CirrusVGAState *c = opaque;
    VGACommonState *s = &c->vga;
2441 2442
    int val, index;

2443
    qemu_flush_coalesced_mmio_buffer();
2444
    addr += 0x3b0;
2445

2446
    if (vga_ioport_invalid(s, addr)) {
2447 2448 2449 2450
	val = 0xff;
    } else {
	switch (addr) {
	case 0x3c0:
2451 2452
	    if (s->ar_flip_flop == 0) {
		val = s->ar_index;
2453 2454 2455 2456 2457
	    } else {
		val = 0;
	    }
	    break;
	case 0x3c1:
2458
	    index = s->ar_index & 0x1f;
2459
	    if (index < 21)
2460
		val = s->ar[index];
2461 2462 2463 2464
	    else
		val = 0;
	    break;
	case 0x3c2:
2465
	    val = s->st00;
2466 2467
	    break;
	case 0x3c4:
2468
	    val = s->sr_index;
2469 2470
	    break;
	case 0x3c5:
2471 2472
	    val = cirrus_vga_read_sr(c);
            break;
2473
#ifdef DEBUG_VGA_REG
2474
	    printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2475 2476 2477
#endif
	    break;
	case 0x3c6:
2478
	    val = cirrus_read_hidden_dac(c);
2479 2480
	    break;
	case 0x3c7:
2481
	    val = s->dac_state;
2482
	    break;
2483
	case 0x3c8:
2484 2485
	    val = s->dac_write_index;
	    c->cirrus_hidden_dac_lockindex = 0;
2486 2487
	    break;
        case 0x3c9:
2488 2489
            val = cirrus_vga_read_palette(c);
            break;
2490
	case 0x3ca:
2491
	    val = s->fcr;
2492 2493
	    break;
	case 0x3cc:
2494
	    val = s->msr;
2495 2496
	    break;
	case 0x3ce:
2497
	    val = s->gr_index;
2498 2499
	    break;
	case 0x3cf:
2500
	    val = cirrus_vga_read_gr(c, s->gr_index);
2501
#ifdef DEBUG_VGA_REG
2502
	    printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2503 2504 2505 2506
#endif
	    break;
	case 0x3b4:
	case 0x3d4:
2507
	    val = s->cr_index;
2508 2509 2510
	    break;
	case 0x3b5:
	case 0x3d5:
2511
            val = cirrus_vga_read_cr(c, s->cr_index);
2512
#ifdef DEBUG_VGA_REG
2513
	    printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2514 2515 2516 2517 2518
#endif
	    break;
	case 0x3ba:
	case 0x3da:
	    /* just toggle to fool polling */
2519 2520
	    val = s->st01 = s->retrace(s);
	    s->ar_flip_flop = 0;
2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532
	    break;
	default:
	    val = 0x00;
	    break;
	}
    }
#if defined(DEBUG_VGA)
    printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
#endif
    return val;
}

2533 2534
static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
                                    unsigned size)
2535
{
2536 2537
    CirrusVGAState *c = opaque;
    VGACommonState *s = &c->vga;
2538 2539
    int index;

2540
    qemu_flush_coalesced_mmio_buffer();
2541
    addr += 0x3b0;
2542

2543
    /* check port range access depending on color/monochrome mode */
2544
    if (vga_ioport_invalid(s, addr)) {
2545
	return;
2546
    }
2547 2548 2549 2550 2551 2552
#ifdef DEBUG_VGA
    printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
#endif

    switch (addr) {
    case 0x3c0:
2553
	if (s->ar_flip_flop == 0) {
2554
	    val &= 0x3f;
2555
	    s->ar_index = val;
2556
	} else {
2557
	    index = s->ar_index & 0x1f;
2558 2559
	    switch (index) {
	    case 0x00 ... 0x0f:
2560
		s->ar[index] = val & 0x3f;
2561 2562
		break;
	    case 0x10:
2563
		s->ar[index] = val & ~0x10;
2564 2565
		break;
	    case 0x11:
2566
		s->ar[index] = val;
2567 2568
		break;
	    case 0x12:
2569
		s->ar[index] = val & ~0xc0;
2570 2571
		break;
	    case 0x13:
2572
		s->ar[index] = val & ~0xf0;
2573 2574
		break;
	    case 0x14:
2575
		s->ar[index] = val & ~0xf0;
2576 2577 2578 2579 2580
		break;
	    default:
		break;
	    }
	}
2581
	s->ar_flip_flop ^= 1;
2582 2583
	break;
    case 0x3c2:
2584 2585
	s->msr = val & ~0x10;
	s->update_retrace_info(s);
2586 2587
	break;
    case 0x3c4:
2588
	s->sr_index = val;
2589 2590 2591
	break;
    case 0x3c5:
#ifdef DEBUG_VGA_REG
2592
	printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2593
#endif
2594 2595
	cirrus_vga_write_sr(c, val);
        break;
2596 2597
	break;
    case 0x3c6:
2598
	cirrus_write_hidden_dac(c, val);
2599 2600
	break;
    case 0x3c7:
2601 2602 2603
	s->dac_read_index = val;
	s->dac_sub_index = 0;
	s->dac_state = 3;
2604 2605
	break;
    case 0x3c8:
2606 2607 2608
	s->dac_write_index = val;
	s->dac_sub_index = 0;
	s->dac_state = 0;
2609 2610
	break;
    case 0x3c9:
2611 2612
        cirrus_vga_write_palette(c, val);
        break;
2613
    case 0x3ce:
2614
	s->gr_index = val;
2615 2616 2617
	break;
    case 0x3cf:
#ifdef DEBUG_VGA_REG
2618
	printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2619
#endif
2620
	cirrus_vga_write_gr(c, s->gr_index, val);
2621 2622 2623
	break;
    case 0x3b4:
    case 0x3d4:
2624
	s->cr_index = val;
2625 2626 2627 2628
	break;
    case 0x3b5:
    case 0x3d5:
#ifdef DEBUG_VGA_REG
2629
	printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2630
#endif
2631
	cirrus_vga_write_cr(c, val);
2632 2633 2634
	break;
    case 0x3ba:
    case 0x3da:
2635
	s->fcr = val & 0x10;
2636 2637 2638 2639
	break;
    }
}

2640 2641 2642 2643 2644 2645
/***************************************
 *
 *  memory-mapped I/O access
 *
 ***************************************/

A
Avi Kivity 已提交
2646
static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
2647
                                 unsigned size)
2648
{
2649
    CirrusVGAState *s = opaque;
2650 2651 2652 2653

    if (addr >= 0x100) {
        return cirrus_mmio_blt_read(s, addr - 0x100);
    } else {
2654
        return cirrus_vga_ioport_read(s, addr + 0x10, size);
2655 2656 2657
    }
}

A
Avi Kivity 已提交
2658
static void cirrus_mmio_write(void *opaque, hwaddr addr,
2659
                              uint64_t val, unsigned size)
2660
{
2661
    CirrusVGAState *s = opaque;
2662 2663 2664 2665

    if (addr >= 0x100) {
	cirrus_mmio_blt_write(s, addr - 0x100, val);
    } else {
2666
        cirrus_vga_ioport_write(s, addr + 0x10, val, size);
2667 2668 2669
    }
}

2670 2671 2672 2673
static const MemoryRegionOps cirrus_mmio_io_ops = {
    .read = cirrus_mmio_read,
    .write = cirrus_mmio_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
2674 2675 2676 2677
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
2678 2679
};

B
bellard 已提交
2680 2681
/* load/save state */

2682
static int cirrus_post_load(void *opaque, int version_id)
B
bellard 已提交
2683 2684 2685
{
    CirrusVGAState *s = opaque;

2686 2687
    s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
    s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
B
bellard 已提交
2688

A
aliguori 已提交
2689
    cirrus_update_memory_access(s);
B
bellard 已提交
2690
    /* force refresh */
2691
    s->vga.graphic_mode = -1;
B
bellard 已提交
2692 2693 2694 2695 2696
    cirrus_update_bank_ptr(s, 0);
    cirrus_update_bank_ptr(s, 1);
    return 0;
}

J
Juan Quintela 已提交
2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733
static const VMStateDescription vmstate_cirrus_vga = {
    .name = "cirrus_vga",
    .version_id = 2,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = cirrus_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(vga.latch, CirrusVGAState),
        VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
        VMSTATE_BUFFER(vga.sr, CirrusVGAState),
        VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
        VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
        VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
        VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
        VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
        VMSTATE_BUFFER(vga.ar, CirrusVGAState),
        VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
        VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
        VMSTATE_BUFFER(vga.cr, CirrusVGAState),
        VMSTATE_UINT8(vga.msr, CirrusVGAState),
        VMSTATE_UINT8(vga.fcr, CirrusVGAState),
        VMSTATE_UINT8(vga.st00, CirrusVGAState),
        VMSTATE_UINT8(vga.st01, CirrusVGAState),
        VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
        VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
        VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
        VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
        VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
        VMSTATE_BUFFER(vga.palette, CirrusVGAState),
        VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
        VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
        VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
        VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
        VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
        /* XXX: we do not save the bitblt state - we assume we do not save
           the state when the blitter is active */
        VMSTATE_END_OF_LIST()
2734
    }
J
Juan Quintela 已提交
2735
};
2736

J
Juan Quintela 已提交
2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748
static const VMStateDescription vmstate_pci_cirrus_vga = {
    .name = "cirrus_vga",
    .version_id = 2,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
        VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
                       vmstate_cirrus_vga, CirrusVGAState),
        VMSTATE_END_OF_LIST()
    }
};
2749

2750 2751 2752 2753 2754 2755
/***************************************
 *
 *  initialize
 *
 ***************************************/

B
blueswir1 已提交
2756
static void cirrus_reset(void *opaque)
2757
{
B
blueswir1 已提交
2758
    CirrusVGAState *s = opaque;
2759

2760
    vga_common_reset(&s->vga);
2761
    unmap_linear_vram(s);
2762
    s->vga.sr[0x06] = 0x0f;
B
blueswir1 已提交
2763
    if (s->device_id == CIRRUS_ID_CLGD5446) {
2764
        /* 4MB 64 bit memory config, always PCI */
2765 2766 2767 2768 2769
        s->vga.sr[0x1F] = 0x2d;		// MemClock
        s->vga.gr[0x18] = 0x0f;             // fastest memory configuration
        s->vga.sr[0x0f] = 0x98;
        s->vga.sr[0x17] = 0x20;
        s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2770
    } else {
2771 2772 2773 2774
        s->vga.sr[0x1F] = 0x22;		// MemClock
        s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
        s->vga.sr[0x17] = s->bustype;
        s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2775
    }
2776
    s->vga.cr[0x27] = s->device_id;
2777 2778 2779

    s->cirrus_hidden_dac_lockindex = 5;
    s->cirrus_hidden_dac_data = 0;
B
blueswir1 已提交
2780 2781
}

2782 2783 2784 2785
static const MemoryRegionOps cirrus_linear_io_ops = {
    .read = cirrus_linear_read,
    .write = cirrus_linear_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
2786 2787 2788 2789
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
2790 2791
};

2792 2793 2794 2795 2796 2797 2798 2799 2800 2801
static const MemoryRegionOps cirrus_vga_io_ops = {
    .read = cirrus_vga_ioport_read,
    .write = cirrus_vga_ioport_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

2802
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
2803 2804
                               MemoryRegion *system_memory,
                               MemoryRegion *system_io)
B
blueswir1 已提交
2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835
{
    int i;
    static int inited;

    if (!inited) {
        inited = 1;
        for(i = 0;i < 256; i++)
            rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
        rop_to_index[CIRRUS_ROP_0] = 0;
        rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
        rop_to_index[CIRRUS_ROP_NOP] = 2;
        rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
        rop_to_index[CIRRUS_ROP_NOTDST] = 4;
        rop_to_index[CIRRUS_ROP_SRC] = 5;
        rop_to_index[CIRRUS_ROP_1] = 6;
        rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
        rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
        rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
        rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
        rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
        rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
        rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
        rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
        rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
        s->device_id = device_id;
        if (is_pci)
            s->bustype = CIRRUS_BUSTYPE_PCI;
        else
            s->bustype = CIRRUS_BUSTYPE_ISA;
    }

2836 2837 2838 2839
    /* Register ioport 0x3b0 - 0x3df */
    memory_region_init_io(&s->cirrus_vga_io, &cirrus_vga_io_ops, s,
                          "cirrus-io", 0x30);
    memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
B
blueswir1 已提交
2840

2841 2842 2843 2844 2845 2846 2847
    memory_region_init(&s->low_mem_container,
                       "cirrus-lowmem-container",
                       0x20000);

    memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
                          "cirrus-low-memory", 0x20000);
    memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2848 2849 2850 2851 2852 2853 2854 2855
    for (i = 0; i < 2; ++i) {
        static const char *names[] = { "vga.bank0", "vga.bank1" };
        MemoryRegion *bank = &s->cirrus_bank[i];
        memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000);
        memory_region_set_enabled(bank, false);
        memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
                                            bank, 1);
    }
2856
    memory_region_add_subregion_overlap(system_memory,
2857 2858 2859 2860
                                        isa_mem_base + 0x000a0000,
                                        &s->low_mem_container,
                                        1);
    memory_region_set_coalescing(&s->low_mem);
B
bellard 已提交
2861

2862
    /* I/O handler for LFB */
2863
    memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
2864 2865
                          "cirrus-linear-io", s->vga.vram_size_mb
                                              * 1024 * 1024);
2866
    memory_region_set_flush_coalesced(&s->cirrus_linear_io);
2867 2868

    /* I/O handler for LFB */
2869 2870 2871 2872 2873
    memory_region_init_io(&s->cirrus_linear_bitblt_io,
                          &cirrus_linear_bitblt_io_ops,
                          s,
                          "cirrus-bitblt-mmio",
                          0x400000);
2874
    memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
2875 2876

    /* I/O handler for memory-mapped I/O */
2877 2878
    memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
                          "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
2879
    memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
2880 2881 2882 2883

    s->real_vram_size =
        (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;

2884
    /* XXX: s->vga.vram_size must be a power of two */
2885 2886 2887
    s->cirrus_addr_mask = s->real_vram_size - 1;
    s->linear_mmio_mask = s->real_vram_size - 256;

2888 2889 2890 2891 2892
    s->vga.get_bpp = cirrus_get_bpp;
    s->vga.get_offsets = cirrus_get_offsets;
    s->vga.get_resolution = cirrus_get_resolution;
    s->vga.cursor_invalidate = cirrus_cursor_invalidate;
    s->vga.cursor_draw_line = cirrus_cursor_draw_line;
2893

2894
    qemu_register_reset(cirrus_reset, s);
2895 2896 2897 2898 2899 2900 2901 2902
}

/***************************************
 *
 *  ISA bus support
 *
 ***************************************/

2903
static int vga_initfn(ISADevice *dev)
2904
{
2905 2906 2907
    ISACirrusVGAState *d = DO_UPCAST(ISACirrusVGAState, dev, dev);
    VGACommonState *s = &d->cirrus_vga.vga;

G
Gerd Hoffmann 已提交
2908
    vga_common_init(s);
2909
    cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
2910
                       isa_address_space(dev), isa_address_space_io(dev));
2911 2912 2913
    s->ds = graphic_console_init(s->update, s->invalidate,
                                 s->screen_dump, s->text_update,
                                 s);
2914
    rom_add_vga(VGABIOS_CIRRUS_FILENAME);
2915
    /* XXX ISA-LFB support */
2916
    /* FIXME not qdev yet */
2917 2918 2919
    return 0;
}

2920 2921 2922 2923 2924 2925
static Property isa_vga_cirrus_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
                       cirrus_vga.vga.vram_size_mb, 8),
    DEFINE_PROP_END_OF_LIST(),
};

2926 2927 2928
static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
{
    ISADeviceClass *k = ISA_DEVICE_CLASS(klass);
2929
    DeviceClass *dc = DEVICE_CLASS(klass);
2930

2931 2932
    dc->vmsd  = &vmstate_cirrus_vga;
    k->init   = vga_initfn;
2933
    dc->props = isa_vga_cirrus_properties;
2934 2935
}

2936 2937 2938 2939
static TypeInfo isa_cirrus_vga_info = {
    .name          = "isa-cirrus-vga",
    .parent        = TYPE_ISA_DEVICE,
    .instance_size = sizeof(ISACirrusVGAState),
2940
    .class_init = isa_cirrus_vga_class_init,
2941 2942
};

2943 2944 2945 2946 2947 2948
/***************************************
 *
 *  PCI bus support
 *
 ***************************************/

2949
static int pci_cirrus_vga_initfn(PCIDevice *dev)
G
Gerd Hoffmann 已提交
2950 2951 2952
{
     PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
     CirrusVGAState *s = &d->cirrus_vga;
2953 2954
     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
     int16_t device_id = pc->device_id;
G
Gerd Hoffmann 已提交
2955 2956

     /* setup VGA */
G
Gerd Hoffmann 已提交
2957
     vga_common_init(&s->vga);
2958 2959
     cirrus_init_common(s, device_id, 1, pci_address_space(dev),
                        pci_address_space_io(dev));
G
Gerd Hoffmann 已提交
2960 2961 2962 2963 2964 2965
     s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
                                      s->vga.screen_dump, s->vga.text_update,
                                      &s->vga);

     /* setup PCI */

2966 2967 2968 2969 2970 2971 2972
    memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);

    /* XXX: add byte swapping apertures */
    memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
    memory_region_add_subregion(&s->pci_bar, 0x1000000,
                                &s->cirrus_linear_bitblt_io);

G
Gerd Hoffmann 已提交
2973 2974 2975 2976
     /* setup memory space */
     /* memory #0 LFB */
     /* memory #1 memory-mapped I/O */
     /* XXX: s->vga.vram_size must be a power of two */
2977
     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
G
Gerd Hoffmann 已提交
2978
     if (device_id == CIRRUS_ID_CLGD5446) {
2979
         pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
G
Gerd Hoffmann 已提交
2980
     }
2981
     return 0;
G
Gerd Hoffmann 已提交
2982 2983
}

2984 2985 2986 2987 2988 2989
static Property pci_vga_cirrus_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
                       cirrus_vga.vga.vram_size_mb, 8),
    DEFINE_PROP_END_OF_LIST(),
};

2990 2991
static void cirrus_vga_class_init(ObjectClass *klass, void *data)
{
2992
    DeviceClass *dc = DEVICE_CLASS(klass);
2993 2994 2995 2996 2997 2998 2999 3000
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->no_hotplug = 1;
    k->init = pci_cirrus_vga_initfn;
    k->romfile = VGABIOS_CIRRUS_FILENAME;
    k->vendor_id = PCI_VENDOR_ID_CIRRUS;
    k->device_id = CIRRUS_ID_CLGD5446;
    k->class_id = PCI_CLASS_DISPLAY_VGA;
3001 3002
    dc->desc = "Cirrus CLGD 54xx VGA";
    dc->vmsd = &vmstate_pci_cirrus_vga;
3003
    dc->props = pci_vga_cirrus_properties;
3004 3005
}

3006 3007 3008 3009 3010
static TypeInfo cirrus_vga_info = {
    .name          = "cirrus-vga",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCICirrusVGAState),
    .class_init    = cirrus_vga_class_init,
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Gerd Hoffmann 已提交
3011
};
3012

A
Andreas Färber 已提交
3013
static void cirrus_vga_register_types(void)
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Gerd Hoffmann 已提交
3014
{
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Andreas Färber 已提交
3015
    type_register_static(&isa_cirrus_vga_info);
3016
    type_register_static(&cirrus_vga_info);
3017
}
A
Andreas Färber 已提交
3018 3019

type_init(cirrus_vga_register_types)