pci.c 43.0 KB
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/*
 * QEMU PCI bus manager
 *
 * Copyright (c) 2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
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#include "hw.h"
#include "pci.h"
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#include "monitor.h"
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#include "net.h"
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#include "sysemu.h"
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
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#else
# define PCI_DPRINTF(format, ...)       do { } while (0)
#endif
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struct PCIBus {
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    BusState qbus;
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    int devfn_min;
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    pci_set_irq_fn set_irq;
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    pci_map_irq_fn map_irq;
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    pci_hotplug_fn hotplug;
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    uint32_t config_reg; /* XXX: suppress */
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    void *irq_opaque;
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    PCIDevice *devices[256];
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    PCIDevice *parent_dev;
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    QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
    QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */

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    /* The bus IRQ state is the logical OR of the connected devices.
       Keep a count of the number of devices with raised IRQs.  */
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    int nirq;
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    int *irq_count;
};

static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);

static struct BusInfo pci_bus_info = {
    .name       = "PCI",
    .size       = sizeof(PCIBus),
    .print_dev  = pcibus_dev_print,
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    .props      = (Property[]) {
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        DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
        DEFINE_PROP_END_OF_LIST()
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    }
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};
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static void pci_update_mappings(PCIDevice *d);
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static void pci_set_irq(void *opaque, int irq_num, int level);
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target_phys_addr_t pci_mem_base;
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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struct PCIHostBus {
    int domain;
    struct PCIBus *bus;
    QLIST_ENTRY(PCIHostBus) next;
};
static QLIST_HEAD(, PCIHostBus) host_buses;
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static const VMStateDescription vmstate_pcibus = {
    .name = "PCIBUS",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_INT32_EQUAL(nirq, PCIBus),
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        VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static int pci_bar(PCIDevice *d, int reg)
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{
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    uint8_t type;

    if (reg != PCI_ROM_SLOT)
        return PCI_BASE_ADDRESS_0 + reg * 4;

    type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
    return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
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}

static void pci_device_reset(PCIDevice *dev)
{
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    int r;

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    memset(dev->irq_state, 0, sizeof dev->irq_state);
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    dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
                                  PCI_COMMAND_MASTER);
    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
    dev->config[PCI_INTERRUPT_LINE] = 0x0;
    for (r = 0; r < PCI_NUM_REGIONS; ++r) {
        if (!dev->io_regions[r].size) {
            continue;
        }
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        pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
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    }
    pci_update_mappings(dev);
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}

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static void pci_bus_reset(void *opaque)
{
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    PCIBus *bus = opaque;
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    int i;

    for (i = 0; i < bus->nirq; i++) {
        bus->irq_count[i] = 0;
    }
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    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
        if (bus->devices[i]) {
            pci_device_reset(bus->devices[i]);
        }
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    }
}

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static void pci_host_bus_register(int domain, PCIBus *bus)
{
    struct PCIHostBus *host;
    host = qemu_mallocz(sizeof(*host));
    host->domain = domain;
    host->bus = bus;
    QLIST_INSERT_HEAD(&host_buses, host, next);
}

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PCIBus *pci_find_root_bus(int domain)
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{
    struct PCIHostBus *host;

    QLIST_FOREACH(host, &host_buses, next) {
        if (host->domain == domain) {
            return host->bus;
        }
    }

    return NULL;
}

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void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
                         const char *name, int devfn_min)
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{
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    static int nbus = 0;

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    qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
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    bus->devfn_min = devfn_min;
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    /* host bridge */
    QLIST_INIT(&bus->child);
    pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */

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    vmstate_register(nbus++, &vmstate_pcibus, bus);
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    qemu_register_reset(pci_bus_reset, bus);
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}

PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
{
    PCIBus *bus;

    bus = qemu_mallocz(sizeof(*bus));
    bus->qbus.qdev_allocated = 1;
    pci_bus_new_inplace(bus, parent, name, devfn_min);
    return bus;
}

void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                  void *irq_opaque, int nirq)
{
    bus->set_irq = set_irq;
    bus->map_irq = map_irq;
    bus->irq_opaque = irq_opaque;
    bus->nirq = nirq;
    bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
}

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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
{
    bus->qbus.allow_hotplug = 1;
    bus->hotplug = hotplug;
}

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PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                         void *irq_opaque, int devfn_min, int nirq)
{
    PCIBus *bus;

    bus = pci_bus_new(parent, name, devfn_min);
    pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
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    return bus;
}
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static void pci_register_secondary_bus(PCIBus *parent,
                                       PCIBus *bus,
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                                       PCIDevice *dev,
                                       pci_map_irq_fn map_irq,
                                       const char *name)
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{
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    qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
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    bus->map_irq = map_irq;
    bus->parent_dev = dev;
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    QLIST_INIT(&bus->child);
    QLIST_INSERT_HEAD(&parent->child, bus, sibling);
}

static void pci_unregister_secondary_bus(PCIBus *bus)
{
    assert(QLIST_EMPTY(&bus->child));
    QLIST_REMOVE(bus, sibling);
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}

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int pci_bus_num(PCIBus *s)
{
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    if (!s->parent_dev)
        return 0;       /* pci host bridge */
    return s->parent_dev->config[PCI_SECONDARY_BUS];
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}

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static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
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{
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    PCIDevice *s = container_of(pv, PCIDevice, config);
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    uint8_t *config;
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    int i;

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    assert(size == pci_config_size(s));
    config = qemu_malloc(size);

    qemu_get_buffer(f, config, size);
    for (i = 0; i < size; ++i) {
        if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
            qemu_free(config);
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            return -EINVAL;
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        }
    }
    memcpy(s->config, config, size);
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    pci_update_mappings(s);
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    qemu_free(config);
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    return 0;
}

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/* just put buffer */
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static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
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{
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    const uint8_t **v = pv;
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    assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
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    qemu_put_buffer(f, *v, size);
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}

static VMStateInfo vmstate_info_pci_config = {
    .name = "pci config",
    .get  = get_pci_config_device,
    .put  = put_pci_config_device,
};

const VMStateDescription vmstate_pci_device = {
    .name = "PCIDevice",
    .version_id = 2,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_INT32_LE(version_id, PCIDevice),
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        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
                                   vmstate_info_pci_config,
                                   PCI_CONFIG_SPACE_SIZE),
        VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_pcie_device = {
    .name = "PCIDevice",
    .version_id = 2,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_INT32_LE(version_id, PCIDevice),
        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
                                   vmstate_info_pci_config,
                                   PCIE_CONFIG_SPACE_SIZE),
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        VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
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        VMSTATE_END_OF_LIST()
    }
};

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static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
{
    return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
}

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void pci_device_save(PCIDevice *s, QEMUFile *f)
{
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    vmstate_save_state(f, pci_get_vmstate(s), s);
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}

int pci_device_load(PCIDevice *s, QEMUFile *f)
{
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    return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
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}

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static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
{
    uint16_t *id;

    id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
    id[0] = cpu_to_le16(pci_default_sub_vendor_id);
    id[1] = cpu_to_le16(pci_default_sub_device_id);
    return 0;
}

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/*
 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 */
static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
{
    const char *p;
    char *e;
    unsigned long val;
    unsigned long dom = 0, bus = 0;
    unsigned slot = 0;

    p = addr;
    val = strtoul(p, &e, 16);
    if (e == p)
	return -1;
    if (*e == ':') {
	bus = val;
	p = e + 1;
	val = strtoul(p, &e, 16);
	if (e == p)
	    return -1;
	if (*e == ':') {
	    dom = bus;
	    bus = val;
	    p = e + 1;
	    val = strtoul(p, &e, 16);
	    if (e == p)
		return -1;
	}
    }

    if (dom > 0xffff || bus > 0xff || val > 0x1f)
	return -1;

    slot = val;

    if (*e)
	return -1;

    /* Note: QEMU doesn't implement domains other than 0 */
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    if (!pci_find_bus(pci_find_root_bus(dom), bus))
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	return -1;

    *domp = dom;
    *busp = bus;
    *slotp = slot;
    return 0;
}

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int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
                     unsigned *slotp)
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{
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    /* strip legacy tag */
    if (!strncmp(addr, "pci_addr=", 9)) {
        addr += 9;
    }
    if (pci_parse_devaddr(addr, domp, busp, slotp)) {
        monitor_printf(mon, "Invalid pci address\n");
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        return -1;
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    }
    return 0;
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}

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PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
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{
    int dom, bus;
    unsigned slot;

    if (!devaddr) {
        *devfnp = -1;
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        return pci_find_bus(pci_find_root_bus(0), 0);
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    }

    if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
        return NULL;
    }

    *devfnp = slot << 3;
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    return pci_find_bus(pci_find_root_bus(0), bus);
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}

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static void pci_init_cmask(PCIDevice *dev)
{
    pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
    pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
    dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
    dev->cmask[PCI_REVISION_ID] = 0xff;
    dev->cmask[PCI_CLASS_PROG] = 0xff;
    pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
    dev->cmask[PCI_HEADER_TYPE] = 0xff;
    dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
}

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static void pci_init_wmask(PCIDevice *dev)
{
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    int config_size = pci_config_size(dev);

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    dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
    dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
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    pci_set_word(dev->wmask + PCI_COMMAND,
                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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    memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
           config_size - PCI_CONFIG_HEADER_SIZE);
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}

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static void pci_init_wmask_bridge(PCIDevice *d)
{
    /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
       PCI_SEC_LETENCY_TIMER */
    memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);

    /* base and limit */
    d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
    d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
    pci_set_word(d->wmask + PCI_MEMORY_BASE,
                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
                 PCI_PREF_RANGE_MASK & 0xffff);
    pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
                 PCI_PREF_RANGE_MASK & 0xffff);

    /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
    memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);

    pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
}

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static void pci_config_alloc(PCIDevice *pci_dev)
{
    int config_size = pci_config_size(pci_dev);

    pci_dev->config = qemu_mallocz(config_size);
    pci_dev->cmask = qemu_mallocz(config_size);
    pci_dev->wmask = qemu_mallocz(config_size);
    pci_dev->used = qemu_mallocz(config_size);
}

static void pci_config_free(PCIDevice *pci_dev)
{
    qemu_free(pci_dev->config);
    qemu_free(pci_dev->cmask);
    qemu_free(pci_dev->wmask);
    qemu_free(pci_dev->used);
}

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/* -1 for devfn means auto assign */
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static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
                                         const char *name, int devfn,
                                         PCIConfigReadFunc *config_read,
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                                         PCIConfigWriteFunc *config_write,
                                         uint8_t header_type)
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{
    if (devfn < 0) {
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        for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
            devfn += 8) {
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            if (!bus->devices[devfn])
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                goto found;
        }
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        hw_error("PCI: no devfn available for %s, all in use\n", name);
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    found: ;
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    } else if (bus->devices[devfn]) {
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        hw_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
                 name, bus->devices[devfn]->name);
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    }
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    pci_dev->bus = bus;
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    pci_dev->devfn = devfn;
    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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    memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
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    pci_config_alloc(pci_dev);
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    header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
    if (header_type == PCI_HEADER_TYPE_NORMAL) {
        pci_set_default_subsystem_id(pci_dev);
    }
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    pci_init_cmask(pci_dev);
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    pci_init_wmask(pci_dev);
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    if (header_type == PCI_HEADER_TYPE_BRIDGE) {
        pci_init_wmask_bridge(pci_dev);
    }
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    if (!config_read)
        config_read = pci_default_read_config;
    if (!config_write)
        config_write = pci_default_write_config;
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    pci_dev->config_read = config_read;
    pci_dev->config_write = config_write;
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    bus->devices[devfn] = pci_dev;
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    pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
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    pci_dev->version_id = 2; /* Current pci device vmstate version */
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    return pci_dev;
}

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PCIDevice *pci_register_device(PCIBus *bus, const char *name,
                               int instance_size, int devfn,
                               PCIConfigReadFunc *config_read,
                               PCIConfigWriteFunc *config_write)
{
    PCIDevice *pci_dev;

    pci_dev = qemu_mallocz(instance_size);
    pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
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                                     config_read, config_write,
                                     PCI_HEADER_TYPE_NORMAL);
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    return pci_dev;
}
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static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
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{
    return addr + pci_mem_base;
}

static void pci_unregister_io_regions(PCIDevice *pci_dev)
{
    PCIIORegion *r;
    int i;

    for(i = 0; i < PCI_NUM_REGIONS; i++) {
        r = &pci_dev->io_regions[i];
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        if (!r->size || r->addr == PCI_BAR_UNMAPPED)
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            continue;
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        if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
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            isa_unassign_ioport(r->addr, r->filtered_size);
558 559
        } else {
            cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
560
                                                     r->filtered_size,
561 562 563 564 565
                                                     IO_MEM_UNASSIGNED);
        }
    }
}

566
static int pci_unregister_device(DeviceState *dev)
567
{
568
    PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
569
    PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
570 571
    int ret = 0;

572 573
    if (info->exit)
        ret = info->exit(pci_dev);
574 575 576 577 578 579 580
    if (ret)
        return ret;

    pci_unregister_io_regions(pci_dev);

    qemu_free_irqs(pci_dev->irq);
    pci_dev->bus->devices[pci_dev->devfn] = NULL;
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    pci_config_free(pci_dev);
582 583 584
    return 0;
}

585
void pci_register_bar(PCIDevice *pci_dev, int region_num,
586
                            pcibus_t size, int type,
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587 588 589
                            PCIMapIORegionFunc *map_func)
{
    PCIIORegion *r;
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590
    uint32_t addr;
591
    pcibus_t wmask;
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592

593
    if ((unsigned int)region_num >= PCI_NUM_REGIONS)
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594
        return;
595 596 597

    if (size & (size-1)) {
        fprintf(stderr, "ERROR: PCI region size must be pow2 "
598
                    "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
599 600 601
        exit(1);
    }

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602
    r = &pci_dev->io_regions[region_num];
603
    r->addr = PCI_BAR_UNMAPPED;
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604
    r->size = size;
605
    r->filtered_size = size;
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    r->type = type;
    r->map_func = map_func;
608 609

    wmask = ~(size - 1);
610
    addr = pci_bar(pci_dev, region_num);
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611
    if (region_num == PCI_ROM_SLOT) {
612
        /* ROM enable bit is writeable */
613
        wmask |= PCI_ROM_ADDRESS_ENABLE;
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614
    }
615
    pci_set_long(pci_dev->config + addr, type);
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    if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
        r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
        pci_set_quad(pci_dev->wmask + addr, wmask);
        pci_set_quad(pci_dev->cmask + addr, ~0ULL);
    } else {
        pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
        pci_set_long(pci_dev->cmask + addr, 0xffffffff);
    }
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}

626 627 628 629 630 631 632
static uint32_t pci_config_get_io_base(PCIDevice *d,
                                       uint32_t base, uint32_t base_upper16)
{
    uint32_t val;

    val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
    if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
633
        val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724
    }
    return val;
}

static uint64_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
{
    return ((uint64_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
        << 16;
}

static uint64_t pci_config_get_pref_base(PCIDevice *d,
                                         uint32_t base, uint32_t upper)
{
    uint64_t val;
    val = ((uint64_t)pci_get_word(d->config + base) &
           PCI_PREF_RANGE_MASK) << 16;
    val |= (uint64_t)pci_get_long(d->config + upper) << 32;
    return val;
}

static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
{
    pcibus_t base;
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
        base = pci_config_get_io_base(bridge,
                                      PCI_IO_BASE, PCI_IO_BASE_UPPER16);
    } else {
        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
            base = pci_config_get_pref_base(
                bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
        } else {
            base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
        }
    }

    return base;
}

static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
{
    pcibus_t limit;
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
        limit = pci_config_get_io_base(bridge,
                                      PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
        limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
    } else {
        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
            limit = pci_config_get_pref_base(
                bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
        } else {
            limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
        }
        limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
    }
    return limit;
}

static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
                              uint8_t type)
{
    pcibus_t base = *addr;
    pcibus_t limit = *addr + *size - 1;
    PCIDevice *br;

    for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
        uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);

        if (type & PCI_BASE_ADDRESS_SPACE_IO) {
            if (!(cmd & PCI_COMMAND_IO)) {
                goto no_map;
            }
        } else {
            if (!(cmd & PCI_COMMAND_MEMORY)) {
                goto no_map;
            }
        }

        base = MAX(base, pci_bridge_get_base(br, type));
        limit = MIN(limit, pci_bridge_get_limit(br, type));
    }

    if (base > limit) {
    no_map:
        *addr = PCI_BAR_UNMAPPED;
        *size = 0;
    } else {
        *addr = base;
        *size = limit - base + 1;
    }
}

725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789
static pcibus_t pci_bar_address(PCIDevice *d,
				int reg, uint8_t type, pcibus_t size)
{
    pcibus_t new_addr, last_addr;
    int bar = pci_bar(d, reg);
    uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);

    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
        if (!(cmd & PCI_COMMAND_IO)) {
            return PCI_BAR_UNMAPPED;
        }
        new_addr = pci_get_long(d->config + bar) & ~(size - 1);
        last_addr = new_addr + size - 1;
        /* NOTE: we have only 64K ioports on PC */
        if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
            return PCI_BAR_UNMAPPED;
        }
        return new_addr;
    }

    if (!(cmd & PCI_COMMAND_MEMORY)) {
        return PCI_BAR_UNMAPPED;
    }
    if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
        new_addr = pci_get_quad(d->config + bar);
    } else {
        new_addr = pci_get_long(d->config + bar);
    }
    /* the ROM slot has a specific enable bit */
    if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
        return PCI_BAR_UNMAPPED;
    }
    new_addr &= ~(size - 1);
    last_addr = new_addr + size - 1;
    /* NOTE: we do not support wrapping */
    /* XXX: as we cannot support really dynamic
       mappings, we handle specific values as invalid
       mappings. */
    if (last_addr <= new_addr || new_addr == 0 ||
        last_addr == PCI_BAR_UNMAPPED) {
        return PCI_BAR_UNMAPPED;
    }

    /* Now pcibus_t is 64bit.
     * Check if 32 bit BAR wraps around explicitly.
     * Without this, PC ide doesn't work well.
     * TODO: remove this work around.
     */
    if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
        return PCI_BAR_UNMAPPED;
    }

    /*
     * OS is allowed to set BAR beyond its addressable
     * bits. For example, 32 bit OS can set 64bit bar
     * to >4G. Check it. TODO: we might need to support
     * it in the future for e.g. PAE.
     */
    if (last_addr >= TARGET_PHYS_ADDR_MAX) {
        return PCI_BAR_UNMAPPED;
    }

    return new_addr;
}

790 791 792
static void pci_update_mappings(PCIDevice *d)
{
    PCIIORegion *r;
793 794
    int i;
    pcibus_t new_addr, filtered_size;
795

796
    for(i = 0; i < PCI_NUM_REGIONS; i++) {
797
        r = &d->io_regions[i];
798 799

        /* this region isn't registered */
800
        if (!r->size)
801 802
            continue;

803
        new_addr = pci_bar_address(d, i, r->type, r->size);
804

805 806 807 808 809 810
        /* bridge filtering */
        filtered_size = r->size;
        if (new_addr != PCI_BAR_UNMAPPED) {
            pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
        }

811
        /* This bar isn't changed */
812
        if (new_addr == r->addr && filtered_size == r->filtered_size)
813 814 815 816 817 818 819 820 821 822 823 824
            continue;

        /* now do the real mapping */
        if (r->addr != PCI_BAR_UNMAPPED) {
            if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
                int class;
                /* NOTE: specific hack for IDE in PC case:
                   only one byte must be mapped. */
                class = pci_get_word(d->config + PCI_CLASS_DEVICE);
                if (class == 0x0101 && r->size == 4) {
                    isa_unassign_ioport(r->addr + 2, 1);
                } else {
825
                    isa_unassign_ioport(r->addr, r->filtered_size);
826
                }
827 828
            } else {
                cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
829
                                             r->filtered_size,
830
                                             IO_MEM_UNASSIGNED);
831
                qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
832 833
            }
        }
834
        r->addr = new_addr;
835
        r->filtered_size = filtered_size;
836
        if (r->addr != PCI_BAR_UNMAPPED) {
837 838 839 840 841 842 843 844
            /*
             * TODO: currently almost all the map funcions assumes
             * filtered_size == size and addr & ~(size - 1) == addr.
             * However with bridge filtering, they aren't always true.
             * Teach them such cases, such that filtered_size < size and
             * addr & (size - 1) != 0.
             */
            r->map_func(d, i, r->addr, r->filtered_size, r->type);
845
        }
846 847 848
    }
}

849
uint32_t pci_default_read_config(PCIDevice *d,
850
                                 uint32_t address, int len)
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{
852 853
    uint32_t val = 0;
    assert(len == 1 || len == 2 || len == 4);
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    len = MIN(len, pci_config_size(d) - address);
855 856
    memcpy(&val, d->config + address, len);
    return le32_to_cpu(val);
857 858
}

859
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
860
{
861
    int i;
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862
    uint32_t config_size = pci_config_size(d);
863

864 865 866
    for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
        uint8_t wmask = d->wmask[addr + i];
        d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
867
    }
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    if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
869 870
        ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
        ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
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        range_covers_byte(addr, l, PCI_COMMAND))
872
        pci_update_mappings(d);
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873 874
}

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875 876
/***********************************************************/
/* generic PCI irq support */
877

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878
/* 0 <= irq_num <= 3. level must be 0 or 1 */
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879
static void pci_set_irq(void *opaque, int irq_num, int level)
B
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880
{
881
    PCIDevice *pci_dev = opaque;
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882 883
    PCIBus *bus;
    int change;
884

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885 886 887
    change = level - pci_dev->irq_state[irq_num];
    if (!change)
        return;
888 889

    pci_dev->irq_state[irq_num] = level;
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890 891
    for (;;) {
        bus = pci_dev->bus;
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892
        irq_num = bus->map_irq(pci_dev, irq_num);
P
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893 894
        if (bus->set_irq)
            break;
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895 896 897
        pci_dev = bus->parent_dev;
    }
    bus->irq_count[irq_num] += change;
898
    bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
B
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899 900
}

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901 902
/***********************************************************/
/* monitor info on PCI */
903

904 905 906 907 908
typedef struct {
    uint16_t class;
    const char *desc;
} pci_class_desc;

909
static const pci_class_desc pci_class_descriptions[] =
910
{
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911
    { 0x0100, "SCSI controller"},
912
    { 0x0101, "IDE controller"},
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913 914 915 916 917 918
    { 0x0102, "Floppy controller"},
    { 0x0103, "IPI controller"},
    { 0x0104, "RAID controller"},
    { 0x0106, "SATA controller"},
    { 0x0107, "SAS controller"},
    { 0x0180, "Storage controller"},
919
    { 0x0200, "Ethernet controller"},
T
ths 已提交
920 921 922 923
    { 0x0201, "Token Ring controller"},
    { 0x0202, "FDDI controller"},
    { 0x0203, "ATM controller"},
    { 0x0280, "Network controller"},
924
    { 0x0300, "VGA controller"},
T
ths 已提交
925 926 927 928 929 930 931 932 933 934
    { 0x0301, "XGA controller"},
    { 0x0302, "3D controller"},
    { 0x0380, "Display controller"},
    { 0x0400, "Video controller"},
    { 0x0401, "Audio controller"},
    { 0x0402, "Phone"},
    { 0x0480, "Multimedia controller"},
    { 0x0500, "RAM controller"},
    { 0x0501, "Flash controller"},
    { 0x0580, "Memory controller"},
935 936
    { 0x0600, "Host bridge"},
    { 0x0601, "ISA bridge"},
T
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937 938
    { 0x0602, "EISA bridge"},
    { 0x0603, "MC bridge"},
939
    { 0x0604, "PCI bridge"},
T
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940 941 942 943 944
    { 0x0605, "PCMCIA bridge"},
    { 0x0606, "NUBUS bridge"},
    { 0x0607, "CARDBUS bridge"},
    { 0x0608, "RACEWAY bridge"},
    { 0x0680, "Bridge"},
945 946 947 948
    { 0x0c03, "USB controller"},
    { 0, NULL}
};

949
static void pci_info_device(PCIBus *bus, PCIDevice *d)
950
{
A
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951
    Monitor *mon = cur_mon;
P
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952 953
    int i, class;
    PCIIORegion *r;
954
    const pci_class_desc *desc;
955

A
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956
    monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
957 958
                   pci_bus_num(d->bus),
                   PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
959
    class = pci_get_word(d->config + PCI_CLASS_DEVICE);
A
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960
    monitor_printf(mon, "    ");
961 962 963 964
    desc = pci_class_descriptions;
    while (desc->desc && class != desc->class)
        desc++;
    if (desc->desc) {
A
aliguori 已提交
965
        monitor_printf(mon, "%s", desc->desc);
966
    } else {
A
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967
        monitor_printf(mon, "Class %04x", class);
968
    }
A
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969
    monitor_printf(mon, ": PCI device %04x:%04x\n",
970 971
           pci_get_word(d->config + PCI_VENDOR_ID),
           pci_get_word(d->config + PCI_DEVICE_ID));
972

P
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973
    if (d->config[PCI_INTERRUPT_PIN] != 0) {
A
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974 975
        monitor_printf(mon, "      IRQ %d.\n",
                       d->config[PCI_INTERRUPT_LINE]);
976
    }
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977
    if (class == 0x0604) {
978 979 980
        uint64_t base;
        uint64_t limit;

A
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981
        monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
982 983 984 985 986 987 988 989 990 991 992
        monitor_printf(mon, "      secondary bus %d.\n",
                       d->config[PCI_SECONDARY_BUS]);
        monitor_printf(mon, "      subordinate bus %d.\n",
                       d->config[PCI_SUBORDINATE_BUS]);

        base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO);
        limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO);
        monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
                       base, limit);

        base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
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993
        limit= pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
994 995 996 997 998 999 1000 1001 1002 1003
        monitor_printf(mon,
                       "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
                       base, limit);

        base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
                                   PCI_BASE_ADDRESS_MEM_PREFETCH);
        limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
                                     PCI_BASE_ADDRESS_MEM_PREFETCH);
        monitor_printf(mon, "      prefetchable memory range "
                       "[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit);
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1004
    }
P
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1005 1006 1007
    for(i = 0;i < PCI_NUM_REGIONS; i++) {
        r = &d->io_regions[i];
        if (r->size != 0) {
A
aliguori 已提交
1008
            monitor_printf(mon, "      BAR%d: ", i);
1009
            if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1010 1011
                monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
                               " [0x%04"FMT_PCIBUS"].\n",
A
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1012
                               r->addr, r->addr + r->size - 1);
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1013
            } else {
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1014 1015 1016 1017 1018 1019 1020
                const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ?
                    "64 bit" : "32 bit";
                const char *prefetch =
                    r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ?
                    " prefetchable" : "";

                monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
1021
                               " [0x%08"FMT_PCIBUS"].\n",
I
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1022
                               type, prefetch,
A
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1023
                               r->addr, r->addr + r->size - 1);
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1024 1025
            }
        }
B
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1026
    }
1027
    monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
P
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1028
    if (class == 0x0604 && d->config[0x19] != 0) {
1029
        pci_for_each_device(bus, d->config[0x19], pci_info_device);
P
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1030
    }
1031 1032
}

1033 1034
static void pci_for_each_device_under_bus(PCIBus *bus,
                                          void (*fn)(PCIBus *b, PCIDevice *d))
1035 1036
{
    PCIDevice *d;
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1037
    int devfn;
1038

1039
    for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1040 1041 1042 1043 1044 1045 1046 1047 1048
        d = bus->devices[devfn];
        if (d)
            fn(bus, d);
    }
}

void pci_for_each_device(PCIBus *bus, int bus_num,
                         void (*fn)(PCIBus *b, PCIDevice *d))
{
1049
    bus = pci_find_bus(bus, bus_num);
1050

P
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1051
    if (bus) {
1052
        pci_for_each_device_under_bus(bus, fn);
B
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1053 1054 1055
    }
}

A
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1056
void pci_info(Monitor *mon)
B
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1057
{
1058 1059 1060 1061
    struct PCIHostBus *host;
    QLIST_FOREACH(host, &host_buses, next) {
        pci_for_each_device(host->bus, 0, pci_info_device);
    }
B
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1062
}
1063

1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
static const char * const pci_nic_models[] = {
    "ne2k_pci",
    "i82551",
    "i82557b",
    "i82559er",
    "rtl8139",
    "e1000",
    "pcnet",
    "virtio",
    NULL
};

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static const char * const pci_nic_names[] = {
    "ne2k_pci",
    "i82551",
    "i82557b",
    "i82559er",
    "rtl8139",
    "e1000",
    "pcnet",
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    "virtio-net-pci",
1085 1086 1087
    NULL
};

1088
/* Initialize a PCI NIC.  */
1089
/* FIXME callers should check for failure, but don't */
1090 1091
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
                        const char *default_devaddr)
1092
{
1093
    const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1094 1095
    PCIBus *bus;
    int devfn;
1096
    PCIDevice *pci_dev;
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    DeviceState *dev;
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    int i;

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    i = qemu_find_nic_model(nd, pci_nic_models, default_model);
    if (i < 0)
        return NULL;

    bus = pci_get_bus_devfn(&devfn, devaddr);
    if (!bus) {
        qemu_error("Invalid PCI device address %s for device %s\n",
                   devaddr, pci_nic_names[i]);
        return NULL;
    }

1111
    pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1112
    dev = &pci_dev->qdev;
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    if (nd->name)
        dev->id = qemu_strdup(nd->name);
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    qdev_set_nic_properties(dev, nd);
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    if (qdev_init(dev) < 0)
        return NULL;
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    return pci_dev;
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}

1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
                               const char *default_devaddr)
{
    PCIDevice *res;

    if (qemu_show_nic_models(nd->model, pci_nic_models))
        exit(0);

    res = pci_nic_init(nd, default_model, default_devaddr);
    if (!res)
        exit(1);
    return res;
}

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typedef struct {
    PCIDevice dev;
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    PCIBus bus;
    uint32_t vid;
    uint32_t did;
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} PCIBridge;

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static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
{
    pci_update_mappings(d);
}

static void pci_bridge_update_mappings(PCIBus *b)
{
    PCIBus *child;

    pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);

    QLIST_FOREACH(child, &b->child, sibling) {
        pci_bridge_update_mappings(child);
    }
}

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static void pci_bridge_write_config(PCIDevice *d,
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                             uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(d, address, val, len);
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    if (/* io base/limit */
        ranges_overlap(address, len, PCI_IO_BASE, 2) ||

        /* memory base/limit, prefetchable base/limit and
           io base/limit upper 16 */
        ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
        pci_bridge_update_mappings(d->bus);
    }
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}

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PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1175
{
1176
    PCIBus *sec;
1177

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    if (!bus)
        return NULL;
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    if (pci_bus_num(bus) == bus_num) {
        return bus;
    }

    /* try child bus */
    QLIST_FOREACH(sec, &bus->child, sibling) {
1187 1188 1189 1190

        if (!bus->parent_dev /* pci host bridge */
            || (pci_bus_num(sec) <= bus_num &&
                bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
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            return pci_find_bus(sec, bus_num);
        }
    }

    return NULL;
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}

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PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1199
{
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    bus = pci_find_bus(bus, bus_num);
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    if (!bus)
        return NULL;

    return bus->devices[PCI_DEVFN(slot, function)];
}

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static int pci_bridge_initfn(PCIDevice *dev)
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{
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    PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
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    pci_config_set_vendor_id(s->dev.config, s->vid);
    pci_config_set_device_id(s->dev.config, s->did);
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    /* TODO: intial value
     * command register:
     * According to PCI bridge spec, after reset
     *   bus master bit is off
     *   memory space enable bit is off
     * According to manual (805-1251.pdf).(See abp_pbi.c for its links.)
     *   the reset value should be zero unless the boot pin is tied high
     *   (which is tru) and thus it should be PCI_COMMAND_MEMORY.
     *
     * For now, don't touch the value.
     * Later command register will be set to zero and apb_pci.c will
     * override the value.
     * Same for latency timer, and multi function bit of header type.
     */
    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);

    pci_set_word(dev->config + PCI_STATUS,
                 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
    pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
    dev->config[PCI_LATENCY_TIMER] = 0x10;
    dev->config[PCI_HEADER_TYPE] =
        PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE;
    pci_set_word(dev->config + PCI_SEC_STATUS,
                 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
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    return 0;
}
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static int pci_bridge_exitfn(PCIDevice *pci_dev)
{
    PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
    PCIBus *bus = &s->bus;
    pci_unregister_secondary_bus(bus);
    return 0;
}

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PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
                        pci_map_irq_fn map_irq, const char *name)
{
    PCIDevice *dev;
    PCIBridge *s;

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    dev = pci_create(bus, devfn, "pci-bridge");
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    qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
    qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
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    qdev_init_nofail(&dev->qdev);
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    s = DO_UPCAST(PCIBridge, dev, dev);
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    pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
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    return &s->bus;
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}
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static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
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{
    PCIDevice *pci_dev = (PCIDevice *)qdev;
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    PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
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    PCIBus *bus;
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    int devfn, rc;
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    /* initialize cap_present for pci_is_express() and pci_config_size() */
    if (info->is_express) {
        pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
    }

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    bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
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    devfn = pci_dev->devfn;
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    pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1282 1283
                                     info->config_read, info->config_write,
                                     info->header_type);
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    rc = info->init(pci_dev);
    if (rc != 0)
        return rc;
    if (qdev->hotplugged)
        bus->hotplug(pci_dev, 1);
    return 0;
}

static int pci_unplug_device(DeviceState *qdev)
{
    PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);

    dev->bus->hotplug(dev, 0);
    return 0;
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}

1300
void pci_qdev_register(PCIDeviceInfo *info)
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{
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    info->qdev.init = pci_qdev_init;
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    info->qdev.unplug = pci_unplug_device;
1304
    info->qdev.exit = pci_unregister_device;
1305
    info->qdev.bus_info = &pci_bus_info;
1306
    qdev_register(&info->qdev);
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}

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void pci_qdev_register_many(PCIDeviceInfo *info)
{
    while (info->qdev.name) {
        pci_qdev_register(info);
        info++;
    }
}

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PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
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{
    DeviceState *dev;

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    dev = qdev_create(&bus->qbus, name);
1322
    qdev_prop_set_uint32(dev, "addr", devfn);
1323 1324
    return DO_UPCAST(PCIDevice, qdev, dev);
}
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PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
{
1328
    PCIDevice *dev = pci_create(bus, devfn, name);
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    qdev_init_nofail(&dev->qdev);
1330
    return dev;
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}
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static int pci_find_space(PCIDevice *pdev, uint8_t size)
{
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    int config_size = pci_config_size(pdev);
1336 1337
    int offset = PCI_CONFIG_HEADER_SIZE;
    int i;
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    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377
        if (pdev->used[i])
            offset = i + 1;
        else if (i - offset + 1 == size)
            return offset;
    return 0;
}

static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
                                        uint8_t *prev_p)
{
    uint8_t next, prev;

    if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
        return 0;

    for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
         prev = next + PCI_CAP_LIST_NEXT)
        if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
            break;

    if (prev_p)
        *prev_p = prev;
    return next;
}

/* Reserve space and add capability to the linked list in pci config space */
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
{
    uint8_t offset = pci_find_space(pdev, size);
    uint8_t *config = pdev->config + offset;
    if (!offset)
        return -ENOSPC;
    config[PCI_CAP_LIST_ID] = cap_id;
    config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
    pdev->config[PCI_CAPABILITY_LIST] = offset;
    pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
    memset(pdev->used + offset, 0xFF, size);
    /* Make capability read-only by default */
    memset(pdev->wmask + offset, 0, size);
1378 1379
    /* Check capability by default */
    memset(pdev->cmask + offset, 0xFF, size);
1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391
    return offset;
}

/* Unlink capability from the pci config space. */
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
{
    uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
    if (!offset)
        return;
    pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
    /* Make capability writeable again */
    memset(pdev->wmask + offset, 0xff, size);
1392 1393
    /* Clear cmask as device-specific registers can't be checked */
    memset(pdev->cmask + offset, 0, size);
1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409
    memset(pdev->used + offset, 0, size);

    if (!pdev->config[PCI_CAPABILITY_LIST])
        pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
}

/* Reserve space for capability at a known offset (to call after load). */
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
{
    memset(pdev->used + offset, 0xff, size);
}

uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
{
    return pci_find_capability_list(pdev, cap_id, NULL);
}
1410 1411 1412 1413 1414 1415 1416 1417 1418

static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
    PCIDevice *d = (PCIDevice *)dev;
    const pci_class_desc *desc;
    char ctxt[64];
    PCIIORegion *r;
    int i, class;

1419
    class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431
    desc = pci_class_descriptions;
    while (desc->desc && class != desc->class)
        desc++;
    if (desc->desc) {
        snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
    } else {
        snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
    }

    monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
                   "pci id %04x:%04x (sub %04x:%04x)\n",
                   indent, "", ctxt,
1432 1433
                   d->config[PCI_SECONDARY_BUS],
                   PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1434 1435 1436 1437
                   pci_get_word(d->config + PCI_VENDOR_ID),
                   pci_get_word(d->config + PCI_DEVICE_ID),
                   pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
                   pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1438 1439 1440 1441
    for (i = 0; i < PCI_NUM_REGIONS; i++) {
        r = &d->io_regions[i];
        if (!r->size)
            continue;
1442 1443 1444
        monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
                       " [0x%"FMT_PCIBUS"]\n",
                       indent, "",
1445
                       i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1446 1447 1448
                       r->addr, r->addr + r->size - 1);
    }
}
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static PCIDeviceInfo bridge_info = {
    .qdev.name    = "pci-bridge",
    .qdev.size    = sizeof(PCIBridge),
    .init         = pci_bridge_initfn,
1454
    .exit         = pci_bridge_exitfn,
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    .config_write = pci_bridge_write_config,
    .qdev.props   = (Property[]) {
        DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
        DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void pci_register_devices(void)
{
    pci_qdev_register(&bridge_info);
}

device_init(pci_register_devices)