- 29 5月, 2013 4 次提交
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由 Hiroshi Doyu 提交于
Use the Tegra20 CAR binding header (tegra20-car.h) to replace magic numbers in the device tree. For example, - clocks = <&tegra_car 28>; + clocks = <&tegra_car CLK_HOST1X>; Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> [swarren, updated since tegra20-car.h moved for consistency] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Use the GIC and standard IRQ binding defines in all IRQ specifiers. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties, and some interrupts properties. Use standard GPIO flag defines too. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as the IDs and flags in GPIO specifiers. Use of those features will increase the readability of the device tree files. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 18 5月, 2013 2 次提交
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由 Venu Byravarasu 提交于
This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Venu Byravarasu 提交于
1. All Tegra20 ULPI reset GPIO DT properties are modified to indicate active low nature of the GPIO. 2. Placed USB PHY DT node immediately below the EHCI controller DT nodes and corrected reg value in the name of USB PHY DT node. Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 05 4月, 2013 4 次提交
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由 Prashant Gaikwad 提交于
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
Adding the PM configuration of PMC when the platform support suspend function. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
This patch adds "non-removable" property of MMC host where the eMMC device is for Tegra platform. And the "keep-power-in-suspend" property was used for the SDIO device that need this to go into suspend mode (e.g. BRCM43xx series). Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Audio-related clocks need to be represented in the device tree. Update bindings to describe which clocks are needed, and DT files to include those clocks. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 04 4月, 2013 1 次提交
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由 Joseph Lo 提交于
Adding the bindings of the clock source of PMC in DT. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 12 3月, 2013 1 次提交
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由 Joseph Lo 提交于
The GPIO pin of SD slot card detection should active low. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Tested-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 29 1月, 2013 4 次提交
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由 Venu Byravarasu 提交于
As reset GPIO information is PHY specific detail, adding it to PHY DT node. Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Lucas Stach 提交于
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: NLucas Stach <dev@lynxeye.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Enable Tegra based keyboard controller and populate the key matrix for seaboard. The key matrix was originally on driver code which is removed to have clean driver. The key mapping is now passed through dts file. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 21 11月, 2012 1 次提交
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由 Stephen Warren 提交于
A couple devices' DT compatible values only contained the device name without any vendor prefix. Add the missing vendor prefixes. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NRob Herring <rob.herring@calxeda.com>
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- 16 11月, 2012 1 次提交
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由 Wei Ni 提交于
Enable the SDHCI1 controller. This is connected to the WiFi module. Signed-off-by: NWei Ni <wni@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 06 11月, 2012 1 次提交
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由 Stephen Warren 提交于
Commit 13511def "regulator: deprecate regulator-compatible DT property" now allows for simpler content within the regulators node within a PMIC. Modify all the Tegra device tree files to take advantage of this. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NThierry Reding <thierry.reding@avionic-design.de>
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- 07 10月, 2012 1 次提交
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由 Stephen Warren 提交于
Unit addresses, whilst written in hex, don't contain a 0x prefix. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 12 9月, 2012 1 次提交
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由 Stephen Warren 提交于
For Seaboard, Ventana, and Cardhu, add DT property to tell the regulator that it should provide the pm_power_off() implementation. This allows "shutdown" to work. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 07 9月, 2012 1 次提交
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由 Stephen Warren 提交于
Seaboard uses a TPS6586x regulator. Instantiate this, and hook up a couple of fixed GPIO-controlled regulators too. Two data sources were used for the data encoded here: * The HW defaults, as extracted from real HW. * The schematic, which specifies a voltage for each LDO rail. In most cases these sources matched. The only differences is: ldo6: The HW default on Springbank is 2.85v. The HW default on Seaboard is 1.8v. The schematics for both Springbank and Seaboard match at 2.85v. However, internal research indicates that the schematics are incorrectly labelled, and 1.8v is correct. The ChromeOS kernel also uses 1.8v. Note that these settings don't entirely match those in the ChromeOS kernel found at the URL below. However, the selected values generally cause no behavior change in the kernel, and so were picked to avoid regressions. repo http://git.chromium.org/chromiumos/third_party/kernel.git branch chromeos-3.2 file arch/arm/mach-tegra/board-seaboard-power.c Portions based on work by Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 07 7月, 2012 2 次提交
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由 Stephen Warren 提交于
Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Tegra's I2C2 controller can be routed to either the PTA or DDC pin group on Seaboard. Define the pinctrl state nodes required to allow runtime control of this routing. Instantiate a pinctrl-i2cmux I2C bus mux that uses these pinctrl states. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 21 6月, 2012 1 次提交
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由 Stephen Warren 提交于
Most ARM ${board}.dts files are already named ${soc}-${board}.dts. This change modifies the Tegra board files to be named the same way for consistency. Once a related change is made in U-Boot, this will cause both U-Boot and the kernel to use the same names for the .dts files and SoC identifiers, thus allowing U-Boot's recently added "soc" and "board" environment variables to be used to construct the name of Tegra .dtb files, and hence allow board-generic U-Boot bootcmd scripts to be written. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 12 6月, 2012 2 次提交
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由 Stephen Warren 提交于
The driver supports the new bus-width property, so remove the legacy support-8bit property. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 hdoyu@nvidia.com 提交于
Use a more plain english name. Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com> [swarren: also rename the node in tegra-seaboard.dts] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 15 5月, 2012 6 次提交
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由 Arnd Bergmann 提交于
This patch unifies the current DT MMC bindings documentation and code, adds generic MMC DT bindings documentation, and updates .dts files for consistency. [cjb: typo fixes, addition of max-frequency property] Signed-off-by: NChris Ball <cjb@laptop.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Stephen Warren 提交于
In tegra*.dtsi, set status="disable" for all HW modules that the board design may choose not to use. Update all boards to specifically enable any of those modules that are useful by setting status="okay". This makes board files say which features they do use, rather than which they don't, which feels more logical. It also makes the .dts files slightly smaller, at least for existing content. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
It's already specified in skeleton.dtsi, included via tegra20.dtsi. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
DT node names only need to include the unit address if it's required to make the node name unique. Remove the unnecessary unit addresses. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Consistently don't place a space after < or before >. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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- 04 5月, 2012 4 次提交
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由 Olof Johansson 提交于
Add the known i2c devices on seaboard to the i2c table. Also rename the temperature sensor device node, and mark it as a nct1008 instead of an adt7461 (which it is -- the chips are compatible though). Signed-off-by: NOlof Johansson <olof@lixom.net> [swarren: Removed isl29018 from patch; it's already there now. Fixed interrupts properties now that Tegra GPIO is an interrupt controller. Moved smart-battery to the correct I2C bus.] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
The I2C2 controller can be routed to either pingroup DDC or PTA. Seaboard actually uses this as an I2C bus mux, and devices are connected to both pingroups. This change statically assigns the I2C2 controller to pingroup PTA, so that on-board devices can be accessed. The DDC pingroup is used for EDID/DDC accesses which are not yet required, given the absence of any Tegra graphics support. I2C muxing will be supported later. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
This I2C bus is used for EDID/DDC reads and other "slow" I2C devices. This requires a 100KHz SCL (clock) rate. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Add the device info for ALS and proximity sensor for tegra boards cardhu, ventana and seaboard. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: s/PZ02/PZ2/ in .dts files, s/seabridge/seaboard/ in commit description] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 26 4月, 2012 1 次提交
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由 Stephen Warren 提交于
ULPI PHYs have a reset signal, and different boards use a different GPIO for this task. Add a property to device tree to represent this. I'm not sure if adding this property to the EHCI controller node is entirely correct; perhaps eventually we should have explicit separate nodes for the various PHYs. However, we don't have that right now, so this binding seems like a reasonable choice. Cc: <devicetree-discuss@lists.ozlabs.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: <linux-usb@vger.kernel.org> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 19 4月, 2012 1 次提交
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由 Stephen Warren 提交于
This adds a complete pinmux configuration to all Tegra20 device tree files. This allows removal of board-dt-tegra20.c's use of the pinmux board files, and the special device tree handling in board-pinmux.c. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NOlof Johansson <olof@lixom.net>
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- 08 3月, 2012 1 次提交
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由 Simon Glass 提交于
The USB1 port on Tegra2 supports operation in host or device modes. On Seaboard this is possible, so mark the port as OTG. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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