ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: NLucas Stach <dev@lynxeye.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
Showing
想要评论请 注册 或 登录