- 14 6月, 2022 1 次提交
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由 Corentin Labbe 提交于
stable inclusion from stable-v5.10.107 commit d687d7559e2460ad306484f64b85a943d7127508 bugzilla: https://gitee.com/openeuler/kernel/issues/I574A2 Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=d687d7559e2460ad306484f64b85a943d7127508 -------------------------------- [ Upstream commit 3916c361 ] crypto-controller had a typo, fix it. In the same time, rename it to just crypto Signed-off-by: NCorentin Labbe <clabbe@baylibre.com> Acked-by: NKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220209120355.1985707-1-clabbe@baylibre.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NYu Liao <liaoyu15@huawei.com> Reviewed-by: NWei Li <liwei391@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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- 15 10月, 2021 3 次提交
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由 Elaine Zhang 提交于
stable inclusion from stable-5.10.53 commit 95b64be2e7414e42a59a4fa9239c92e96210b399 bugzilla: 175574 https://gitee.com/openeuler/kernel/issues/I4DTUX Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=95b64be2e7414e42a59a4fa9239c92e96210b399 -------------------------------- [ Upstream commit 970cdc53 ] Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com> Reviewed-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210417112952.8516-4-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NChen Jun <chenjun102@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Ezequiel Garcia 提交于
stable inclusion from stable-5.10.53 commit 55014c38e73d00e88d152e9deb0fc8c01e755c9a bugzilla: 175574 https://gitee.com/openeuler/kernel/issues/I4DTUX Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=55014c38e73d00e88d152e9deb0fc8c01e755c9a -------------------------------- [ Upstream commit 7b46d674 ] Fixed order is the device-tree convention. The timer driver currently gets clocks by name, so no changes are needed there. Signed-off-by: NEzequiel Garcia <ezequiel@collabora.com> Link: https://lore.kernel.org/r/20210506111136.3941-3-ezequiel@collabora.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NChen Jun <chenjun102@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Johan Jonker 提交于
stable inclusion from stable-5.10.53 commit 7d3408c723364320c1552e034a8e808ec50e7e08 bugzilla: 175574 https://gitee.com/openeuler/kernel/issues/I4DTUX Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=7d3408c723364320c1552e034a8e808ec50e7e08 -------------------------------- [ Upstream commit dfbfb86a ] A test with the command below aimed at powerpc generates notifications in the Rockchip ARM tree. Fix pinctrl "sleep" nodename by renaming it to "suspend" for rk3036-kylin and rk3288 make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/powerpc/sleep.yaml Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210126110221.10815-1-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NChen Jun <chenjun102@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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- 23 7月, 2020 1 次提交
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由 Jagan Teki 提交于
rk3288 and rk3288w have a usb host0 ohci controller. Although rk3288 ohci doesn't actually work on hardware, but rk3288w ohci can work well. So add usb host0 ohci node in rk3288 dtsi and boards can then enable it if supported. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Cc: William Wu <william.wu@rock-chips.com> Link: https://lore.kernel.org/r/20200720105846.367776-1-jagan@amarulasolutions.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 18 7月, 2020 1 次提交
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由 Sugar Zhang 提交于
This patch Add the quirk to specify to use burst transfer for better compatible and higher performance. Signed-off-by: NSugar Zhang <sugar.zhang@rock-chips.com> Link: https://lore.kernel.org/r/1593439866-68459-1-git-send-email-sugar.zhang@rock-chips.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 17 6月, 2020 1 次提交
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由 Johan Jonker 提交于
A test with the command below gives for example this error: arch/arm/boot/dts/rk3288-tinker.dt.yaml: tsadc: otp-gpio: {'phandle': [[54]], 'rockchip,pins': [[0, 10, 0, 118]]} is not of type 'array' 'gpio' is a sort of reserved nodename and should not be used for pinctrl in combination with 'rockchip,pins', so change nodes that end with 'gpio' to end with 'pin' or 'pins'. make ARCH=arm dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/ dtschema/schemas/gpio/gpio.yaml Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200524160636.16547-1-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 19 5月, 2020 1 次提交
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由 Johan Jonker 提交于
There are 2 identical '#include' for 'rk3288-power.h', so remove one of them. Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200403180159.13387-1-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 17 3月, 2020 5 次提交
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由 Johan Jonker 提交于
An experimental test with the command below gives for example this error: arch/arm/boot/dts/rk3036-evb.dt.yaml: i2s@10220000: '#address-cells', '#size-cells' do not match any of the regexes: 'pinctrl-[0-9]+' '#address-cells' and '#size-cells' are not a valid property for i2s nodes, so remove them. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/rockchip-i2s.yaml Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200311162524.19748-2-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Johan Jonker 提交于
Current dts files with 'i2s' nodes are manually verified. In order to automate this process rockchip-i2s.txt has to be converted to yaml. In the new setup dtbs_check with rockchip-i2s.yaml expect clocks and clock-names values in the same order. Fix this for some older Rockchip models. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/rockchip-i2s.yaml Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200311162524.19748-1-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Johan Jonker 提交于
A test with the command below gives for example this error: arch/arm/boot/dts/rv1108-evb.dt.yaml: usb@30140000: 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+' 'clock-names' is not a valid property name for usb_host nodes with compatible string 'generic-ehci', so remove them. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/generic-ehci.yaml Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200312171441.21144-1-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Johan Jonker 提交于
Current dts files with 'spdif' nodes are manually verified. In order to automate this process rockchip-spdif.txt has to be converted to yaml. In the new setup dtbs_check with rockchip-spdif.yaml expect clocks and clock-names values in the same order. Fix this for some older Rockchip models. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/rockchip-spdif.yaml Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200312172240.21362-2-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Katsuhiro Suzuki 提交于
This patch enables to use DMAC for all UARTs that are connected to dmac_peri core for Rochchip RK3288. Only uart2 is connected different DMAC (dmac_bus_s) so keep current settings on this patch. Signed-off-by: NKatsuhiro Suzuki <katsuhiro@katsuster.net> Link: https://lore.kernel.org/r/20200315095115.10106-1-katsuhiro@katsuster.netSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 11 3月, 2020 1 次提交
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由 Johan Jonker 提交于
A test with the command below gives for example this error: arch/arm/boot/dts/rk3188-bqedison2qc.dt.yaml: amba: $nodename:0: 'amba' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' AMBA is a open standard for the connection and management of functional blocks in a SoC. It's compatible with 'simple-bus', so fix this error by adding 'bus' to all Rockchip 'amba' nodes. make ARCH=arm dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/ schemas/simple-bus.yaml Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200302153047.17101-1-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 01 3月, 2020 1 次提交
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由 Johan Jonker 提交于
A test with the command below gives for example these errors: arch/arm/boot/dts/rk3288-evb-act8846.dt.yaml: bus_intmem@ff700000: $nodename:0: 'bus_intmem@ff700000' does not match '^sram(@.*)?' arch/arm/boot/dts/rk3288-evb-rk808.dt.yaml: bus_intmem@ff700000: $nodename:0: 'bus_intmem@ff700000' does not match '^sram(@.*)?' 'rockchip-pmu-sram.txt' inherit properties from 'sram.yaml'. Fix this error by adding 'sram' to the bus_intmem nodename in 'rk3288.dtsi'. But 'sram' is also a node name already in use. To prevent confusion rename it to 'pmu_sram'. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sram/sram.yaml Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200228155354.27206-3-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 19 1月, 2020 1 次提交
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由 Johan Jonker 提交于
Current dts files with 'dwmmc' nodes are manually verified. In order to automate this process rockchip-dw-mshc.txt has to be converted to yaml. In the new setup rockchip-dw-mshc.yaml will inherit properties from mmc-controller.yaml and synopsys-dw-mshc-common.yaml. 'dwmmc' will no longer be a valid name for a node, so change them all to 'mmc' Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200115185244.18149-1-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 14 10月, 2019 1 次提交
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由 Ezequiel Garcia 提交于
RK3288 SoC VOPs have optional support Gamma LUT setting, which requires specifying the Gamma LUT address in the devicetree. Signed-off-by: NEzequiel Garcia <ezequiel@collabora.com> Reviewed-by: NDouglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191010194351.17940-4-ezequiel@collabora.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 01 10月, 2019 1 次提交
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由 Douglas Anderson 提交于
This just adds in another field of what's stored in the e-fuse on rk3288. Though I can't personally promise that every rk3288 out there has the CPU ID stored in the eFuse at this location, there is some evidence that it is correct: - This matches what was in the Chrome OS 3.14 branch (see EFUSE_CHIP_UID_OFFSET and EFUSE_CHIP_UID_LEN) for rk3288. - The upstream rk3399 dts file has this same data at the same offset and with the same length, indiciating that this is likely common for several modern Rockchip SoCs. Signed-off-by: NDouglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20190919142611.1.I309434f00a2a9be71e4437991fe08abc12f06e2e@changeidSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 06 6月, 2019 1 次提交
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由 Douglas Anderson 提交于
This adds the "unwedge" pinctrl entries introduced by a recent dw_hdmi change that can unwedge the dw_hdmi i2c bus in some cases. It's expected that any boards using this would add: pinctrl-names = "default", "unwedge"; pinctrl-0 = <&hdmi_ddc>; pinctrl-1 = <&hdmi_ddc_unwedge>; Note that this isn't added by default because some boards may choose to mux i2c5 for their DDC bus (if that is more tested for them). Signed-off-by: NDouglas Anderson <dianders@chromium.org> Reviewed-by: NSean Paul <sean@poorly.run> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 04 6月, 2019 1 次提交
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由 John Keeping 提交于
This is the same as the other PWMs on this SoC and uses 3 cells. Signed-off-by: NJohn Keeping <john@metanate.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 22 5月, 2019 4 次提交
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由 Matthias Kaehlcke 提交于
The NPLL is the only safe way to generate 500 MHz for the GPU. The downstream Chrome OS 3.14 kernel ('official' kernel for veyron devices) re-purposes NPLL to HDMI and hence disables the OPP for the GPU (see https://crrev.com/c/1574579). Disable it here as well to keep in sync and avoid problems in case someone decides to re-purpose NPLL. Signed-off-by: NMatthias Kaehlcke <mka@chromium.org> Reviewed-by: NDouglas Anderson <dianders@chromium.org> [moved from veyron to general rk3288, as tying up the NPLL for a not-that-helpful opp (not really fast but will still generate quite a bit of heat) doesn't make so much sense when it will keep us from supporting other display modes in the future] Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Matthias Kaehlcke 提交于
Currently the CPUs are used as cooling devices of the rk3288 GPU thermal zone. The CPUs are also configured as cooling devices in the CPU thermal zone, which indirectly helps with cooling the GPU thermal zone, since the CPU and GPU temperatures are correlated on the rk3288. Configure the ARM Mali Midgard GPU as cooling device for the GPU thermal zone instead of the CPUs. Signed-off-by: NMatthias Kaehlcke <mka@chromium.org> Reviewed-by: NDouglas Anderson <dianders@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Matthias Kaehlcke 提交于
The Mali GPU of the rk3288 can be used as cooling device, add a #cooling-cells entry for it. Signed-off-by: NMatthias Kaehlcke <mka@chromium.org> Reviewed-by: NDouglas Anderson <dianders@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Douglas Anderson 提交于
This is similar to commit e6186820 ("arm64: dts: rockchip: Arch counter doesn't tick in system suspend"). Specifically on the rk3288 it can be seen that the timer stops ticking in suspend if we end up running through the "osc_disable" path in rk3288_slp_mode_set(). In that path the 24 MHz clock will turn off and the timer stops. To test this, I ran this on a Chrome OS filesystem: before=$(date); \ suspend_stress_test -c1 --suspend_min=30 --suspend_max=31; \ echo ${before}; date ...and I found that unless I plug in a device that requests USB wakeup to be active that the two calls to "date" would show that fewer than 30 seconds passed. NOTE: deep suspend (where the 24 MHz clock gets disabled) isn't supported yet on upstream Linux so this was tested on a downstream kernel. Signed-off-by: NDouglas Anderson <dianders@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 20 5月, 2019 1 次提交
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由 Caesar Wang 提交于
We use the new PWM IP on RK3288, but the PWM's clock indeed incorrect. Signed-off-by: NCaesar Wang <caesar.wang@rock-chips.com> Signed-off-by: NDouglas Anderson <dianders@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 03 5月, 2019 2 次提交
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由 Douglas Anderson 提交于
The "host" USB port on rk3288 has a hardware errata where we've got to assert a PHY reset whenever we see a remote wakeup. Add that quirk property to the device tree. Signed-off-by: NDouglas Anderson <dianders@chromium.org> Reviewed-by: NMatthias Kaehlcke <mka@chromium.org> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Douglas Anderson 提交于
Let's hook up the resets to the three USB PHYs on rk3288 as per the bindings. This is in preparation for a future patch that will set the "snps,reset-phy-on-wake" on the host port. Signed-off-by: NDouglas Anderson <dianders@chromium.org> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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- 12 4月, 2019 1 次提交
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由 Matthias Kaehlcke 提交于
The value was determined with the following method: - take CPUs 1-3 offline - for each OPP - set cpufreq min and max freq to OPP freq - start dhrystone benchmark - measure CPU power consumption during 10s - calculate Cx for OPPx - Cx = (Px - P1) / (Vx²fx - V1²f1) [1] using the following units: mW / Ghz / V [2] - C = avg(C2, ..., Cn) [1] see commit 4daa001a ("arm64: dts: juno: Add cpu dynamic-power-coefficient information") [2] https://patchwork.kernel.org/patch/10493615/#22158551 FTR, these are the values for the different OPPs: freq (kHz) mV Px (mW) Cx 126000 900 39 216000 900 66 370 312000 900 95 372 408000 900 122 363 600000 900 177 359 696000 950 230 363 816000 1000 297 361 1008000 1050 404 362 1200000 1100 528 362 1416000 1200 770 377 1512000 1300 984 385 1608000 1350 1156 394 Signed-off-by: NMatthias Kaehlcke <mka@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 11 4月, 2019 1 次提交
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由 Heiko Stuebner 提交于
Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: NEmil Renner Berthing <esmil@mailme.dk> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 25 3月, 2019 2 次提交
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由 Douglas Anderson 提交于
They are pointless. As dtc points out: Warning (avoid_unnecessary_addr_size): /mipi@ff960000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Let's remove them. Signed-off-by: NDouglas Anderson <dianders@chromium.org> Reviewed-by: NMatthias Kaehlcke <mka@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Douglas Anderson 提交于
The device tree compiler yells like this: Warning (unit_address_vs_reg): /gpu-opp-table/opp@100000000: node has a unit name, but no reg property Let's match the cpu opp node names and use a dash. Signed-off-by: NDouglas Anderson <dianders@chromium.org> Reviewed-by: NMatthias Kaehlcke <mka@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 21 3月, 2019 1 次提交
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由 Douglas Anderson 提交于
It can be seen that 0xffb40000 < 0xffc01000, thus efuse comes first. Signed-off-by: NDouglas Anderson <dianders@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 18 3月, 2019 2 次提交
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由 Jonas Karlman 提交于
The following message can be seen during boot: rockchip-thermal ff280000.tsadc: Missing rockchip,grf property Fix this by adding rockchip,grf property to tsadc node. The warning itself is not relevant on rk3288 right now, as the tsadc doesn't need to set GRF-values at this point and only newer variants do. Signed-off-by: NJonas Karlman <jonas@kwiboo.se> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Jonas Karlman 提交于
The following error can be seen during boot: of: /cpus/cpu@501: Couldn't find opp node Change cpu nodes to use operating-points-v2 in order to fix this. Fixes: ce76de98 ("ARM: dts: rockchip: convert rk3288 to operating-points-v2") Cc: stable@vger.kernel.org Signed-off-by: NJonas Karlman <jonas@kwiboo.se> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 06 12月, 2018 1 次提交
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由 Ezequiel Garcia 提交于
Add the Video Processing Unit node for RK3288 SoC. Fix the VPU IOMMU node, which was disabled and lacking its power domain property. Reviewed-by: NTomasz Figa <tfiga@chromium.org> Signed-off-by: NEzequiel Garcia <ezequiel@collabora.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 19 11月, 2018 1 次提交
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由 Viresh Kumar 提交于
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 18 6月, 2018 2 次提交
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由 Viresh Kumar 提交于
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, OPP, clock latency) as well to make it all work. Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> [follow conversion to operating-points-v2] Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Heiko Stuebner 提交于
Operating points need to be present in each cpu core using it, not only the first one. With operating-points-v1 this would require duplicating this table into each cpu node. With opp-v2 we can share the same table on all nodes. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
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- 17 6月, 2018 1 次提交
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由 Klaus Goger 提交于
Update all 32bit rockchip devicetree files to use SPDX-License-Identifiers. All files except rk3288-veyron-analog-audio.dtsi (which is GPL 2.0 only) claim to be GPL and X11 while the actual license text is MIT. Use the MIT SPDX tag for them. Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Acked-by: NBrian Norris <briannorris@chromium.org> Acked-by: NMatthias Brugger <mbrugger@suse.com> Acked-by: NDouglas Anderson <dianders@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 16 4月, 2018 1 次提交
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由 Jeffy Chen 提交于
Add clocks in iommu nodes, since we are going to control clocks in rockchip iommu driver. Signed-off-by: NJeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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