提交 b72b0526 编写于 作者: E Ezequiel Garcia 提交者: Zheng Zengkai

ARM: dts: rockchip: Fix the timer clocks order

stable inclusion
from stable-5.10.53
commit 55014c38e73d00e88d152e9deb0fc8c01e755c9a
bugzilla: 175574 https://gitee.com/openeuler/kernel/issues/I4DTUX

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=55014c38e73d00e88d152e9deb0fc8c01e755c9a

--------------------------------

[ Upstream commit 7b46d674 ]

Fixed order is the device-tree convention.
The timer driver currently gets clocks by name,
so no changes are needed there.
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.com>
Link: https://lore.kernel.org/r/20210506111136.3941-3-ezequiel@collabora.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NChen Jun <chenjun102@huawei.com>
Acked-by: NWeilong Chen <chenweilong@huawei.com>
Signed-off-by: NChen Jun <chenjun102@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
上级 b88937db
...@@ -150,16 +150,16 @@ ...@@ -150,16 +150,16 @@
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>; reg = <0x2000e000 0x20>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>; clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
clock-names = "timer", "pclk"; clock-names = "pclk", "timer";
}; };
timer6: timer@200380a0 { timer6: timer@200380a0 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x200380a0 0x20>; reg = <0x200380a0 0x20>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
clock-names = "timer", "pclk"; clock-names = "pclk", "timer";
}; };
i2s0: i2s@1011a000 { i2s0: i2s@1011a000 {
......
...@@ -240,8 +240,8 @@ ...@@ -240,8 +240,8 @@
compatible = "rockchip,rk3288-timer"; compatible = "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x20>; reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>; clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "timer", "pclk"; clock-names = "pclk", "timer";
}; };
display-subsystem { display-subsystem {
......
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