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  1. 17 7月, 2020 1 次提交
    • T
      spi: atmel-quadspi: Use optimezed memcpy_fromio()/memcpy_toio() · b780c3f3
      由 Tudor Ambarus 提交于 
      Optimezed mem*io operations are defined for LE platforms, use them.

The ARM and !ARCH_EBSA110 dependencies for COMPILE_TEST were added
only for the _memcpy_fromio()/_memcpy_toio() functions. Drop these
dependencies.

Tested unaligned accesses on both sama5d2 and sam9x60 QSPI controllers
using SPI NOR flashes, everything works ok. The following performance
improvement can be seen when running mtd_speedtest:

sama5d2_xplained (mx25l25635e)
- before:
	mtd_speedtest: eraseblock write speed is 983 KiB/s
	mtd_speedtest: eraseblock read speed is 6150 KiB/s
- after:
	mtd_speedtest: eraseblock write speed is 1055 KiB/s
	mtd_speedtest: eraseblock read speed is 20144 KiB/s

sam9x60ek (sst26vf064b)
- before:
	mtd_speedtest: eraseblock write speed is 4770 KiB/s
	mtd_speedtest: eraseblock read speed is 8062 KiB/s
- after:
	mtd_speedtest: eraseblock write speed is 4524 KiB/s
	mtd_speedtest: eraseblock read speed is 21186 KiB/s
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200716043139.565734-1-tudor.ambarus@microchip.comSigned-off-by: NMark Brown <broonie@kernel.org>
      b780c3f3
  3. 19 6月, 2020 2 次提交
  5. 16 6月, 2020 3 次提交
  7. 29 5月, 2020 3 次提交
  9. 12 5月, 2020 1 次提交
  11. 27 4月, 2020 1 次提交
  13. 13 3月, 2020 1 次提交
  15. 12 3月, 2020 2 次提交
    • C
      spi: add support for mediatek spi-nor controller · 881d1ee9
      由 Chuanhong Guo 提交于 
      This is a driver for mtk spi-nor controller using spi-mem interface.
The same controller already has limited support provided by mtk-quadspi
driver under spi-nor framework and this new driver is a replacement
for the old one.

Comparing to the old driver, this driver has following advantages:
1. It can handle any full-duplex spi transfer up to 6 bytes, and
   this is implemented using generic spi interface.
2. It take account into command opcode properly. The reading routine
   in this controller can only use 0x03 or 0x0b as opcode on 1-1-1
   transfers, but old driver doesn't implement this properly. This
   driver checks supported opcode explicitly and use (1) to perform
   unmatched operations.
3. It properly handles SFDP reading. Old driver can't read SFDP
   due to the bug mentioned in (2).
4. It can do 1-2-2 and 1-4-4 fast reading on spi-nor. These two ops
   requires parsing SFDP, which isn't possible in old driver. And
   the old driver is only flagged to support 1-1-2 mode.
5. It takes advantage of the DMA feature in this controller for
   long reads and supports IRQ on DMA requests to free cpu cycles
   from polling status registers on long DMA reading. It achieves
   up to 17.5MB/s reading speed (1-4-4 mode) which is way faster
   than the old one. IRQ is implemented as optional to maintain
   backward compatibility.
Signed-off-by: NChuanhong Guo <gch981213@gmail.com>
Link: https://lore.kernel.org/r/20200306085052.28258-3-gch981213@gmail.comSigned-off-by: NMark Brown <broonie@kernel.org>
      881d1ee9
    • J
      spi: Stop selecting MTD_SPI_NOR for SPI_HISI_SFC_V3XX · caef2df1
      由 John Garry 提交于 
      By selecting MTD_SPI_NOR for SPI_HISI_SFC_V3XX, we may introduce unmet
dependencies:

WARNING: unmet direct dependencies detected for MTD_SPI_NOR
  Depends on [m]: MTD [=m] && SPI_MASTER [=y]
  Selected by [y]:
  - SPI_HISI_SFC_V3XX [=y] && SPI [=y] && SPI_MASTER [=y] && (ARM64 && ACPI [=y] || COMPILE_TEST [=y]) && HAS_IOMEM [=y]

Since MTD_SPI_NOR is only selected by SPI_HISI_SFC_V3XX for practical
reasons - slave devices use the spi-nor driver, enabled by MTD_SPI_NOR -
just drop it.
Signed-off-by: NJohn Garry <john.garry@huawei.com>

Link: https://lore.kernel.org/r/1583948115-239907-1-git-send-email-john.garry@huawei.comSigned-off-by: NMark Brown <broonie@kernel.org>
      caef2df1
  17. 10 3月, 2020 1 次提交
  19. 06 3月, 2020 1 次提交
  21. 13 2月, 2020 1 次提交
  23. 11 2月, 2020 2 次提交
  25. 10 1月, 2020 1 次提交
  27. 21 11月, 2019 1 次提交
  29. 19 10月, 2019 1 次提交
  31. 04 9月, 2019 1 次提交
  33. 30 8月, 2019 1 次提交
  35. 01 8月, 2019 1 次提交
  37. 04 6月, 2019 1 次提交
  39. 21 5月, 2019 1 次提交
  41. 13 5月, 2019 1 次提交
  43. 05 4月, 2019 1 次提交
  45. 25 3月, 2019 1 次提交
    • S
      spi: mt7621: Move SPI driver out of staging · cbd66c62
      由 Stefan Roese 提交于 
      This patch moves the MT7621 SPI driver, which is used on some Ralink /
MediaTek MT76xx MIPS SoC's, out of the staging directory. No changes to
the source code are done in this patch.

This driver version was tested successfully on an MT7688 based platform
with an SPI NOR on CS0 and an SPI NAND on CS1 without any issues (so
far).

This patch also documents the devicetree bindings for the MT7621 SPI
device driver.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: NeilBrown <neil@brown.name>
Cc: Sankalp Negi <sankalpnegi2310@gmail.com>
Cc: Chuanhong Guo <gch981213@gmail.com>
Cc: John Crispin <john@phrozen.org>
Cc: Armando Miraglia <arma2ff0@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      cbd66c62
  47. 19 2月, 2019 1 次提交
  49. 29 1月, 2019 1 次提交
  51. 28 1月, 2019 1 次提交
    • Y
      spi: spi-mem: Add driver for NXP FlexSPI controller · a5356aef
      由 Yogesh Narayan Gaur 提交于 
      - Add driver for NXP FlexSPI host controller

(0) What is the FlexSPI controller?
 FlexSPI is a flexsible SPI host controller which supports two SPI
 channels and up to 4 external devices. Each channel supports
 Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
 data lines) i.e. FlexSPI acts as an interface to external devices,
 maximum 4, each with up to 8 bidirectional data lines.

 It uses new SPI memory interface of the SPI framework to issue
 flash memory operations to up to four connected flash
 devices (2 buses with 2 CS each).

(1) Tested this driver with the mtd_debug and JFFS2 filesystem utility
 on NXP LX2160ARDB and LX2160AQDS targets.
 LX2160ARDB is having two NOR slave device connected on single bus A
 i.e. A0 and A1 (CS0 and CS1).
 LX2160AQDS is having two NOR slave device connected on separate buses
 one flash on A0 and second on B1 i.e. (CS0 and CS3).
 Verified this driver on following SPI NOR flashes:
    Micron, mt35xu512ab, [Read - 1 bit mode]
    Cypress, s25fl512s, [Read - 1/2/4 bit mode]
Signed-off-by: NYogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: NBoris Brezillon <bbrezillon@kernel.org>
Tested-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      a5356aef
  53. 17 1月, 2019 2 次提交
    • A
      spi: ath79: Enable support for compile test · b172fd0c
      由 Alban Bedel 提交于 
      To allow building this driver in compile test we need to remove all
dependency on headers from arch/mips/include. To allow this we
explicitly define all the registers locally instead of using
ar71xx_regs.h and we move the platform data struct definition to
include/linux/platform_data/spi-ath79.h.
Signed-off-by: NAlban Bedel <albeu@free.fr>
Signed-off-by: NMark Brown <broonie@kernel.org>
      b172fd0c
    • A
      spi: ath79: Simplify ath79_spi_chipselect() · 797622d7
      由 Alban Bedel 提交于 
      First of all this callback was slightly misused to setup the clock
polarity at the beginning of a transfer. Beside being at the wrong
place, it is also useless as only SPI mode 1 is supported. Instead
just make sure the base value used for IOC is suitable to start a
transfer by clearing the clock and data bits during the controller
setup.

This also remove the last direct usage of the GPIO API, so we can
remove the direct dependency on GPIOLIB.
Signed-off-by: NAlban Bedel <albeu@free.fr>
Signed-off-by: NMark Brown <broonie@kernel.org>
      797622d7
  55. 08 1月, 2019 3 次提交
  57. 11 12月, 2018 1 次提交
  59. 14 11月, 2018 1 次提交