Optimezed mem*io operations are defined for LE platforms, use them.

The ARM and !ARCH_EBSA110 dependencies for COMPILE_TEST were added
only for the _memcpy_fromio()/_memcpy_toio() functions. Drop these
dependencies.

Tested unaligned accesses on both sama5d2 and sam9x60 QSPI controllers
using SPI NOR flashes, everything works ok. The following performance
improvement can be seen when running mtd_speedtest:

sama5d2_xplained (mx25l25635e)
- before:
	mtd_speedtest: eraseblock write speed is 983 KiB/s
	mtd_speedtest: eraseblock read speed is 6150 KiB/s
- after:
	mtd_speedtest: eraseblock write speed is 1055 KiB/s
	mtd_speedtest: eraseblock read speed is 20144 KiB/s

sam9x60ek (sst26vf064b)
- before:
	mtd_speedtest: eraseblock write speed is 4770 KiB/s
	mtd_speedtest: eraseblock read speed is 8062 KiB/s
- after:
	mtd_speedtest: eraseblock write speed is 4524 KiB/s
	mtd_speedtest: eraseblock read speed is 21186 KiB/s
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200716043139.565734-1-tudor.ambarus@microchip.comSigned-off-by: NMark Brown <broonie@kernel.org>

Currently we always defer idling of controllers to the SPI thread, the goal
being to ensure that we're doing teardown that's not suitable for atomic
context in an appropriate context and to try to batch up more expensive
teardown operations when the system is under higher load, allowing more
work to be started before the SPI thread is scheduled. However when the
controller does not require any substantial work to idle there is no need
to do this, we can instead save the context switch and immediately mark
the controller as idle. This is particularly useful for systems where there
is frequent but not constant activity.
Signed-off-by: NMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20200715163610.9475-1-broonie@kernel.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Convert clk_enable() to clk_prepare_enable() and clk_disable() to
clk_disable_unprepare() respectively in the spi-omap-uwire.c.
Signed-off-by: NQing Zhang <zhangqing@loongson.cn>
Link: https://lore.kernel.org/r/1594790807-32319-1-git-send-email-zhangqing@loongson.cnSigned-off-by: NMark Brown <broonie@kernel.org>

The OMAP-100k driver includes <linux/gpio.h> but does not
use any symbols from it, so drop the include.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20200714073357.34879-1-linus.walleij@linaro.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller
doesn't support DTR transactions. Since we don't use the default
supports_op(), which rejects all DTR ops, do that explicitly in our
supports_op().
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200623183030.26591-5-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller
doesn't support DTR transactions. Since we don't use the default
supports_op(), which rejects all DTR ops, do that explicitly in our
supports_op().
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200623183030.26591-4-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode. When it is "hex" an additional opcode byte based
is sent with the command whose value can be anything.

So, make opcode a 16-bit value and add a 'nbytes', similar to how
multiple address widths are handled.

Some places use sizeof(op->cmd.opcode). Replace them with op->cmd.nbytes

The spi-mxic and spi-zynq-qspi drivers directly use op->cmd.opcode as a
buffer. Now that opcode is a 2-byte field, this can result in different
behaviour depending on if the machine is little endian or big endian.
Extract the opcode in a local 1-byte variable and use that as the buffer
instead. Both these drivers would reject multi-byte opcodes in their
supports_op() hook anyway, so we only need to worry about single-byte
opcodes for now.

The above two changes are put in this commit to keep the series
bisectable.
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200623183030.26591-3-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200623183030.26591-2-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

This converts the two Freescale i.MX SPI drivers
Freescale i.MX (CONFIG_SPI_IMX) and Freescale i.MX LPSPI
(CONFIG_SPI_FSL_LPSPI) to use GPIO descriptors handled in
the SPI core for GPIO chip selects whether defined in
the device tree or a board file.

The reason why both are converted at the same time is
that they were both using the same platform data and
platform device population helpers when using
board files intertwining the code so this gives a cleaner
cut.

The platform device creation was passing a platform data
container from each boardfile down to the driver using
struct spi_imx_master from <linux/platform_data/spi-imx.h>,
but this was only conveying the number of chipselects and
an int * array of the chipselect GPIO numbers.

The imx27 and imx31 platforms had code passing the
now-unused platform data when creating the platform devices,
this has been repurposed to pass around GPIO descriptor
tables. The platform data struct that was just passing an
array of integers and number of chip selects for the GPIO
lines has been removed.

The number of chipselects used to be passed from the board
file, because this number also limits the number of native
chipselects that the platform can use. To deal with this we
just augment the i.MX (CONFIG_SPI_IMX) driver to support 3
chipselects if the platform does not define "num-cs" as a
device property (such as from the device tree). This covers
all the legacy boards as these use <= 3 native chip selects
(or GPIO lines, and in that case the number of chip selects
is determined by the core from the number of available
GPIO lines). Any new boards should use device tree, so
this is a reasonable simplification to cover all old
boards.

The LPSPI driver never assigned the number of chipselects
and thus always fall back to the core default of 1 chip
select if no GPIOs are defined in the device tree.

The Freescale i.MX driver was already partly utilizing
the SPI core to obtain the GPIO numbers from the device tree,
so this completes the transtion to let the core handle all
of it.

All board files and the core i.MX boardfile registration
code is augmented to account for these changes.

This has been compile-tested with the imx_v4_v5_defconfig
and the imx_v6_v7_defconfig.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Robin Gong <yibin.gong@nxp.com>
Cc: Trent Piepho <tpiepho@impinj.com>
Cc: Clark Wang <xiaoning.wang@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Link: https://lore.kernel.org/r/20200625200252.207614-1-linus.walleij@linaro.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.

Deterministic algorithm:
For each file:
  If not .svg:
    For each line:
      If doesn't contain `\bxmlns\b`:
        For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
	  If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
            If both the HTTP and HTTPS versions
            return 200 OK and serve the same content:
              Replace HTTP with HTTPS.
Signed-off-by: NAlexander A. Klimov <grandmaster@al2klimov.de>
Link: https://lore.kernel.org/r/20200708194400.22213-1-grandmaster@al2klimov.deSigned-off-by: NMark Brown <broonie@kernel.org>

The error exit label out_free is no longer being used, it is redundant
and can be removed.

Cleans up warning:
drivers/spi/spi-atmel.c:1680:1: warning: label ‘out_free’ defined but not used [-Wunused-label]

Fixes: 2d9a7446 ("spi: atmel: No need to call spi_master_put() if spi_alloc_master() failed")
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20200709101203.1374117-1-colin.king@canonical.comSigned-off-by: NMark Brown <broonie@kernel.org>

Use kthread_create_worker() helper to simplify the code. It uses
the kthread worker API the right way. It will eventually allow
to remove the FIXME in kthread_worker_fn() and add more consistency
checks in the future.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NPetr Mladek <pmladek@suse.com>
Link: https://lore.kernel.org/r/20200709065007.26896-1-m.szyprowski@samsung.comSigned-off-by: NMark Brown <broonie@kernel.org>

There is no need to call spi_master_put() if spi_alloc_master()
failed, it should return -ENOMEM directly.
Signed-off-by: NPeng Fan <fanpeng@loongson.cn>
Link: https://lore.kernel.org/r/1594111842-9468-1-git-send-email-fanpeng@loongson.cnSigned-off-by: NMark Brown <broonie@kernel.org>

In commit 0e3b8a81 ("spi: spi-geni-qcom: Add interconnect
support") the spi_geni_runtime_suspend() and spi_geni_runtime_resume()
became a bit slower.  Measuring on my hardware I see numbers in the
hundreds of microseconds now.

Let's use autosuspend to help avoid some of the overhead.  Now if
we're doing a bunch of transfers we won't need to be constantly
chruning.

The number 250 ms for the autosuspend delay was picked a bit
arbitrarily, so if someone has measurements showing a better value we
could easily change this.

Fixes: 0e3b8a81 ("spi: spi-geni-qcom: Add interconnect support")
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: Akash Asthana<akashast@codeaurora.org>
Link: https://lore.kernel.org/r/20200701174506.2.I9b8f6bb1e7e6d8847e2ed2cf854ec55678db427f@changeidSigned-off-by: NMark Brown <broonie@kernel.org>

In sun6i_spi_transfer_one() the RX FIFO Ready (SUN6I_INT_CTL_RF_RDY) is
unconditionally enabled.

A RX interrupt is only needed, if more data than fits into the FIFO is going to
be received during this transfer. As the RX-FIFO is drained during transfer
complete interrupt, enable the RX FIFO Ready interrupt only if the data doesn't
fit into the FIFO.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-11-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

In sun6i_spi_transfer_one() the Interrupt Control Register is written three
times. This patch collates the three writes into one.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-10-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

The function sun6i_spi_fill_fifo() is called with a length argument of
"sspi->fifo_depth" and "SUN6I_FIFO_DEPTH".

The driver reads the number of free bytes in the FIFO from the hardware and
uses the length argument to limit this value. This is not needed as the number
of free bytes in the FIFO is always less or equal the depth of the FIFO.

This patch removes the length argument and check.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-9-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

The function sun6i_spi_drain_fifo() is called with a length argument of
"sspi->fifo_depth" and "SUN6I_FIFO_DEPTH".

The driver reads the number of available bytes to read from the FIFO from the
hardware and uses the length argument to limit this value. This is not needed
as the FIFO can contain only the fifo depth number of bytes.

This patch removes the length argument and check.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-8-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

This patch introduces the function sun6i_spi_get_rx_fifo_count(), similar to
the existing sun6i_spi_get_tx_fifo_count(), to make the sun6i_spi_drain_fifo()
function a bit easier to read.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-7-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

This patch converts the manual shift+mask in sun6i_spi_get_tx_fifo_count() to
make use of FIELD_GET()
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20200706143443.9855-6-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

In sun6i_spi_transfer_one() the driver ensures that the length of the transfer
is smaller or equal to SUN6I_MAX_XFER_SIZE. This means the masking of the
length to SUN6I_MAX_XFER_SIZE can be skipped when writing the transfer length
into the registers.

This patch removes the useless masking of the transfer length to
SUN6I_MAX_XFER_SIZE.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-5-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

This patch removes an useless goto at the end of
sun6i_spi_transfer_one().
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-4-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

This patch implementes the reporting of the effectivly used speed_hz for the
transfer by setting tfr->effective_speed_hz.

See the following patch, which adds this feature to the SPI core for more
information:

    5d7e2b5e spi: core: allow reporting the effectivly used speed_hz for a transfer
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-3-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

A SPI transfer defines the _maximum_ speed of the SPI transfer. However the
driver doesn't take into account that the clock divider is always rounded down
(due to integer arithmetics). This results in a too high clock rate for the SPI
transfer.

E.g.: with a mclk_rate of 24 MHz and a SPI transfer speed of 10 MHz, the
original code calculates a reg of "0", which results in a effective divider of
"2" and a 12 MHz clock for the SPI transfer.

This patch fixes the issue by using DIV_ROUND_UP() instead of a plain
integer division.

While there simplify the divider calculation for the CDR1 case, use
order_base_2() instead of two ilog2() calculations.

Fixes: 3558fe90 ("spi: sunxi: Add Allwinner A31 SPI controller driver")
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-2-mkl@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

This switches the Lantiq SSC driver over to use GPIO descriptor
handling in the core.

The driver was already utilizing the core to look up and request
GPIOs from the device tree so this is a pretty small change
just switching it over to use descriptors directly instead.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Link: https://lore.kernel.org/r/20200625202149.209276-1-linus.walleij@linaro.orgSigned-off-by: NMark Brown <broonie@kernel.org>

This converts the IMG SPFI SPI driver to use GPIO descriptors
as obtained from the core instead of GPIO numbers.

The driver was already relying on the core code to look up
the GPIO numbers from the device tree and allocate memory for
storing state etc. By moving to use descriptors handled by
the core we can delete the setup/cleanup functions and
the device state handler that were only dealing with this.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Ionela Voinescu <ionela.voinescu@imgtec.com>
Cc: Sifan Naeem <sifan.naeem@imgtec.com>
Link: https://lore.kernel.org/r/20200625201422.208640-1-linus.walleij@linaro.orgSigned-off-by: NMark Brown <broonie@kernel.org>

The Nuvoton PSPI driver already uses the core to handle GPIO
chip selects but is using the old GPIO number method and
retrieveing the GPIOs in the probe() call.

Switch it over to using GPIO descriptors saving a bunch of
code and modernizing it.

Compile tested med ARMv7 multiplatform config augmented
with the Nuvoton arch and this driver.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20200625225759.273911-1-linus.walleij@linaro.orgSigned-off-by: NMark Brown <broonie@kernel.org>

On some SPI controllers (like spi-geni-qcom) setting the chip select
is a heavy operation.  For instance on spi-geni-qcom, with the current
code, is was measured as taking upwards of 20 us.  Even on SPI
controllers that aren't as heavy, setting the chip select is at least
something like a MMIO operation over some peripheral bus which isn't
as fast as a RAM access.

While it would be good to find ways to mitigate problems like this in
the drivers for those SPI controllers, it can also be noted that the
SPI framework could also help out.  Specifically, in some situations,
we can see the SPI framework calling the driver's set_cs() with the
same parameter several times in a row.  This is specifically observed
when looking at the way the Chrome OS EC SPI driver (cros_ec_spi)
works but other drivers likely trip it to some extent.

Let's solve this by caching the chip select state in the core and only
calling into the controller if there was a change.  We check not only
the "enable" state but also the chip select mode (active high or
active low) since controllers may care about both the mode and the
enable flag in their callback.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200629164103.1.Ied8e8ad8bbb2df7f947e3bc5ea1c315e041785a2@changeidSigned-off-by: NMark Brown <broonie@kernel.org>

The field mspi->reg_base is annotated as an __iomem pointer. Good.

However, this field is often assigned to a temporary variable:
before being used. For example:
	struct fsl_spi_reg *reg_base = mspi->reg_base;

But this variable is missing the __iomem annotation.
So, add the missing __iomem and make sparse & the bot happier.
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NLuc Van Oostenryck <luc.vanoostenryck@gmail.com>
Link: https://lore.kernel.org/r/20200622162611.83694-1-luc.vanoostenryck@gmail.comSigned-off-by: NMark Brown <broonie@kernel.org>

Add the memory driver for Renesas RPC-IF which registers either SPI or
HyperFLash device depending on the contents of the device tree subnode.
It also provides the absract "back end" device APIs that can be used by
the "front end" SPI/MTD drivers to talk to the real hardware.

Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/9a3606ec-d4d0-c63a-4fb6-631ab38e621c@cogentembedded.comSigned-off-by: NMark Brown <broonie@kernel.org>

The blind and counted loops are always called with nonzero count, so
convert them to do-while loops that lead to slightly more efficient
code generation. With GCC 8.3 this shaves off 1-2 instructions per
iteration in each case.
Signed-off-by: NRobin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/9242863077acf9a64e4b3720e479855b88d19e82.1592261248.git.robin.murphy@arm.comSigned-off-by: NMark Brown <broonie@kernel.org>

The IRQ handler only needs the struct spi_controller for the sake of
the completion at the end of a transfer. Passing the struct bcm2835_spi
directly as the IRQ data allows that level of indirection to be pushed
into the completion path for the reverse lookup, and avoided entirely
in all other cases.

This saves one explicit load in the critical path, plus (for a GCC 8.3
build) two registers worth of stack frame overhead.
Signed-off-by: NRobin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/6b401cb521539caffab21f05b4c8cba6c9d27c6e.1592261248.git.robin.murphy@arm.comSigned-off-by: NMark Brown <broonie@kernel.org>

It doesn't need a struct spi_controller, and every callsite has
already retrieved the appropriate struct bcm2835_spi, so just pass
that directly.
Signed-off-by: NRobin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/eca458ae1a0d3934d0627f90e25d294fefd4b13d.1592261248.git.robin.murphy@arm.comSigned-off-by: NMark Brown <broonie@kernel.org>

this patch use correct SPI_CFG2_REG offset.
Signed-off-by: Nleilk.liu <leilk.liu@mediatek.com>
Link: https://lore.kernel.org/r/20200701090020.7935-1-leilk.liu@mediatek.comSigned-off-by: NMark Brown <broonie@kernel.org>

The OMAP2 MCSPI has some kind of half-baked GPIO CS support:
it includes code like this:

  if (gpio_is_valid(spi->cs_gpio)) {
        ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
	(...)

But it doesn't parse the "cs-gpios" attribute in the device
tree to count the number of GPIOs or pick out the GPIO numbers
and put these in the SPI master's .cs_gpios property.

We complete the implementation of supporting CS GPIOs
from the device tree and switch it over to use the SPI core
for this.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20200625231257.280615-1-linus.walleij@linaro.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Setting the chip select on the Qualcomm geni SPI controller isn't
exactly cheap.  Let's cache the current setting and avoid setting the
chip select if it's already right.

Using "flashrom" to read or write the EC firmware on a Chromebook
shows roughly a 25% reduction in interrupts and a 15% speedup.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200626151946.1.I06134fd669bf91fd387dc6ecfe21d44c202bd412@changeidSigned-off-by: NMark Brown <broonie@kernel.org>

Add Intel Tiger Lake PCH-H PCI IDs.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Link: https://lore.kernel.org/r/20200625140041.745804-1-jarkko.nikula@linux.intel.comSigned-off-by: NMark Brown <broonie@kernel.org>

Add the MODULE_DEVICE_TABLE macro for the platform_device_id table to
allow proper creation of modalias strings and fix autoloading module for
this driver.
Signed-off-by: NXu Yilun <yilun.xu@intel.com>
Signed-off-by: NRuss Weight <russell.h.weight@intel.com>
Link: https://lore.kernel.org/r/1592962286-25752-3-git-send-email-yilun.xu@intel.comSigned-off-by: NMark Brown <broonie@kernel.org>

The driver is expected to support device ID "spi_altera" for MMIO accessed
devices, device ID "subdev_spi_altera" for indirect accessed devices. But
the platform bus will not try driver name match anymore if the platform
driver has an id_table. So the "spi_altera" should also be added to
id_table.
Signed-off-by: NXu Yilun <yilun.xu@intel.com>
Signed-off-by: NRuss Weight <russell.h.weight@intel.com>
Link: https://lore.kernel.org/r/1592962286-25752-2-git-send-email-yilun.xu@intel.comSigned-off-by: NMark Brown <broonie@kernel.org>

Add fallback pio feature in case  dma transfer failed before start.
Besides, another whole pio transfer including setup_transfer will be
issued by spi core, no need to restore jobs like commit bcd8e776 ("spi:
imx: fallback to PIO if dma setup failure").
Signed-off-by: NRobin Gong <yibin.gong@nxp.com>
Link: https://lore.kernel.org/r/1592347329-28363-3-git-send-email-yibin.gong@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>