This was accidentally disabled by commit 2a5fdc9a "ARM: dt: tegra:
invert status=disable vs status=okay".

Cc: <stable@vger.kernel.org> # v3.5 (file is named tegra-trimslice.dts there)
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

On TrimSlice, Tegra's USB1 port may be routed to either an external micro
USB port, or an internal USB->SATA bridge for SSD or HDD. This muxing is
controlled by a GPIO. Whilst not strictly a VBUS GPIO, the TrimSlice
board files caused this GPIO to be set appropriately to enable the SATA
bridge by passing it as the VBUS GPIO to the USB driver. Echo this same
configuration in device tree to enable the SATA bridge.

An alternative might be to implement a full USB bus mux driver. However,
that seems over-complex right now.

Cc: <stable@vger.kernel.org> # v3.5 (file is named tegra-trimslice.dts there)
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

It has been decided to use marvell, not mrvl, in the compatibility
property. Search & replace.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NRob Herring <rob.herring@calxeda.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

On spear320 device supported mode are:

   * AUTO_NET_SMII_MODE
   * AUTO_NET_MII_MODE
   * AUTO_EXP_MODE
   * SMALL_PRINTERS_MODE
   * EXTENDED_MODE

spear320-evb board is designed for EXTENDED_MODE only, hence it does not
boot correctly in current form where pinctrl part for some devices fail.

Configure and boot the SPEAr320 evaluation board in EXTENDED_MODE.
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

   - Correct interrupt bindings for uart, ethernet and pmu.
   - Added interrupt binding for keyboard.
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

Bindings for DMA channels are still under discussion and will
change once this has been resolved. Therefore we mark them
the newly added ones as preliminary. Let's hope nobody starts
relying on them...
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Some mxc processors have an edge_sel feature, which allows the IRQ to be
triggered by any edge.

This patch makes use of this feature if available, which skips mxc_flip_edge().

Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: NSascha Hauer <kernel@pengutronix.de>
Cc: <linux-arm-kernel@lists.infradead.org>
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add device nodes for the three instances of spi controllers in
EXYNOS5 platforms and enable instance SPI 1 for SMDK5250 board.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add device nodes for the three instances of spi controllers in
EXYNOS4 platforms. Enable instance SPI 2 for SMDKV310 board and
disable all spi instances for Origen board.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds Device Tree file for the CoreTile Express
A15x2 A7x3 (V2P-CA15_CA7).

Note that the A7 cpu nodes are commented out, as the
big.LITTLE-relevant patches are not upstreamed yet. Till
this time one can use the board with two A15 cores only,
keeping the A7s in reset by adding the following setting
to the board.txt file in Versatile Express configuration
tree:

SCC: 0x018 0x00001FFF
Signed-off-by: NPawel Moll <pawel.moll@arm.com>

... to enable use of LPAE, which extends physical address space
to 40 bits.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>

SMSC driver requires "vdd33a" and "vddvario" regulator supplies now.

Add fixed regulator describing 3V3 power line (in both motherboard's
Device Trees and the non-DT code) and force fixed regulator config
option if regulators framework is enabled.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>

Signed-off-by: NPawel Moll <pawel.moll@arm.com>

This patch configures the I2C bus timing registers according
to information passed via DT. Currently, 100kHz and 400kHz
modes are supported.

The TIMING2 register value is wrong in the documentation for
i.MX28! This was found and fixed by:
  Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

Any non-standard property should contain the vendor's identifier which
should be perpended onto the property name followed by a comma. This
aids in name-space collision prevention.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

During a Device Tree boot, all probing will now be completed on parse
of the Device Tree binary. In the same patch we remove platform
registration of the Real Time Clock.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Here we add a node for the AB8500 Real Time Clock in all devices
supporting the DB8500. The AB8500 RTC driver makes use of named
interrupts we provide support for this too.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The AB8500 driver has now been provided with IRQ domain support. This
means we can request IRQs from any of it's uses via Device Tree. This
patch advertises the AB8500 as an Interrupt Controller and provides the
correct calls in the format the driver expects.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This node has no properties. It merely allows probing of the
ab8500-debugfs driver during Device Tree initialisation.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Here we specify each of the ab8500 USB driver's seven IRQs, which the
driver references by name. We also apply regulator support for the
three used by the device.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This adds the DT node for the misc/ab8500-pwm driver. It will
allow probing of the driver during a Device Tree enabled boot.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This adds the DT node for the mfd/ab8500-sysctrl driver. It will
allow probing of the driver during a Device Tree enabled boot.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch configures the user LED on Snowball to double flash
every second or so, whilst it's still alive. This can give key
indications as to what the board is doing in the case of no
console output.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch provides support for the ab8500-gpadc driver.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch enables and illuminates the user_led on the
Snowball low-cost development board using DT. It also
removes initialisation carried out from platform code.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Allow proper initialisation for MMC via the mmci driver
for the Snowball low-cost development board using DT. At
the moment we continue to use DMA setup from platform code.
Once the DMA generic DT bindings have been completed we
can then port the remainder over to DT.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Add node for EXYNOS4 interrupt combiner controller.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Imx6q sabrelite board uses ecspi1 to connect a spi flash sst25vf016b,
we need to add pinctrl information for it in the dts, otherwise the
ecspi1 driver can't work and the connected flash is wrongly
detected as a mr25h256 flash like this:

m25p80 spi32766.0: found mr25h256, expected sst25vf016b
m25p80 spi32766.0: mr25h256 (32 Kbytes)

Cc: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: NHui Wang <jason77.wang@gmail.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

- add usbphy devices
- add usb host controller and otg devices
- add usb h1 vbus regulator
Signed-off-by: NRichard Zhao <richard.zhao@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

- add usb phy devices
- add usb controller devices
- add usb vbus regulators
Signed-off-by: NRichard Zhao <richard.zhao@freescale.com>
Tested-by: NSubodh Nijsure <snijsure@grid-net.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This adds real clock support to Calxeda Highbank SOC using the common
clock infrastructure.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
[mturquette@linaro.org: fixed up invalid writes to const struct member]
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Rename mxs dts files with soc name being the prefix, so that the board
dts file can be located easily by soc name, and we also gain the
consistency of naming.
Suggested-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Some pins are used as GPIOs in user space.
Signed-off-by: NLauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

AUART3 is not available anymore. Pins are used as GPIOs.
Signed-off-by: NLauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NLauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>