The commit 475d0094 (of: Improve prom_update_property() function)
changed prom_update_property interface, and causes the compile
error below.

  CC      arch/arm/mach-mxs/mach-mxs.o
arch/arm/mach-mxs/mach-mxs.c: In function ‘update_fec_mac_prop’:
arch/arm/mach-mxs/mach-mxs.c:216:4: error: too many arguments to function ‘prom_update_property’
include/linux/of.h:263:12: note: declared here

Update the caller update_fec_mac_prop to fix the error.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This was accidentally disabled by commit 2a5fdc9a "ARM: dt: tegra:
invert status=disable vs status=okay".

Cc: <stable@vger.kernel.org> # v3.5 (file is named tegra-trimslice.dts there)
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

On TrimSlice, Tegra's USB1 port may be routed to either an external micro
USB port, or an internal USB->SATA bridge for SSD or HDD. This muxing is
controlled by a GPIO. Whilst not strictly a VBUS GPIO, the TrimSlice
board files caused this GPIO to be set appropriately to enable the SATA
bridge by passing it as the VBUS GPIO to the USB driver. Echo this same
configuration in device tree to enable the SATA bridge.

An alternative might be to implement a full USB bus mux driver. However,
that seems over-complex right now.

Cc: <stable@vger.kernel.org> # v3.5 (file is named tegra-trimslice.dts there)
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

It has been decided to use marvell, not mrvl, in the compatibility
property. Search & replace.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

The last argument of orion_ge00_init() is actually the error
interrupt, so we should be using the correct value here.
Signed-off-by: NHannes Reinecke <hare@suse.de>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

Commit 98d9986c (ARM: Kirkwood: Replace clock gating) and the fix 5fb2ce
(ARM: Kirkwood: clk_register_gate_fn: add fn assignment) introduced a custom
variant of clock gating which allows to define a function to be called
before gating the clock off.

This is used to disable the SATA and PCIe PHYs if the respective clocks
are unused after initialization.

However, of these two drivers, the SATA driver may be compiled as a module.
The driver re-enables the clocks at module init but the PHYs stay disabled.

Since the custom clock gating disabled the PHYs when gating the clock off,
it should also re-enable them when enabling the clock gate.  This is done by
adding a second function that may be used to enable the PHYs.
Signed-off-by: NSimon Baatz <gmbnomis@gmail.com>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

Marvell engineers tell us:

	It seems that many units use the RUNIT clock.
	SPI, UART, NAND, TWSI, ...
	So it's not possible to clock gate it.

Currently the SPI, NAND and TWSI driver will clk_prepaure_enable()
this clk, but since we have no idea what ... is, and turning this clk
off results in a hard lock, unconditionally enable runit.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NSimon Baatz <gmbnomis@gmail.com>

Due to automatic merge of a613163d
"ARM: integrator: convert to common clock" and
56a34b03 "ARM: versatile: Make
plat-versatile clock optional" two platforms: Integrator and
Versatile Express now select both COMMON_CLK and
PLAT_VERSATILE_CLOCK which breaks building them. Fixed now.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Name the regulator as per board schematics and adds its
supply name info in regulator data.
Add the always on fixed regulator to refer the battery supply.

Use this fixed regulator for input supply of some of PMIC
regulator

This patch was originally part of a 2-patch series. Patch 2 got applied
to the regulator tree as 7c7fac30 "regulator: tps6586x: add support for
input supply" without this patch. This broke regulator support on
Harmony.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: added dependency info to commit description]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NCong Wang <amwang@redhat.com>

Adds header file protection macros.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This enables the new EXYNOS5 platforms in the defconfig, and enables DT
support on EXYNOS4.

Other options enabled: USB host, EXT3/4, regulators and tps65090,
networking and a few of the common usb ethernet adapters as well as the
smsc911x controller used on some boards.

I enabled EFI_PARTITION, since it's used on some filesystem images I'm
using. I didn't see a need to keep Solaris and BSD partition format
still enabled.

Finally, framebuffer console, logo and fonts were enabled.

Note that enabling some of these options introduces build coverage
previously missing, thus introducing a few build errors and warnings
for which fixes have been sent out already.
Signed-off-by: NOlof Johansson <olof@lixom.net>
[kgene.kim@samsung.com: restored exynos4_defconfig from original]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This SoC has two PWM channels
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

LPC32xx SoC has a 128 bits unique id that can be used as a system
serial number, if none has been provided by atags or dt.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Obsoleted since commit 7c5763b8 ("drivers:
misc: Remove MISC_DEVICES config option")
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

Correcting spelling typo in mach-omap2
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NRob Herring <rob.herring@calxeda.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

On Origen board, we have 2 status leds, so adding them as heartbeat and
mmc0 by default. The patch basically adds the platform data required by
leds-gpio driver.
Signed-off-by: NRicardo Salveti de Araujo <ricardo.salveti@linaro.org>
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

With the greater use of deferred probes we need to be more sure that
initdata is actually used only at system init rather than being used
by devices when they probe (which could happen after the main kernel
init has completed and is much more likely to now).
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Adds missing .reserve field to SMDKC210 board.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

DRM core device and FIMD DRM platform device support is added to
SMDK4212 & SMDK4412 boards.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Commit 1c20c2 (spi: s3c64xx: Remove the 'set_level' callback from
controller data) didn't update all the users, breaking the build.
Fix that.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Since clk_xusbxti.rate is 24Mhz as a default,
so we don't need to set that when it is 24Mhz.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Removed system.h as it only contained an inline for arch_reset()
Changed the existing board files to use .restart in there machine
descriptions.

Added device tree support for the restart controller.
Device tree support for mach-vt8500 is still a work-in-progress.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

On spear320 device supported mode are:

   * AUTO_NET_SMII_MODE
   * AUTO_NET_MII_MODE
   * AUTO_EXP_MODE
   * SMALL_PRINTERS_MODE
   * EXTENDED_MODE

spear320-evb board is designed for EXTENDED_MODE only, hence it does not
boot correctly in current form where pinctrl part for some devices fail.

Configure and boot the SPEAr320 evaluation board in EXTENDED_MODE.
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

   - Correct interrupt bindings for uart, ethernet and pmu.
   - Added interrupt binding for keyboard.
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk
ids are exceeding this predefined limit.

This patch is intended to rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    ras_gen1_synth_gate_clk -> ras_syn1_gclk
    pll3_48m -> pll3_
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk
ids are exceeding this predefined limit.

This patch is intended to rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    ras_gen1_synth_gate_clk -> ras_syn1_gclk
    ras_pll3_48m -> ras_pll3_
    pll3_48m -> pll3_
Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Bindings for DMA channels are still under discussion and will
change once this has been resolved. Therefore we mark them
the newly added ones as preliminary. Let's hope nobody starts
relying on them...
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the necessary dtb-$(CONFIG_...) entries so that "make dtbs"
generates the Device Tree Blobs that correspond to the selected mvebu
SoCs.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch fixes "bug: interrupts were enabled early" due to
do_settimeofday() which used in common code for clps711x-platform.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This override does not allow support for multiple machines in a single core.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Since we are trying to do to support multiple machines in a single kernel,
we need to eliminate the use of __initcall to be used for all machines.
Using .init_early call solves this problem.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Some mxc processors have an edge_sel feature, which allows the IRQ to be
triggered by any edge.

This patch makes use of this feature if available, which skips mxc_flip_edge().

Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: NSascha Hauer <kernel@pengutronix.de>
Cc: <linux-arm-kernel@lists.infradead.org>
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Adds G2D related clock entries for SMDK4X12 boards.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

G2D clock registers are different in EXYNOS4210 and EXYNOS4X12 SoCs.
Hence moving the SoC specific G2D clock entries from common clock file
(clock-exynos4.c) to EXYNOS4210 specific clock file (clock-exynos4210.c).
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>