Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- Refacotr PSR to follow correct module pattern
- fix eDP only working on sink index 0.
Signed-off-by: NSylvia Tsai <sylvia.tsai@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NZeyu Fan <Zeyu.Fan@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This change will cache cursor attributes and reprogram them
when enabling cursor after power gating if the attributes were not
yet reprogrammed
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAmy Zhang <Amy.Zhang@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NZeyu Fan <Zeyu.Fan@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

dc_commit_surfaces_to_stream() function currently
is handle's only one plane at a time.
This will not work if multiple planes have to be set to a crtc.

The functionality of dc_commit_surfaces_to_stream() with this patch
is slit into
1. Accumulate and initialise all the surfaces that needs to be
   set to a crtc.
2. Update the intialised set of surfaces to the steam in one go.

Hence dc_commit_surfaces_to_stream() is renamed to init_surfaces().
Once all the planes requested by user space are initialised,
dc_commit_surfaces_to_stream() shall sequentially populates *updates,
 *flip_addr, *plane_info and *scaling_info for all surfaces.

BUG: SWDEV-119421
TEST: (On Chromium OS for Stoney Only)
* Chromium UI comes up, on both eDP & DP.
* 'new_surface_count' now changes as per user input for e.g for
  all below run tests its 2, without this patch for the below
  tests it used to be 1
* Executed below tests to see YUV(underlay) & RGB planes on eDP
plane_test --format XR24 --size 500x100 -p --format YV12 --size 500x500
plane_test --format AR24 --size 500x50 -p --format YV12 --size 150x150
plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768
Signed-off-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NShirish S <shirish.s@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch updates the planes default offsets to
the appropriate ones, and aligns the pitch to 64 bits.

BUG=SWDEV-119421
TEST=Boots to UI on jadeite
TEST=
     plane_test --format AR24 --size 500x50 -p --format YV12 --size 500x500
     plane_test --format AR24 --size 500x50 -p --format YV12 --size 1280x720
     plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768
Signed-off-by: NShirish S <shirish.s@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch populates the YUV surface configurations.

Tests: (On Chromium OS for Stoney Only)
builds without any errors.
Signed-off-by: NShirish S <shirish.s@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This will allow us to carry it from check to commit
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This will be needed to clean up context once we add it to private
atomic state.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This should make things simpler when we try to rework this later when we
pass validate_context from atomic_check to atomic_commit.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NJordan Lazare <Jordan.Lazare@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If we need to update our context we can allocate memory.
No need to keep temporary memory for this.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- Update BTR/LFC logic so that V_TOTAL_MIN/MAX will take affect on current frame
- Add in FreeSync update to MPO code path
Signed-off-by: NEric Cook <Eric.Cook@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NVitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

They could differ between ASIC generations
Signed-off-by: NSylvia Tsai <sylvia.tsai@amd.com>
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NJordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- Set stream signal type to be SST when setting non-tile timing on MST
  tiled display.
  - Disable MST on sink after disabling MST link.
  - Enable MST on sink before enabling MST link.
Signed-off-by: NDing Wang <Ding.Wang@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

In MST case during removal of remote sink its descriptor pointer wasn't freed corectly.
Signed-off-by: NLeon Elazar <leon.elazar@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- Adding dm controlled signal type in dc_stream
- Adding fallback to dvi signal when output signal is hdmi and the connector
  type is not
Signed-off-by: NSylvia Tsai <sylvia.tsai@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NSylvia Tsai <Sylvia.Tsai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

1. get_ss_info_from_atombios function was allocating the memory populating the provided pointer
but them freeing the memory.
Since the pointer was return as a valid value, we are trying to free the same memory during clock resource destruction
Signed-off-by: NLeon Elazar <leon.elazar@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- Remove x,y hotspot from dc_cursor_attributes. Only program it
  through setPosition.
Signed-off-by: NZeyu Fan <Zeyu.Fan@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NZeyu Fan <Zeyu.Fan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Make sure we do not program a hw pageflip inside vblank 'n' iff the
atomic flip is comitted while inside the same vblank 'n'. We must
defer such a flip by one refresh cycle to vblank 'n+1', unless this
is a DRM_MODE_PAGE_FLIP_ASYNC async pageflip, which must always
execute as soon as possible.

Without this, pageflips programmed via X11 GLX_OML_sync_control extensions
glXSwapBuffersMscOML(..., target_msc, ...); call and/or via DRI3/Present
PresentPixmap(..., target_msc, ...); request will complete one vblank
too early whenever target_msc > current_msc + 1, ie. more than 1 vblank
in the future. In such a case, the call of the pageflip ioctl() would be
triggered by a queued drmWaitVblank() vblank event, which itself gets
dispatched inside the vblank one frame before the target_msc vblank.

Testing with this patch does no longer show any problems with
OML_sync_control swap scheduling or flip completion timestamps.
Tested on R9 380 Tonga.

v2: Add acked/r-b by Harry and Michel.
v3: Feedback from Andrey: Must not wait an extra frame for
    DRM_MODE_PAGE_FLIP_ASYNC flips.
Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com>
Acked-by: Harry Wentland <harry.wentland@amd.com> (v1)
Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com>
Reviewed-by: NAndrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>