提交 07c84c7a 编写于 作者: D Ding Wang 提交者: Alex Deucher

drm/amd/display: Fix for tile MST

- Set stream signal type to be SST when setting non-tile timing on MST
  tiled display.
  - Disable MST on sink after disabling MST link.
  - Enable MST on sink before enabling MST link.
Signed-off-by: NDing Wang <Ding.Wang@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 b64875fe
......@@ -1250,6 +1250,9 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx)
if (link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
return DC_OK;
/* set the sink to MST mode before enabling the link */
dp_enable_mst_on_sink(link, true);
return enable_link_dp(pipe_ctx);
}
......
......@@ -2453,3 +2453,16 @@ bool dc_link_dp_set_test_pattern(
return true;
}
void dp_enable_mst_on_sink(struct core_link *link, bool enable)
{
unsigned char mstmCntl;
core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
if (enable)
mstmCntl |= DP_MST_EN;
else
mstmCntl &= (~DP_MST_EN);
core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
}
......@@ -129,6 +129,9 @@ void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal)
return;
dp_disable_link_phy(link, signal);
/* set the sink to SST mode after disabling the link */
dp_enable_mst_on_sink(link, false);
}
bool dp_set_hw_training_pattern(
......
......@@ -57,4 +57,6 @@ void detect_dp_sink_caps(struct core_link *link);
bool is_dp_active_dongle(const struct core_link *link);
void dp_enable_mst_on_sink(struct core_link *link, bool enable);
#endif /* __DC_LINK_DP_H__ */
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