Add support for the USB3 PHY used by the secondary usb controller on sm8150
Signed-off-by: NJonathan Marek <jonathan@marek.ca>
Tested-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200524021416.17049-3-jonathan@marek.caSigned-off-by: NVinod Koul <vkoul@kernel.org>

The primary USB PHY on sm8250 sets some values differently for the second
lane. This makes it possible to represent that.
Signed-off-by: NJonathan Marek <jonathan@marek.ca>
Tested-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200524021416.17049-2-jonathan@marek.caSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add QMP USB PHY found in IPQ8074
Co-developed-by: NBalaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: NBalaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: NSivaprakash Murugesan <sivaprak@codeaurora.org>
Tested-by: NSricharan R <sricharan@codeaurora.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1591625479-4483-4-git-send-email-sivaprak@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Adding QMP v3 USB3 PHY support for SC7180.
Adding only usb phy reset in the list to avoid
reset of DP block.
Signed-off-by: NSandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1589510358-3865-5-git-send-email-sanm@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

It's possible that struct qmp_phy_cfg->regs references an array that is
smaller than the possible register lookups that is going to be
performed, with the resulting out-of-bounds read resulting in undefined
behavior.

One such example is when during qcom_qmp_phy_com_init() performs a
qphy_setbits() on entry QPHY_PCS_POWER_DOWN_CONTROL (i.e. 17) with
msm8996_ufsphy_regs_layout only being 12 entries long.

Solve this by inflating all "regs_layout" arrays to ensure that any
remaining entries are zero-initialized, as expected by the code.

Fixes: e4d8b05a ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB")
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200515013643.2081941-1-bjorn.andersson@linaro.orgSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The UFS QMP v4 PHY has a largely different register set versus USB and
PCIe.  Rename the register offsets to denote that the value is specific for
the UFS PCS register.
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

The register map for SM8150 QMP USB SSPHY has moved
QPHY_POWER_DOWN_CONTROL to a different offset.  Allow for
an offset in the register table to override default value
if it is a DP capable PHY.
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-5-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add support for SM8150 QMP USB3 PHY with the necessary
initialization sequences as well as additional QMP V4
register definitions.
Signed-off-by: NJack Pham <jackp@codeaurora.org>
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

The SM8250 UFS PHY can run off the same initialization sequence as
SM8150, but add the compatible to allow future changes.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>

The PCIe PHY initialization requires the attached device to be present,
which is primarily achieved by the PCI controller driver.  So move the
logic from init/exit to power_on/power_off.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NJohn Stultz <john.stultz@linaro.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The support for the 14nm MSM8996 UFS PHY is currently handled by the
UFS-specific 14nm QMP driver, due to the earlier need for additional
operations beyond the standard PHY API.

Add support for this PHY to the common QMP driver, to allow us to remove
the old driver.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add the GEN3 QHP PCIe PHY found in SDM845.
Tested-by: NJulien Massot <jmassot@softbankrobotics.com>
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

qcom_qmp_phy_init() is extended to support the additional register
writes needed in PCS MISC and the appropriate sequences and resources
are defined for the GEN2 PCIe QMP PHY found in SDM845.
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
then deassert it, so add the QPHY_SW_RESET register which does this.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NCan Guo <cang@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

SM8150 QMPY phy for UFS and onwards the PHY_SW_RESET is present in PHY's
PCS register so we should not mark no_pcs_sw_reset for sm8150 and
onwards
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NCan Guo <cang@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

We already write to QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_com_init()
before invoking qcom_qmp_phy_configure() so remove the duplicate write.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

We already define register offsets so use them in register layout.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NCan Guo <cang@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

It's typical for the QHP PHY to take slightly above 1ms to initialize,
so increase the timeout of the PHY ready check to 10ms - as already done
in the downstream PCIe driver.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NEvan Green <evgreen@chromium.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

SM8150 UFS PHY is v4 of QMP phy. Add support for V4 QMP phy register
defines and support for SM8150 QMP UFS PHY.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Despite extensive testing of commit 885bd765 ("phy: qcom-qmp: Correct
READY_STATUS poll break condition") I failed to conclude that the
PHYSTATUS bit of the PCS_STATUS register used in PCIe and USB3 falls as
the PHY gets ready. Similar to the prior bug with UFS the code will
generally get past the check before the transition and thereby
"succeed".

Correct the name of the register used PCIe and USB3 PHYs, replace
mask_pcs_ready with a constant expression depending on the type of the
PHY and check for the appropriate ready state.

Cc: stable@vger.kernel.org
Cc: Vivek Gautam <vivek.gautam@codeaurora.org>
Cc: Evan Green <evgreen@chromium.org>
Cc: Niklas Cassel <niklas.cassel@linaro.org>
Reported-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Fixes: 885bd765 ("phy: qcom-qmp: Correct READY_STATUS poll break condition")
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Each iteration of for_each_available_child_of_node() puts the previous
node, but in the case of a return from the middle of the loop, there is
no put, thus causing a memory leak. Hence create a new label,
err_node_put, that puts the previous node (child) before returning the
required value. Also include the statement pm_runtime_disable() under
this label in order to avoid repetition among mid-loop return
conditions. Edit the mid-loop return statements to instead go to this
new label err_node_put.
Issue found with Coccinelle.
Signed-off-by: NNishka Dasgupta <nishkadg.linux@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

readl_poll_timeout() calls usleep_range() to sleep between reads.
usleep_range() doesn't work efficiently for tiny values.

Raise the polling delay in qcom_qmp_phy_enable() to bring it in line
with the delay in qcom_qmp_phy_com_init().
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

'mask_com_pcs_ready' is only useful if 'has_phy_com_ctrl' is true.
Since msm8998_pciephy_cfg.has_phy_com_ctrl is false, let's drop
msm8998_pciephy_cfg.mask_com_pcs_ready altogether.
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

After issuing a PHY_START request to the QMP, the hardware documentation
states that the software should wait for the PCS_READY_STATUS to become
1.

With the introduction of commit c9b58979 ("phy: qcom: Utilize UFS
reset controller") an additional 1ms delay was introduced between the
start request and the check of the status bit. This greatly increases
the chances for the hardware to actually becoming ready before the
status bit is read.

The result can be seen in that UFS PHY enabling is now reported as a
failure in 10% of the boots on SDM845, which is a clear regression from
the previous rare/occasional failure.

This patch fixes the "break condition" of the poll to check for the
correct state of the status bit.

Unfortunately PCIe on 8996 and 8998 does not specify the mask_pcs_ready
register, which means that the code checks a bit that's always 0. So the
patch also fixes these, in order to not regress these targets.

Fixes: 73d7ec89 ("phy: qcom-qmp: Add msm8998 PCIe QMP PHY support")
Fixes: e78f3d15 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Cc: stable@vger.kernel.org
Cc: Evan Green <evgreen@chromium.org>
Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Vivek Gautam <vivek.gautam@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NNiklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Tested-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Documentation for this PHY, and the proper configuration settings,
is *not* publicly available. Therefore the initialization sequence
is copied wholesale from downstream:

https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998-v2.dtsi?h=LE.UM.1.3.r3.25#n372Reviewed-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The phy code was using implicit sequencing between the PHY driver
and the UFS driver to implement certain hardware requirements.
Specifically, the PHY reset register in the UFS controller needs
to be deasserted before serdes start occurs in the PHY.

Before this change, the code was doing this by utilizing the two
phy callbacks, phy_init() and phy_poweron(), as "init step 1" and
"init step 2", where the UFS driver would deassert reset between
these two steps.

This makes it challenging to power off the regulators in suspend,
as regulators are initialized in init, not in poweron(), but only
poweroff() is called during suspend, not exit().

For UFS, move the actual firing up of the PHY to phy_poweron() and
phy_poweroff() callbacks, rather than init()/exit(). UFS calls
phy_poweroff() during suspend, so now all clocks and regulators for
the phy can be powered down during suspend.

QMP is a little tricky because the PHY is also shared with PCIe and
USB3, which have their own definitions for init() and poweron(). Rename
the meaty functions to _enable() and _disable() to disentangle from the
PHY core names, and then create two different ops structures: one for
UFS and one for the other PHY types.

In phy-qcom-ufs, remove the 'is_powered_on' and 'is_started' guards,
as the generic PHY code does the reference counting. The
14/20nm-specific init functions get collapsed into the generic power_on()
function, with the addition of a calibrate() callback specific to 14/20nm.
Signed-off-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Move the PHY reset from ufs-qcom into the respective PHYs. This will
allow us to merge the two phases of UFS PHY initialization.
Signed-off-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Use same init sequence as sdm845.
Reviewed-by: NJeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

MSM8998 contains a single QMP v3 USB3 phy similar to the existing sdm845
support.
Signed-off-by: NJeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Register a simple clock provider for the PHY pipe clock sources so that
device tree users can point at these clocks via phandles to the lane
nodes.
Signed-off-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Tested-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Utilize the newly fixed up DT bindings to get the tx2 and rx2 register
regions for the second lane of dual-lane PHYs. Before this change,
the driver was simply using lane one's register region and adding
0x400, which reached well beyond the DT-specified register
allocation. This would have been a crash were it not for the page size
on ARM64. Fix the driver not to rely on the magic of virtual memory by
using the newly specified DT register regions for tx2 and rx2.

In order to support existing device trees, this change also contains a
fallback mode for when those new register regions don't exist, which
reverts to the original behavior of overreaching and prints a complaint.
Signed-off-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Currently the attempt to add support for Ethernet interface mode PHY
(MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and
duplicate there values from phy_interface_t enum (or introduce more PHY
callbacks) [1]. Both approaches are ineffective and would lead to fast
bloating of enum phy_mode or struct phy_ops in the process of adding more
PHYs for different subsystems which will make them unmaintainable.

As discussed in [1] the solution could be to introduce dual level PHYs mode
configuration - PHY mode and PHY submode. The PHY mode will define generic
PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem
specific interface mode. The last is usually already defined in
corresponding subsystem headers (phy_interface_t for Ethernet, enum
usb_device_speed for USB).

This patch is cumulative change which refactors PHY framework code to
support dual level PHYs mode configuration - PHY mode and PHY submode. It
extends .set_mode() callback to support additional parameter "int submode"
and converts all corresponding PHY drivers to support new .set_mode()
callback declaration.
The new extended PHY API
 int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
is introduced to support dual level PHYs mode configuration and existing
phy_set_mode() API is converted to macros, so PHY framework consumers do
not need to be changed (~21 matches).

[1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.comSigned-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add UFS PHY support to make SDM845 UFS work with common PHY framework.
Signed-off-by: NCan Guo <cang@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Move MSM8996 specific PHY vreg list struct name to a genernal one as it is
used by all PHYs. Add a specific field to handle dual lane situation.
Signed-off-by: NCan Guo <cang@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

All PHYs should be powered on before register configuration starts. And
only PCIe PHYs need an extra power control before deasserts reset state.
Signed-off-by: NCan Guo <cang@codeaurora.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The -EPROBE_DEFER virus demands special case code to avoid printing
error messages when the error is only -EPROBE_DEFER.  Spread the virus
to a new host: qcom_qmp_phy_probe().  Specifically handle when our
regulators might not be ready yet.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

QMP V3 UNI PHY is a single lane USB3 PHY without support
for DisplayPort (DP).
Main difference from DP combo QMPv3 PHY is that UNI PHY
doesn't have dual RX/TX lanes and no separate DP_COM
block for configuration related to type-c or DP.
Also remove "qcom,qmp-v3-usb3-phy" compatible string which
was earlier added for sdm845 only as there wouldn't be
any user of same.
While at it, fix has_pwrdn_delay attribute for USB-DP
PHY configuration and.
Reviewed-by: NEvan Green <evgreen@chromium.org>
Signed-off-by: NManu Gautam <mgautam@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

QMP PHY for USB/PCIE requires pipe_clk for locking of
retime buffers at the pipe interface. Driver checks for
PHY_STATUS without enabling pipe_clk due to which
phy_init() fails with initialization timeout.
Though pipe_clk is output from PHY (after PLL is programmed
during initialization sequence) to GCC clock_ctl and then fed
back to PHY but for PHY_STATUS register to reflect successful
initialization pipe_clk from GCC must be present.
Since, clock driver now ignores status_check for pipe_clk on
clk_enable/disable, driver can safely enable/disable pipe_clk
from phy_init/exit.
Signed-off-by: NManu Gautam <mgautam@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The SPDX identifier is a legally binding shorthand, which
can be used instead of the full boiler plate text.
Signed-off-by: NManu Gautam <mgautam@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>