Add support for the USB3 PHY used by the secondary usb controller on sm8150
Signed-off-by: NJonathan Marek <jonathan@marek.ca>
Tested-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200524021416.17049-3-jonathan@marek.caSigned-off-by: NVinod Koul <vkoul@kernel.org>

The primary USB PHY on sm8250 sets some values differently for the second
lane. This makes it possible to represent that.
Signed-off-by: NJonathan Marek <jonathan@marek.ca>
Tested-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200524021416.17049-2-jonathan@marek.caSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add ipq8074 qusb2 device compatible for high speed usb support.
Signed-off-by: NSivaprakash Murugesan <sivaprak@codeaurora.org>
Tested-by: NSricharan R <sricharan@codeaurora.org>
Reviewed-by: NSricharan R <sricharan@codeaurora.org>
Link: https://lore.kernel.org/r/1591625479-4483-5-git-send-email-sivaprak@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add QMP USB PHY found in IPQ8074
Co-developed-by: NBalaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: NBalaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: NSivaprakash Murugesan <sivaprak@codeaurora.org>
Tested-by: NSricharan R <sricharan@codeaurora.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1591625479-4483-4-git-send-email-sivaprak@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Adding QMP v3 USB3 PHY support for SC7180.
Adding only usb phy reset in the list to avoid
reset of DP block.
Signed-off-by: NSandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1589510358-3865-5-git-send-email-sanm@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

It's possible that struct qmp_phy_cfg->regs references an array that is
smaller than the possible register lookups that is going to be
performed, with the resulting out-of-bounds read resulting in undefined
behavior.

One such example is when during qcom_qmp_phy_com_init() performs a
qphy_setbits() on entry QPHY_PCS_POWER_DOWN_CONTROL (i.e. 17) with
msm8996_ufsphy_regs_layout only being 12 entries long.

Solve this by inflating all "regs_layout" arrays to ensure that any
remaining entries are zero-initialized, as expected by the code.

Fixes: e4d8b05a ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB")
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200515013643.2081941-1-bjorn.andersson@linaro.orgSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The UFS QMP v4 PHY has a largely different register set versus USB and
PCIe.  Rename the register offsets to denote that the value is specific for
the UFS PCS register.
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

The register map for SM8150 QMP USB SSPHY has moved
QPHY_POWER_DOWN_CONTROL to a different offset.  Allow for
an offset in the register table to override default value
if it is a DP capable PHY.
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-5-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add support for SM8150 QMP USB3 PHY with the necessary
initialization sequences as well as additional QMP V4
register definitions.
Signed-off-by: NJack Pham <jackp@codeaurora.org>
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs.  There
are potentially multiple instances of this UTMI PHY on the
SOC, all which can utilize this driver.  The V2 driver will
have a different register map compared to V1.
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Reviewed-by: NPhilipp Zabel <pza@pengutronix.de>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NStephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/1588636467-23409-3-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs.
The driver sets up HS and SS phys.
Signed-off-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NRobert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Link: https://lore.kernel.org/r/20200503201823.531757-1-robert.marko@sartura.hrSigned-off-by: NVinod Koul <vkoul@kernel.org>

The AHB clock must be on for qcom_snps_hsphy_init() to be able to write
the initialization sequence to the hardware, so move the clock
enablement to phy init and exit.

Fixes: 67b27dbe ("phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver")
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The SM8250 UFS PHY can run off the same initialization sequence as
SM8150, but add the compatible to allow future changes.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>

This patch fixes a regression in 5.7-rc1+

In commit 8fe75cd4 ("phy: qcom-qusb2: Add generic QUSB2 V2
PHY support"), the change was made to add "qcom,qusb2-v2-phy"
as a generic compat string. However the change also removed
the "qcom,sdm845-qusb2-phy" compat string, which is documented
in the binding and already in use.

This patch re-adds the "qcom,sdm845-qusb2-phy" compat string
which allows the driver to continue to work with existing dts
entries such as found on the db845c.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 8fe75cd4 ("phy: qcom-qusb2: Add generic QUSB2 V2 PHY support")
Reported-by: NYongQin Liu <yongqin.liu@linaro.org>
Signed-off-by: NJohn Stultz <john.stultz@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Added support for overriding bias-ctrl-value,charge-ctrl-value and
hsdisc-trim-value params for QUSB2 V2 PHY
Signed-off-by: NSandeep Maheswaram <sanm@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Added new structure for overriding tuning parameters in QUSB2 V2 PHY as the
override params are increased due to usage of generic QUSB2 V2 phy table.
Signed-off-by: NSandeep Maheswaram <sanm@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add generic QUSB2 V2 PHY table so the respective phys
can use the same table.
Signed-off-by: NSandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the
20nm and 28nm process nodes.

Based on Sriharsha Allenki's <sallenki@codeaurora.org> original code.

[bod: Removed dependency on extcon.
      Switched to gpio-usb-conn to handle VBUS On/Off
      Switched to usb-role-switch to bind gpio-usb-conn to DWC3]
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: Sriharsha Allenki's <sallenki@codeaurora.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Tested-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually
paired with Synopsys DWC3 USB controllers on Qualcomm SoCs.

The PHY can come in two flavours femtoPHY or picoPHY. This commit adds
support for the femtoPHY with the possibility of extending to the picoPHY
with additional future commits. Both PHYs are on a 28 nanometer process
node.

[bod: Updated qcom_snps_hsphy_set_mode to match new method signature
      Added disjunct on mode > 0
      Removed regulator_set_voltage() in favour of setting floor in dts
      Removed 'snps' and from driver name
      Extended commit log to mention femtoPHY and picoPHY for future
      reference.]
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Tested-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The PCIe PHY initialization requires the attached device to be present,
which is primarily achieved by the PCI controller driver.  So move the
logic from init/exit to power_on/power_off.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NJohn Stultz <john.stultz@linaro.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The support for the 14nm MSM8996 UFS PHY is currently handled by the
UFS-specific 14nm QMP driver, due to the earlier need for additional
operations beyond the standard PHY API.

Add support for this PHY to the common QMP driver, to allow us to remove
the old driver.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add the GEN3 QHP PCIe PHY found in SDM845.
Tested-by: NJulien Massot <jmassot@softbankrobotics.com>
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

qcom_qmp_phy_init() is extended to support the additional register
writes needed in PCS MISC and the appropriate sequences and resources
are defined for the GEN2 PCIe QMP PHY found in SDM845.
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
then deassert it, so add the QPHY_SW_RESET register which does this.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NCan Guo <cang@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

SM8150 QMPY phy for UFS and onwards the PHY_SW_RESET is present in PHY's
PCS register so we should not mark no_pcs_sw_reset for sm8150 and
onwards
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NCan Guo <cang@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

We already write to QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_com_init()
before invoking qcom_qmp_phy_configure() so remove the duplicate write.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

We already define register offsets so use them in register layout.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NCan Guo <cang@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Clang warns:

../drivers/phy/qualcomm/phy-qcom-apq8064-sata.c:83:4: warning:
misleading indentation; statement is not part of the previous 'if'
[-Wmisleading-indentation]
                 usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
                 ^
../drivers/phy/qualcomm/phy-qcom-apq8064-sata.c:80:3: note: previous
statement is here
                if (readl_relaxed(addr) & mask)
                ^
1 warning generated.

This warning occurs because there is a space after the tab on this line.
Remove it so that the indentation is consistent with the Linux kernel
coding style and clang no longer warns.

Fixes: 1de990d8 ("phy: qcom: Add driver for QCOM APQ8064 SATA PHY")
Link: https://github.com/ClangBuiltLinux/linux/issues/816Signed-off-by: NNathan Chancellor <natechancellor@gmail.com>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

It's typical for the QHP PHY to take slightly above 1ms to initialize,
so increase the timeout of the PHY ready check to 10ms - as already done
in the downstream PCIe driver.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NEvan Green <evgreen@chromium.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch corrects the SPDX License Identifier style in
header files related to PHY drivers for Qualcomm platforms.
For C header files Documentation/process/license-rules.rst
mandates C-like comments (opposed to C source files where
C++ style should be used).

Changes made by using a script provided by Joe Perches here:
https://lkml.org/lkml/2019/2/7/46.
Suggested-by: NJoe Perches <joe@perches.com>
Signed-off-by: NNishad Kamdar <nishadkamdar@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Commit f0b5c2c9 ("phy: qcom-usb-hs: Replace the extcon API")
switched from extcon_register_notifier() to the resource-managed
API, i.e. devm_extcon_register_notifier().

This is problematic in this case, because the extcon notifier
is dynamically registered/unregistered whenever the PHY is powered
on/off. The resource-managed API does not unregister the notifier
until the driver is removed, so as soon as the PHY is power cycled,
attempting to register the notifier again results in:

	double register detected
	WARNING: CPU: 1 PID: 182 at kernel/notifier.c:26 notifier_chain_register+0x74/0xa0
	Call trace:
	 ...
	 extcon_register_notifier+0x74/0xb8
	 devm_extcon_register_notifier+0x54/0xb8
	 qcom_usb_hs_phy_power_on+0x1fc/0x208
	 ...

... and USB stops working after plugging the cable out and in
another time.

The easiest way to fix this is to make a partial revert of
commit f0b5c2c9 ("phy: qcom-usb-hs: Replace the extcon API")
and avoid using the resource-managed API in this case.

Fixes: f0b5c2c9 ("phy: qcom-usb-hs: Replace the extcon API")
Signed-off-by: NStephan Gerhold <stephan@gerhold.net>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

SM8150 UFS PHY is v4 of QMP phy. Add support for V4 QMP phy register
defines and support for SM8150 QMP UFS PHY.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Despite extensive testing of commit 885bd765 ("phy: qcom-qmp: Correct
READY_STATUS poll break condition") I failed to conclude that the
PHYSTATUS bit of the PCS_STATUS register used in PCIe and USB3 falls as
the PHY gets ready. Similar to the prior bug with UFS the code will
generally get past the check before the transition and thereby
"succeed".

Correct the name of the register used PCIe and USB3 PHYs, replace
mask_pcs_ready with a constant expression depending on the type of the
PHY and check for the appropriate ready state.

Cc: stable@vger.kernel.org
Cc: Vivek Gautam <vivek.gautam@codeaurora.org>
Cc: Evan Green <evgreen@chromium.org>
Cc: Niklas Cassel <niklas.cassel@linaro.org>
Reported-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Fixes: 885bd765 ("phy: qcom-qmp: Correct READY_STATUS poll break condition")
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Each iteration of for_each_available_child_of_node() puts the previous
node, but in the case of a return from the middle of the loop, there is
no put, thus causing a memory leak. Hence create a new label,
err_node_put, that puts the previous node (child) before returning the
required value. Also include the statement pm_runtime_disable() under
this label in order to avoid repetition among mid-loop return
conditions. Edit the mid-loop return statements to instead go to this
new label err_node_put.
Issue found with Coccinelle.
Signed-off-by: NNishka Dasgupta <nishkadg.linux@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

readl_poll_timeout() calls usleep_range() to sleep between reads.
usleep_range() doesn't work efficiently for tiny values.

Raise the polling delay in qcom_qmp_phy_enable() to bring it in line
with the delay in qcom_qmp_phy_com_init().
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

'mask_com_pcs_ready' is only useful if 'has_phy_com_ctrl' is true.
Since msm8998_pciephy_cfg.has_phy_com_ctrl is false, let's drop
msm8998_pciephy_cfg.mask_com_pcs_ready altogether.
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

After issuing a PHY_START request to the QMP, the hardware documentation
states that the software should wait for the PCS_READY_STATUS to become
1.

With the introduction of commit c9b58979 ("phy: qcom: Utilize UFS
reset controller") an additional 1ms delay was introduced between the
start request and the check of the status bit. This greatly increases
the chances for the hardware to actually becoming ready before the
status bit is read.

The result can be seen in that UFS PHY enabling is now reported as a
failure in 10% of the boots on SDM845, which is a clear regression from
the previous rare/occasional failure.

This patch fixes the "break condition" of the poll to check for the
correct state of the status bit.

Unfortunately PCIe on 8996 and 8998 does not specify the mask_pcs_ready
register, which means that the code checks a bit that's always 0. So the
patch also fixes these, in order to not regress these targets.

Fixes: 73d7ec89 ("phy: qcom-qmp: Add msm8998 PCIe QMP PHY support")
Fixes: e78f3d15 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Cc: stable@vger.kernel.org
Cc: Evan Green <evgreen@chromium.org>
Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Vivek Gautam <vivek.gautam@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NNiklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Tested-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NEnrico Weigelt <info@metux.net>
Reviewed-by: NKate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: NAllison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 and
  only version 2 as published by the free software foundation this
  program is distributed in the hope that it will be useful but
  without any warranty without even the implied warranty of
  merchantability or fitness for a particular purpose see the gnu
  general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 294 file(s).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NAllison Randal <allison@lohutok.net>
Reviewed-by: NAlexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The error return from the call to clk_prepare_enable is not being assigned
to variable ret even though ret is being used to check if the call failed.
Fix this by adding in the missing assignment.

Addresses-Coverity: ("Logically dead code")
Fixes: 891a96f6 ("phy: qcom-qusb2: Add support for runtime PM")
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>