Add support for the USB3 PHY used by the secondary usb controller on sm8150
Signed-off-by: NJonathan Marek <jonathan@marek.ca>
Tested-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200524021416.17049-3-jonathan@marek.caSigned-off-by: NVinod Koul <vkoul@kernel.org>

The primary USB PHY on sm8250 sets some values differently for the second
lane. This makes it possible to represent that.
Signed-off-by: NJonathan Marek <jonathan@marek.ca>
Tested-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200524021416.17049-2-jonathan@marek.caSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add ipq8074 qusb2 device compatible for high speed usb support.
Signed-off-by: NSivaprakash Murugesan <sivaprak@codeaurora.org>
Tested-by: NSricharan R <sricharan@codeaurora.org>
Reviewed-by: NSricharan R <sricharan@codeaurora.org>
Link: https://lore.kernel.org/r/1591625479-4483-5-git-send-email-sivaprak@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add QMP USB PHY found in IPQ8074
Co-developed-by: NBalaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: NBalaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: NSivaprakash Murugesan <sivaprak@codeaurora.org>
Tested-by: NSricharan R <sricharan@codeaurora.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1591625479-4483-4-git-send-email-sivaprak@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Fix up inconsistent usage of upper and lowercase letters in "Exynos"
name.

"EXYNOS" is not an abbreviation but a regular trademarked name.
Therefore it should be written with lowercase letters starting with
capital letter.

The lowercase "Exynos" name is promoted by its manufacturer Samsung
Electronics Co., Ltd., in advertisement materials and on website.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

Link: https://lore.kernel.org/r/20200617152803.17941-1-krzk@kernel.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

If CONFIG_ARCH_ROCKCHIP is not set but COMPILE_TEST is set, the file in
the subdir rockchip can not be built due to CONFIG_ARCH_ROCKCHIP check
in drivers/phy/Makefile.

Since the related configs in drivers/phy/rockchip/Kconfig depend on
ARCH_ROCKCHIP, so remove CONFIG_ARCH_ROCKCHIP check for subdir rockchip
in drivers/phy/Makefile.

The other CONFIG_ARCH_* about allwinner, amlogic, mediatek, renesas and
tegra have the same situation, so remove them too.
Signed-off-by: NTiezhu Yang <yangtiezhu@loongson.cn>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/1590412138-13903-2-git-send-email-yangtiezhu@loongson.cnSigned-off-by: NVinod Koul <vkoul@kernel.org>

The registers which are managed by the meson-gxl-usb3 PHY driver are
actually "USB control" registers (which are "glue" registers which
manage OTG detection and routing of the OTG capable port between the
DWC2 peripheral-only controller and the DWC3 host-only controller).

Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-g12a-usb
driver supports the USB control registers on GXL and GXM SoCs (these
were previously managed by the meson-gxl-usb3 PHY driver).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NFelipe Balbi <balbi@kernel.org>

ComboPhy subsystem provides PHYs for various
controllers like PCIe, SATA and EMAC.
Signed-off-by: NDilip Kota <eswara.kota@linux.intel.com>
Acked-By: NVinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/7b313826f46b9006a3ba98c0613e8f88f293a074.1589868358.git.eswara.kota@linux.intel.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Adding QMP v3 USB3 PHY support for SC7180.
Adding only usb phy reset in the list to avoid
reset of DP block.
Signed-off-by: NSandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1589510358-3865-5-git-send-email-sanm@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: NSanket Parmar <sparmar@cadence.com>
Link: https://lore.kernel.org/r/1589804053-14302-1-git-send-email-sparmar@cadence.comReviewed-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The SERDES PHY can support USB super-speed lane.
Add support for that.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Link: https://lore.kernel.org/r/20200513131254.10497-3-rogerq@ti.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The max_register property must be set in order to
show up the registers in debugfs.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Link: https://lore.kernel.org/r/20200513131254.10497-2-rogerq@ti.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

During different reboot cycles, USB PHY PLL may not always lock
during initialization and therefore can cause USB to be not usable.

Hence do not use internal FSM programming sequence for the USB
PHY initialization.

Fixes: 4dcddbb3 ("phy: sr-usb: Add Stingray USB PHY driver")
Signed-off-by: NBharat Gooty <bharat.gooty@broadcom.com>
Signed-off-by: NRayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Link: https://lore.kernel.org/r/20200513173947.10919-1-rayagonda.kokatanur@broadcom.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

It's possible that struct qmp_phy_cfg->regs references an array that is
smaller than the possible register lookups that is going to be
performed, with the resulting out-of-bounds read resulting in undefined
behavior.

One such example is when during qcom_qmp_phy_com_init() performs a
qphy_setbits() on entry QPHY_PCS_POWER_DOWN_CONTROL (i.e. 17) with
msm8996_ufsphy_regs_layout only being 12 entries long.

Solve this by inflating all "regs_layout" arrays to ensure that any
remaining entries are zero-initialized, as expected by the code.

Fixes: e4d8b05a ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB")
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200515013643.2081941-1-bjorn.andersson@linaro.orgSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Move private definitions from header to phy-omap-usb2.c file.
Get rid of unused data structures usb_dpll_params and omap_usb_phy_type.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Link: https://lore.kernel.org/r/20200515080518.26870-2-rogerq@ti.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

phy_ops are never modified and can therefore be made const to allow the
compiler to put it in read-only memory.

Before:
   text    data     bss     dec     hex filename
   7831    3144     128   11103    2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o

After:
   text    data     bss     dec     hex filename
   7959    3016     128   11103    2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o
Signed-off-by: NRikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200516120441.7627-2-rikard.falkeborn@gmail.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

A number of structs were not modified and can therefore be made const
to allow the compiler to put them in read-only memory.

In order to do so, update a few functions that don't modify there input
to take pointers to const.

Before:
   text    data     bss     dec     hex filename
  15511    6448      64   22023    5607 drivers/phy/broadcom/phy-brcm-usb.o

After:
   text    data     bss     dec     hex filename
  16058    5936      64   22058    562a drivers/phy/broadcom/phy-brcm-usb.o
Signed-off-by: NRikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200516120441.7627-4-rikard.falkeborn@gmail.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

phy_ops are never modified and can therefore be made const to allow the
compiler to put it in read-only memory.

Before:
   text    data     bss     dec     hex filename
   4310    1244       0    5554    15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o

After:
   text    data     bss     dec     hex filename
   4438    1116       0    5554    15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o
Signed-off-by: NRikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200516120441.7627-3-rikard.falkeborn@gmail.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The .init is used for one-time PHY's initialization, and .power_on
is called many times during the device lifecycle.
Signed-off-by: NPeter Chen <peter.chen@nxp.com>
Link: https://lore.kernel.org/r/20200513125605.5545-1-peter.chen@nxp.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

The 3.10 vendor kernel sets the ACA_ENABLE bit on Meson8b, Meson8m2 and
GXBB, but not on Meson8. Add a compatible string for Meson8m2 which also
sets that bit.
While here, also update the Kconfig text and MODULE_DESCRIPTION.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NThomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-7-martin.blumenstingl@googlemail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

The vendor driver unsets the set_iddig bit during power-on as well and
sets it when suspending the PHY. I did not notice this in the vendor
driver first, because it's part of the dwc_otg driver there (instead of
their PHY code). While here, also add all other REG_DBG_UART register
bit definitions.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NThomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-6-martin.blumenstingl@googlemail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Skip setting REG_ADP_BC_ACA_ENABLE on Meson8 SoCs and polling for the
REG_ADP_BC_ACA_PIN_FLOAT bit. The vendor also skips this part on Meson8
SoCs.
This fixes initialization of the host-only USB PHY on Meson8 which would
otherwise fail with "USB ID detect failed!".

Fixes: 4a3449d1 ("phy: meson8b-usb2: add support for the USB PHY on Meson8 SoCs")
Reported-by: NThomas Graichen <thomas.graichen@gmail.com>
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NThomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-5-martin.blumenstingl@googlemail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Using a MMIO regmap and switch to regmap_update_bits() to simplify the
code in the driver. Also switch to devm_platform_ioremap_resource()
instead of open-coding it. No functional changes intended.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NThomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-4-martin.blumenstingl@googlemail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

The Intel eMMC PHY is only present on Intel Lightning Mountain SoCs.
Add an architecture dependency to the PHY_INTEL_EMMC config symbol, to
avoid asking the user about it when configuring a kernel for a non-x86
architecture.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200507113626.24026-3-geert+renesas@glider.beSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Fix to return negative error code from some error handling
cases instead of 0, as done elsewhere in this function.

Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Reported-by: NHulk Robot <hulkci@huawei.com>
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Acked-by: NRoger Quadros <rogerq@ti.com>
Link: https://lore.kernel.org/r/20200507054109.110849-1-weiyongjun1@huawei.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Axe a clk that is unused in the driver.
Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: NTony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20200507203127.202197-1-christophe.jaillet@wanadoo.frSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The USB phy takes some time to reset, so make sure we give it to it. The
delay length was taken from the 4x12 phy driver.

This manifested in issues with the DWC2 driver since commit fe369e18
("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.")
where the endianness check would read the DWC ID as 0 due to the phy still
resetting, resulting in the wrong endian mode being chosen.
Signed-off-by: NJonathan Bakker <xc-racer2@live.ca>
Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.comSigned-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2.
According to the Cadence, this PHY is a legacy Module, and Sierra and
Torrent are later evolutions from it, and their sequence overlap is
minimal, meaning we cannot reuse either (Sierra & Torrent) of the PHY
drivers.
Signed-off-by: NPeter Chen <peter.chen@nxp.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The UFS QMP v4 PHY has a largely different register set versus USB and
PCIe.  Rename the register offsets to denote that the value is specific for
the UFS PCS register.
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

The register map for SM8150 QMP USB SSPHY has moved
QPHY_POWER_DOWN_CONTROL to a different offset.  Allow for
an offset in the register table to override default value
if it is a DP capable PHY.
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-5-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add support for SM8150 QMP USB3 PHY with the necessary
initialization sequences as well as additional QMP V4
register definitions.
Signed-off-by: NJack Pham <jackp@codeaurora.org>
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs.  There
are potentially multiple instances of this UTMI PHY on the
SOC, all which can utilize this driver.  The V2 driver will
have a different register map compared to V1.
Signed-off-by: NWesley Cheng <wcheng@codeaurora.org>
Reviewed-by: NPhilipp Zabel <pza@pengutronix.de>
Reviewed-by: NManu Gautam <mgautam@codeaurora.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NStephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/1588636467-23409-3-git-send-email-wcheng@codeaurora.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs.
The driver sets up HS and SS phys.
Signed-off-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NRobert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Link: https://lore.kernel.org/r/20200503201823.531757-1-robert.marko@sartura.hrSigned-off-by: NVinod Koul <vkoul@kernel.org>

The AHB clock must be on for qcom_snps_hsphy_init() to be able to write
the initialization sequence to the hardware, so move the clock
enablement to phy init and exit.

Fixes: 67b27dbe ("phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver")
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The SM8250 UFS PHY can run off the same initialization sequence as
SM8150, but add the compatible to allow future changes.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>

This patch fixes a regression in 5.7-rc1+

In commit 8fe75cd4 ("phy: qcom-qusb2: Add generic QUSB2 V2
PHY support"), the change was made to add "qcom,qusb2-v2-phy"
as a generic compat string. However the change also removed
the "qcom,sdm845-qusb2-phy" compat string, which is documented
in the binding and already in use.

This patch re-adds the "qcom,sdm845-qusb2-phy" compat string
which allows the driver to continue to work with existing dts
entries such as found on the db845c.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 8fe75cd4 ("phy: qcom-qusb2: Add generic QUSB2 V2 PHY support")
Reported-by: NYongQin Liu <yongqin.liu@linaro.org>
Signed-off-by: NJohn Stultz <john.stultz@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

For DisplayPort use we need to set WIZ_CONFIG_LANECTL register's
P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the
P_ENABLE bits of the same register are set to P_ENABLE instead of
P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable
the lane as needed. The DisplayPort mode is selected according to
"cdns,phy-type"-properties found in link subnodes under the managed
serdes (see "ti,sierra-phy-t0" and "ti,j721e-serdes-10g" devicetree
bindings for details). All other values of "cdns,phy-type"-property
but PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits
to force enable.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The usb_get_maximum_speed() function is part of the usb-common module,
so enable it by selecting the corresponding Kconfig symbol.

While at it, also make sure to depend on USB_SUPPORT because USB_PHY
requires that. This can lead to Kconfig conflicts if USB_SUPPORT is not
enabled while attempting to enable PHY_TEGRA_XUSB.
Reported-by: Nkbuild test robot <lkp@intel.com>
Suggested-by: NNathan Chancellor <natechancellor@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The usb_get_maximum_speed() function is part of the usb-common module,
so enable it by selecting the corresponding Kconfig symbol.

While at it, also make sure to depend on USB_SUPPORT because USB_PHY
requires that. This can lead to Kconfig conflicts if USB_SUPPORT is not
enabled while attempting to enable PHY_TEGRA_XUSB.
Reported-by: Nkbuild test robot <lkp@intel.com>
Suggested-by: NNathan Chancellor <natechancellor@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200330101038.2422389-1-thierry.reding@gmail.comSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The phy-gmii-sel can be only auto selected in Kconfig and now the pretty
complex Kconfig dependencies are defined for phy-gmii-sel driver, which
also need to be updated every time phy-gmii-sel is re-used for any new
networking driver.

Simplify Kconfig definition for phy-gmii-sel PHY driver - drop all
dependencies and from networking drivers and rely on using 'imply
PHY_TI_GMII_SEL' in Kconfig definitions for networking drivers instead.
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
Tested-by: NMurali Karicheri <m-karicheri2@ti.com>
Tested-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>