- 11 4月, 2019 1 次提交
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由 Peng Ma 提交于
Ls1028a SATA ecc address with more than 32 bit, so we should corrrect the address. Signed-off-by: NPeng Ma <peng.ma@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 03 4月, 2019 3 次提交
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由 Angus Ainslie (Purism) 提交于
Set ahb clock on sdma1 to get rid of "Timeout waiting for CH0" on the imx8mq. Signed-off-by: NAngus Ainslie (Purism) <angus@akkea.ca> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Angus Ainslie (Purism) 提交于
Fix a typo in the compatible string Signed-off-by: NAngus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: NDaniel Baluta <daniel.baluta@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Anson Huang 提交于
Add i.MX8QXP system controller watchdog support. Signed-off-by: NAnson Huang <Anson.Huang@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 29 3月, 2019 1 次提交
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由 Fabio Estevam 提交于
thermal-zones node does not have any register properties and thus shouldn't be placed inside the bus. Move thermal-zones node from soc node to root node in order to fix the following build warning with W=1: arch/arm64/boot/dts/freescale/imx8mq.dtsi:305.18-364.6: Warning (simple_bus_reg): /soc@0/bus@30000000/thermal-zones: missing or empty reg/ranges property Signed-off-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 26 3月, 2019 2 次提交
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由 Jacky Bai 提交于
Add basic dts support for i.MM8MM LPDDR4 EVK. Signed-off-by: NJacky Bai <ping.bai@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Jacky Bai 提交于
The i.MX8M Mini is new SOC of the i.MX8M family. it is focused on delivering the latest and greatest video and audio experience combining state-of-the-art media-specific features with high-performance processing while optimized for lowest power consumption. The i.MX 8M Mini Media Applications Processor is 14nm FinFET product of the growing i.MX8M family targeting the consumer & industrial market. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster with video and graphics accelerators This patch adds the basic dtsi support for i.MX8MM. Signed-off-by: NJacky Bai <ping.bai@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 22 3月, 2019 4 次提交
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由 Fabio Estevam 提交于
Move opp-table node from soc node to root node. opp-table node does not have any register properties and thus shouldn't be placed inside the bus. This fixes the following build warnings with W=1: arch/arm64/boot/dts/freescale/imx8mq.dtsi:687.28-703.5: Warning (simple_bus_reg): /soc@0/opp-table: missing or empty reg/ranges property Fixes: 64d26f8c ("arm64: dts: imx8mq: Add the opp table and cores opp properties") Signed-off-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Horia Geantă 提交于
crypto node alias is needed by U-boot to identify the node and perform fix-ups, like adding "fsl,sec-era" property or deleting a job ring child node (in case ARM TF-A is running). Signed-off-by: NHoria Geantă <horia.geanta@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Frieder Schrempf 提交于
After switching to the new FSL QSPI driver the properties 'fsl,qspi-has-second-chip' and 'big-endian' are not used anymore. The driver now uses the 'reg' property to determine the bus and the chipselect. The endianness is selected by the driver depending on which SoC is used. Signed-off-by: NFrieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Angus Ainslie (Purism) 提交于
Add the imx8mq TMU (Thermal management unit) nodes for CPU, GPU, and VPU. Signed-off-by: NAngus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 21 3月, 2019 2 次提交
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由 Peng Fan 提交于
Add lsio_mu2 node which could be used communicate with SCU. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NDong Aisheng <aisheng.dong@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Peng Fan 提交于
Currently lsio_mu1 is used by Linux Kernel with mbox-cells as 2, but actually mu0-4 could be used to communicate with SCU. So fix the mbox-cells. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NDong Aisheng <aisheng.dong@nxp.com> Fixes: 3d91ba65 ("arm64: dts: imx: add imx8qxp support") Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 20 3月, 2019 5 次提交
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由 Manivannan Sadhasivam 提交于
Enable PCI-E controller for Oxalis board based on NXP/Freescale LS1012a SoC available as the Mini PCI-E connector on the bottom side. Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Alison Wang 提交于
This patch adds pmu dt nodes for LS1028A. Signed-off-by: NAlison Wang <alison.wang@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Daniel Baluta 提交于
The main Audio DAC used on the EVK board is wm8524 The EVK provides the MCLK to wm8524. Digital interface is SAI2 which includes three signals: SYNC_CLK, BCLK and DACDAT. This patch sets: * SAI2 pinctrl configuration * clock hierarchy * wm8524 codec Then uses simple-card machine driver to connect them into a sound card. Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Daniel Baluta 提交于
SAI2 is part of AIPS-3 memory region. Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Daniel Baluta 提交于
SDMA1 is part of AIPS-3 region and SDMA2 is part of AIPS-1 region. Signed-off-by: NAnson Huang <Anson.Huang@nxp.com> Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 19 3月, 2019 7 次提交
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由 Anson Huang 提交于
i.MX8MQ has clock gate for each GPIO bank, add clock info to GPIO node for clock management. Signed-off-by: NAnson Huang <Anson.Huang@nxp.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Abel Vesa 提交于
Add the 0.8GHz and 1GHz opps. According to the datasheet: https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf section 3.1.3 Operating ranges. The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V. The 1GHz runs in overdrive mode with the regulator set to 1V. Signed-off-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Abel Vesa 提交于
According to the schematics, this is a MP2147 switch converter which is controlled by GPIO1_IO13. When set the gpio is set to high the regulator output is set to 0.9V. When the gpio is set to low the regulator output is set to 1V. Signed-off-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Abel Vesa 提交于
The clocks and their latencies will be used by cpufreq-dt. Signed-off-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Alison Wang 提交于
This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards. Signed-off-by: NAlison Wang <alison.wang@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Carlo Caione 提交于
Add the node for the OTP controller. Signed-off-by: NCarlo Caione <ccaione@baylibre.com> Reviewed-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Anson Huang 提交于
Add i.MX8QXP CPU opp table to support cpufreq. Signed-off-by: NAnson Huang <Anson.Huang@nxp.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 02 3月, 2019 2 次提交
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由 Claudiu Manoil 提交于
The LS1028A RDB board features an Atheros PHY connected over SGMII to the ENETC PF0 (or Port0). ENETC Port1 (PF1) has no external connection on this board, so it can be disabled for now. Signed-off-by: NAlex Marginean <alexandru.marginean@nxp.com> Signed-off-by: NClaudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Claudiu Manoil 提交于
The LS1028A SoC features a PCI Integrated Endpoint Root Complex (IERC) defining several integrated PCI devices, including the ENETC ethernet controller integrated endpoints (IEPs). The IERC implements ECAM (Enhanced Configuration Access Mechanism) to provide access to the PCIe config space of the IEPs. This means the the IEPs (including ENETC) do not support the standard PCIe BARs, instead the Enhanced Allocation (EA) capability structures in the ECAM space are used to fix the base addresses in the system, and the PCI subsystem uses these structures for device enumeration and discovery. The "ranges" entries contain basic information from these EA capabily structures required by the kernel for device enumeration. The current patch also enables the first 2 ENETC PFs (Physiscal Functions) and the associated VFs (Virtual Functions), 2 VFs for each PF. Each of these ENETC PFs has an external ethernet port on the LS1028A SoC. Signed-off-by: NAlex Marginean <alexandru.marginean@nxp.com> Signed-off-by: NClaudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 27 2月, 2019 2 次提交
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由 Brian Norris 提交于
Currently, we don't coordinate BT USB activity with our handling of the BT out-of-band wake pin, and instead just use gpio-keys. That causes problems because we have no way of distinguishing wake activity due to a BT device (e.g., mouse) vs. the BT controller (e.g., re-configuring wake mask before suspend). This can cause spurious wake events just because we, for instance, try to reconfigure the host controller's event mask before suspending. We can avoid these synchronization problems by handling the BT wake pin directly in the btusb driver -- for all activity up until BT controller suspend(), we simply listen to normal USB activity (e.g., to know the difference between device and host activity); once we're really ready to suspend the host controller, there should be no more host activity, and only *then* do we unmask the GPIO interrupt. This is already supported by btusb; we just need to describe the wake pin in the right node. We list 2 compatible properties, since both PID/VID pairs show up on Scarlet devices, and they're both essentially identical QCA6174A-based modules. Also note that the polarity was wrong before: Qualcomm implemented WAKE as active high, not active low. We only got away with this because gpio-keys always reconfigured us as bi-directional edge-triggered. Finally, we have an external pull-up and a level-shifter on this line (we didn't notice Qualcomm's polarity in the initial design), so we can't do pull-down. Switch to pull-none. Signed-off-by: NBrian Norris <briannorris@chromium.org> Reviewed-by: NMatthias Kaehlcke <mka@chromium.org> Signed-off-by: NMarcel Holtmann <marcel@holtmann.org>
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由 Marc Gonzalez 提交于
My console locks up as soon as Linux writes to [88800000,88f00000[ AFAIU, that memory area is reserved for trustzone. Extend TZ reserved memory range, to prevent Linux from stepping on trustzone's toes. Cc: stable@vger.kernel.org # 4.20+ Reviewed-by: NSibi Sankar <sibis@codeaurora.org> Fixes: c7833949 ("arm64: dts: qcom: msm8998: Add smem related nodes") Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 22 2月, 2019 1 次提交
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由 Sameer Pujar 提交于
"nvidia,model" property is added to pass custom name for hda sound card. This is parsed in hda driver and used for card name. This aligns with the way with which sound cards are named in general. This patch populates above for jetson-tx1, jetson-tx2 and jetson-xavier. Signed-off-by: NSameer Pujar <spujar@nvidia.com> Reviewed-by: NJonathan Hunter <jonathanh@nvidia.com> Signed-off-by: NTakashi Iwai <tiwai@suse.de>
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- 21 2月, 2019 1 次提交
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由 Xiaowei Bao 提交于
Add the PCIE EP node in dts for ls1046a. Signed-off-by: NXiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: NMinghuan Lian <minghuan.lian@nxp.com> Reviewed-by: NZhiqiang Hou <zhiqiang.hou@nxp.com> Reviewed-by: NRob Herring <robh+dt@kernel.org>
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- 19 2月, 2019 1 次提交
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由 Baruch Siach 提交于
The PHY reset signal goes to mpp43 on CP0. Fixes: babc5544 ("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal") Reported-by: NDenis Odintsov <oversun@me.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>
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- 18 2月, 2019 6 次提交
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由 Baolin Wang 提交于
Remove wildcard compatible string. Signed-off-by: NBaolin Wang <baolin.wang@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Baolin Wang 提交于
Add Spreadtrum SC27XX fuel gauge device node to calculate the battery capacity. Signed-off-by: NBaolin Wang <baolin.wang@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Baolin Wang 提交于
Add charger device node and related battery node for SC2731 PMIC. Signed-off-by: NBaolin Wang <baolin.wang@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Baolin Wang 提交于
This patch adds phandles to the calibration cells provided by the Efuse device, which is used to calibrate the ADC channel scales. Signed-off-by: NBaolin Wang <baolin.wang@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Baolin Wang 提交于
The Spreadtrum PMIC INTC controller has no registers to set trigger type, since it is always high level trigger as default. So remove its child devices' irq trigger type setting and change #interrupt-cells to 1. Signed-off-by: NBaolin Wang <baolin.wang@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Ezequiel Garcia 提交于
Enable the thermal sensor. This device also provides temperature shutdown protection. The shutdown value is set at 110C, as tested by the vendor. Signed-off-by: NEzequiel Garcia <ezequiel@collabora.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 16 2月, 2019 2 次提交
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由 Parthiban Nallathambi 提交于
Add pinctrl definitions for Actions Semiconductor S700 I2C controllers. Pinctrl definitions are only available for I2C0, I2C1 and I2C2. Enable I2C0 (PMIC), I2C1 (gyro, touchscreen) in cubieboard7. Signed-off-by: NParthiban Nallathambi <pn@denx.de> Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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由 Parthiban Nallathambi 提交于
Add I2C controller nodes for Actions Semiconductor S700 SoC. Signed-off-by: NParthiban Nallathambi <pn@denx.de> Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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