提交 7be494dd 编写于 作者: A Anson Huang 提交者: Shawn Guo

arm64: dts: imx8qxp: add cpu opp table

Add i.MX8QXP CPU opp table to support cpufreq.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>
上级 9e98c678
无相关合并请求
......@@ -34,6 +34,9 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_1: cpu@1 {
......@@ -42,6 +45,9 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_2: cpu@2 {
......@@ -50,6 +56,9 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_3: cpu@3 {
......@@ -58,6 +67,9 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_L2: l2-cache0 {
......@@ -65,6 +77,24 @@
};
};
a35_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册