The public Meson8b (S805) datasheet describes a memory region called "A9
Periph base" which starts at 0xC4300000 and ends at 0xC430FFFF. Add a
simple-bus node and move all peripherals that are part of this memory
region.
This makes the .dts a bit easier to read. No functional changes.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The Meson Timer IP block has two clock inputs:
- clk81 for using the system clock as timebase
- xtal for a timebase with 1us, 10us, 100us and 1ms resolution

The clocksource driver does not use these yet, but it's still a good
idea to add them as this describes how the hardware actually works
internally.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

On Amlogic chipsets, the bias set through pinconf applies to the pad
itself, not only the GPIO function. This means that even when we change
the function of the pad from GPIO to anything else, the bias previously
set still applies.

As we have seen with the eMMC, depending on the bias type and the function,
it may trigger problems.

The underlying issue is that we inherit whatever was left by previous user
of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual
setup we will get is undefined.

There is nothing mentioned in the documentation about pad bias and pinmux
function, however leaving it undefined is not an option.

This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Acked-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Some boards use an RMII Ethernet PHY which requires fewer pins than the
RGMII PHYs. Add a separate eth_rmii_pins node which does not include the
pins which are only required for RGMII (but not for RMII) PHYs.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

These are used for example on the Endless Mini (EC-100):
- I2C_A is connected to the Realtek RT5640 audio codec
- PWM_C (GPIODV_9) is connected to a PWM regulator which is used for
  VCCK (CPU voltage supply)
- UART_B is connected to the Bluetooth module (of the RTL8723BS SDIO
  wifi and Bluetooth combo chip)
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The clock controller registers are not 0x460 wide because the reset
controller starts at CBUS 0x4404. This currently overlaps with the
clock controller (which is at CBUS 0x4000).

There is no public documentation available on the actual size of the
clock controller's register area (also called "HHI"). However, in
Amlogic's GPL kernel sources the last "HHI" register is
HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size
doesn't seem unlikely.

Fixes: 4a69fcd3 ("ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boards")
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The Odroid-C1 comes with an IR receiver. It is connected to the GPIOAO_7
pin and thus using the SoC's internal IR decoder.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Enable the performance monitor unit on Meson8b.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Update the "gpio-ranges" property of the CBUS GPIO controller on Meson8b
because it only provides 83 GPIOs.
The GPIO definitions in include/dt-bindings/gpio/meson8b-gpio.h
inherited all GPIOs from Meson8 until recently. However, Meson8b does
not support all GPIOs which are supported by Meson8 (Meson8b doesn't
have a GPIOZ bank, most of the pins from the GPIODV bank are missing on
Meson8b - just to name a few differences).

The actual number of GPIOs is only 83, instead of 120 from Meson8 plus
the 10 GPIOs from the DIF bank on Meson8b.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NJerome Brunet <jbrunet@baylibre.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The Odroid C1 features a microSD slot. This patch adds the necessary
DT bindings to support it.
Signed-off-by: NLinus Lüssing <linus.luessing@c0d3.blue>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add the I2C clocks so the I2C busses can be used. The clock input is not
device specific (the AO I2C bus uses clk81 as input, while the two I2C
busses in CBUS have a separate "CLKID_I2C" gate, provided by the clock
controller.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Enable S805 (aka Meson8b) ethernet pin multiplexing and
extend the controller description.
The programmable ethernet (PRG_ETHERNET) register address
value (0xc1108108), contained in meson.dtsi, is overridden
according to the value found in S805 SoC manual.
This also required to switch to "amlogic,meson8b-dwmac" compatible
to correctly configure that register.
The two clock sources "clkin0" and "clkin1" are both equals
to MPLL2 because, as reported in bit 9-7 register description,
that is the only Meson8b ethernet clock source.
Signed-off-by: NEmiliano Ingrassia <ingrassia@epigenesys.com>
Tested-by: NLinus Lüssing <linus.luessing@c0d3.blue>
Reviewed-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The reset controller in the Meson8b SoCs also supports level resets.
These use the same defines (from
dt-bindings/reset/amlogic,meson8b-reset.h) as the reset pulses.

The reset-meson driver internally handles the difference if a consumer
requests a reset pulse or a level reset. However, for this to work we
must extend the memory zone of the reset controller.
Suggested-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Switch to the stable UART bindings and add the correct gate clocks
to the non-AO UART nodes.
This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The SAR ADC modules doesn't require The "sana" clock.
Acked-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NXingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Amlogic's vendor kernel prints these PL310 L2 cache controller settings
during boot:
  8 ways, 2048 sets, CACHE_ID 0x4100a0c9,  Cache size: 524288 B
  AUX_CTRL 0x7ec60001, PERFETCH_CTRL 0x75000007, POWER_CTRL  0x00000000
  TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222

Add the "prefetch-data", "prefetch-instr" and "arm,shared-override"
properties to get the same L2 cache controller configuration as the
vendor kernel.
Four differences still remain:
- L310_AUX_CTRL_EARLY_BRESP is enabled by the vendor kernel, however
  this is only supported on Cortex-A9 cores (Meson8b has Cortex-A5 cores
  though)
- L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0
  driver
- bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h
- L310_AUX_CTRL_FULL_LINE_ZERO is enabled by the vendor kernel which is
  also only supported on Cortex-A9 cores
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Meson6, Meson8 and Meson8b use a similar IP block which has access to
512 bytes of efuse data.
During SoC manufacturing some calibration settings for the CVBS
connector and the internal temperature sensor are written to this efuse.
On some boards it additionally stores for example the MAC addresses.

The efuse is enabled on Meson8 and Meson8b but kept disabled on Meson6
since we do not have a clock driver there (which is required to read
data from the efuse).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add gpio interrupt controller node to the meson8b boards
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller
  which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU
  cores
- a range in the SRAM specifically reserved for booting secondary CPU
  cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU
cores.
Signed-off-by: NCarlo Caione <carlo@caione.org>
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NLinus Lüssing <linus.luessing@c0d3.blue>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Meson6, Meson8 and Meson8b are using the same MMC controller IP. This
adds the MMC controller node to meson.dtsi so it can be used by all
SoCs.

The controller itself is a bit special, because it has multiple slots.
Each slot is accessed through a sub-node of the controller. However,
currently the driver for this hardware only supports one slot.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Remove pin offset on the AO controller. meson pinctrl no longer has
this quirk
Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

So far, the stress-ng tool for instance quickly resulted in a silent
freeze of the system with no prior notice on a serial console when
running its filesystem or memory stressor classes.

Even with a panic-on-OOM and reboot-on-panic (vm.panic_on_oom=1,
kernel.panic=10) configured, the system would neither reboot nor
would the OOM killer get any chance to otherwise do its job.

The Amlogic reference source code uses a 2MB PHYS_OFFSET. With these 2MB
reserved via DT, stress-ng was able to run on an Odroid C1+ just fine for
several hours, the OOM killer was able to kill processes again and if
configured would successfully trigger a reboot of the system.

Fixes: 4a69fcd3 ("ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boards")
Signed-off-by: NLinus Lüssing <linus.luessing@c0d3.blue>
Acked-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The SoC type and version information is encoded in different register
blocks.
The SoC type information is part of the "assist" registers.
The misc version information is part of the "bootrom" registers.
On Meson8, Meson8b and Meson8m2 there is additionally information about
the minor version. This information is stored in the "analog top"
registers.

Add the nodes for these register blocks so we can decode the SoC type
and version information.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Meson8b has to define it's own compatible string for the watchdog. This
patch removes the duplicate resource (register region and interrupt)
definition from meson8b.dtsi and simply re-uses these values from
meson.dtsi (as the register offset, size and interrupt are identical).

This is purely cosmetic and does not change any functionality.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

According to the vendor kernel sources these also exist (at the same
address) on Meson6 and Meson8. This can be found by running
$ grep -R "define PWM_PWM_[A-D]" arch/arm/
in the Amlogic GPL kernel tree (arm-src-kernel-2015-01-15-321cfb5a46).
pwm_ef does not seem to exist on older SoCs, so we keep it in
meson8b.dtsi for now.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Until now clk81 was used as gate clock for the ethernet controller on
Meson8 whereas Meson8b did not configure a gate clock at all. Use
CLKID_ETH for both SoCs, which is the real gate clock for the ethernet
controller.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many
other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be
used during SMP boot.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This adds the DWC2 USB controller nodes and the corresponding USB2 PHY
nodes to meson.dtsi (as the same - or at least a very similar) IP block
is used on all SoCs (at the same physical address).
Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the
DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be
initialized by the dwc2 driver.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

All supported Meson SoCs have a random number generator in CBUS.
Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
32-bit random number registers. The existing meson-rng driver only
supports the lower 32-bit - but it still works fine on the older SoCs
apart from this small limitation.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
and Meson8b to allow boards to use it. Some boards use it to connect a
button to it.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This patch extends the L2 cache controller node for the Amlogic Meson8
and Meson8b SoCs with some missing parameters. These are taken from the
Amlogic GPL kernel source.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
[apply the change to Meson8 and Meson8b and updated description]
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Currently only meson6.dtsi and meson8.dtsi inherit the generic
meson.dtsi. However, since the Meson8b platform is basically a slightly
updated version of Meson8 we can safely inherit meson.dtsi. An indicator
for this are the nodes which are identical in meson.dtsi and
meson8b.dtsi (L2, gic, timer, uart_AO, uart_A, uart_B, uart_C).

Additionally this makes the following devices available on Meson8b which
were not avaialble before (however, since all affected drivers support
Meson6, Meson8 and the whole GX series there's no reason to assume that
they are not working):
- i2c_a and i2c_B
- the IR receiver
- SPFIC (SPI flash controller)
- the dwmac ethernet controller

Differences between Meson8 and Meson8b seem to be:
- ARM Cortex-A5 core instead of Cortex-A9 on Meson8
- dwmac on Meson8b supports RGMII
- small pinctrl updates

Inheriting meson.dtsi makes it easier to maintain by removing duplicate
definitions.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Update DTSI file to add the reset controller node.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Tested-by: NKevin Hilman <khilman@baylibre.com>

With this patch we add the watchdog node in the meson8b DTS file.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>

Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add pinctrl node to the DTSI file for meson8 and sub-nodes for some
standard mux configurations.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>