Export sdhci_abort_tuning() function symbols which are used by other SD Host
controller driver modules.
Signed-off-by: NBen Chuang <ben.chuang@genesyslogic.com.tw>
Co-developed-by: NMichael K Johnson <johnsonm@danlj.org>
Signed-off-by: NMichael K Johnson <johnsonm@danlj.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable
setup as part of the internal clock setup as described in 3.2.1 Internal
Clock Setup Sequence of SD Host Controller Simplified Specification
Version 4.20.
Signed-off-by: NBen Chuang <ben.chuang@genesyslogic.com.tw>
Co-developed-by: NMichael K Johnson <johnsonm@danlj.org>
Signed-off-by: NMichael K Johnson <johnsonm@danlj.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

According to section 3.2.1 internal clock setup in SD Host Controller
Simplified Specifications 4.20, the timeout of loop for checking
internal clock stable is defined as 150ms.
Signed-off-by: NBen Chuang <ben.chuang@genesyslogic.com.tw>
Co-developed-by: NMichael K Johnson <johnsonm@danlj.org>
Signed-off-by: NMichael K Johnson <johnsonm@danlj.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The SD host controller specification defines 3 types software reset:
software reset for data line, software reset for command line and software
reset for all. Software reset for all means this reset affects the entire
Host controller except for the card detection circuit.

In sdhci_runtime_resume_host() we always do a software "reset for all",
which causes the Spreadtrum variant controller to work abnormally after
resuming. To fix the problem, let's do a software reset for the data and
the command part, rather than "for all".

However, as sdhci_runtime_resume() is a common sdhci function and we don't
want to change the behaviour for other variants, let's introduce a new
in-parameter for it. This enables the caller to decide if a "reset for all"
shall be done or not.
Signed-off-by: NBaolin Wang <baolin.wang@linaro.org>
Fixes: fb8bd90f ("mmc: sdhci-sprd: Add Spreadtrum's initial host controller")
Cc: stable@vger.kernel.org
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NAllison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Since commit c07a48c2 ("mmc: sdhci: Remove finish_tasklet"), the IRQ
thread might be used to complete requests, but the IRQ thread is also used
to process SDIO card interrupts. This can cause a deadlock when the SDIO
processing tries to access the card since that would also require the IRQ
thread. Change SDHCI to use sdio_signal_irq() to schedule a work item
instead. That also requires implementing the ->ack_sdio_irq() mmc host op.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Fixes: c07a48c2 ("mmc: sdhci: Remove finish_tasklet")
Reported-by: NBrian Masney <masneyb@onstation.org>
Tested-by: NBrian Masney <masneyb@onstation.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Remove finish_tasklet. Requests that require DMA-unmapping or sdhci_reset
are completed either in the IRQ thread or a workqueue if the completion is
not initiated by the IRQ.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Reviewed-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In preparation for removing finish_tasklet, call mmc_request_done() from
the IRQ handler if possible. That will alleviate the potential loss of
performance from shifting away from finish_tasklet.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Reviewed-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In preparation for removing finish_tasklet, move some processing from
sdhci_request_done() to __sdhci_finish_mrq().
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Reviewed-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In preparation for removing finish_tasklet, move some functions.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Reviewed-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In preparation for removing finish_tasklet, reorganize sdhci_finish_mrq()
and __sdhci_finish_mrq() to separate the tasklet scheduling from other
processing.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Reviewed-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

As per the Host Controller Standard Specification Version 4.20,
limitation of tuning iteration count is removed as PLL locking
time can be longer than UHS-1 tuning due to larger PVT fluctuation
and it will result in increase of tuning iteration to complete the
tuning.

This patch creates sdhci_host member tuning_loop_count to allow
hosts to specify maximum tuning iterations and also updates
execute_tuning to use this specified maximum tuning iteration count.

Default tuning_loop_count is set to same as existing loop count of
MAX_TUNING_LOOP which is 40 iterations.
Tested-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

mmiowb() is now implied by spin_unlock() on architectures that require
it, so there is no reason to call it from driver code. This patch was
generated using coccinelle:

	@mmiowb@
	@@
	- mmiowb();

and invoked as:

$ for d in drivers include/linux/qed sound; do \
spatch --include-headers --sp-file mmiowb.cocci --dir $d --in-place; done

NOTE: mmiowb() has only ever guaranteed ordering in conjunction with
spin_unlock(). However, pairing each mmiowb() removal in this patch with
the corresponding call to spin_unlock() is not at all trivial, so there
is a small chance that this change may regress any drivers incorrectly
relying on mmiowb() to order MMIO writes between CPUs using lock-free
synchronisation. If you've ended up bisecting to this commit, you can
reintroduce the mmiowb() calls using wmb() instead, which should restore
the old behaviour on all architectures other than some esoteric ia64
systems.
Acked-by: NLinus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

Even though SDHCI controllers may have a dedicated WP pin that can be
queried using the SDHCI_PRESENT_STATE register, some platforms may
chose to use a separate regular GPIO to route the WP signal. Such a
GPIO is typically represented using the wp-gpios property in the
Device Tree.

Unfortunately, the current sdhci_check_ro() function does not make use
of such GPIO when available: it either uses a host controller specific
->get_ro() operation, or uses the SDHCI_PRESENT_STATE. Several host
controller specific ->get_ro() functions are implemented just to check
a WP GPIO state.

Instead of pushing this to more controller-specific implementations,
let's handle this in the core SDHCI code, just like it is already done
for the CD GPIO in sdhci_get_cd().

The below patch simply changes sdhci_check_ro() to use the value of
the WP GPIO if available.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Below are the supported DMA types in Host Control1 Register
with Version 4 enable
b'00 - SDMA
b'01 - Not Used
b'10 - ADMA2
b'11 - ADMA2 or ADMA3

ADMA3 uses Command Descriptor to issue an SD command.
A multi-block data transfer is performed by using a pair of CMD
descriptor and ADMA2 descriptor.

ADMA3 performs multiple of multi-block data transfer by using
Integrated Descriptor which is more suitable for Command Queuing
to fetch both Command and Transfer descriptors.

Host Capabilities register indicates the supports of ADMA3 DMA.
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Reviewed-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Change to use sdhci_set_timeout() to set the maximum timeout, so that
the host can use it's own set_timeout() callback to set the maximum
timeout if the host has.
Signed-off-by: NHaibo Chen <haibo.chen@nxp.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

When host set the host->tuning_delay, even the last tuning
command need a delay, otherwise the first command after the
tuning will meet issue.

Take i.MX7D as an example, there will be the following log:
  mmc2: switch to high-speed from hs200 failed, err:-110
  mmc2: error -110 whilst initialising MMC card
Signed-off-by: NHaibo Chen <haibo.chen@nxp.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

We already need to zero out memory for dma_alloc_coherent(), as such
using dma_zalloc_coherent() is superflous. Phase it out.

This change was generated with the following Coccinelle SmPL patch:

@ replace_dma_zalloc_coherent @
expression dev, size, data, handle, flags;
@@

-dma_zalloc_coherent(dev, size, handle, flags)
+dma_alloc_coherent(dev, size, handle, flags)
Suggested-by: NChristoph Hellwig <hch@lst.de>
Signed-off-by: NLuis Chamberlain <mcgrof@kernel.org>
[hch: re-ran the script on the latest tree]
Signed-off-by: NChristoph Hellwig <hch@lst.de>

V4_MODE is Bit-15 of SDHCI_HOST_CONTROL2 register.
Need to perform word access to this register.
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Fixes: b3f80b43 ("mmc: sdhci: Add sd host v4 mode")
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Host controllers may not have a LED signal line, whereas the register
updates to control the non-existent LED can be relatively time consuming.
Add a quirk to disable LED control.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

If the host controller supports auto-commands then enable the auto-command
error interrupt and handle it. In the case of auto-CMD23, the error is
treated the same as manual CMD23 error. In the case of auto-CMD12,
commands-during-transfer are not permitted, so the error handling is
treated the same as a data error.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The SDHCI_ACMD12_ERR register is used for auto-CMD23 and auto-CMD12
errors, as is the SDHCI_INT_ACMD12ERR interrupt bit. Rename them to
SDHCI_AUTO_CMD_STATUS and SDHCI_INT_AUTO_CMD_ERR respectively.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Existing data command CRC error handling is non-standard and does not work
with some Intel host controllers. Specifically, the assumption that the host
controller will continue operating normally after the error interrupt,
is not valid. Change the driver to handle the error in the same manner
as a data CRC error, taking care to ensure that the data line reset is
done for single or multi-block transfers, and it is done before
unmapping DMA.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The function sdhci_allocate_bounce_buffer() always return zero at
present, so there's no need to have a return value, that will also make
error path easier.

CC: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

We observed some premature timeouts on a virtualization platform, the log
is like this:

case 1:
[159525.255629] mmc1: Internal clock never stabilised.
[159525.255818] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
[159525.256049] mmc1: sdhci: Sys addr:  0x00000000 | Version:  0x00001002
...
[159525.257205] mmc1: sdhci: Wake-up:   0x00000000 | Clock:    0x0000fa03
From the clock control register dump, we are pretty sure the clock was
stablized.

case 2:
[  914.550127] mmc1: Reset 0x2 never completed.
[  914.550321] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
[  914.550608] mmc1: sdhci: Sys addr:  0x00000010 | Version:  0x00001002

After checking the sdhci code, we found the timeout check actually has a
little window that the CPU can be scheduled out and when it comes back,
the original time set or check is not valid.

Fixes: 5a436cc0 ("mmc: sdhci: Optimize delay loops")
Cc: stable@vger.kernel.org      # v4.12+
Signed-off-by: NAlek Du <alek.du@intel.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

If hosts provides ops->adma_write_desc, we should not fall back to the
general sdhci_adma_write_desc().
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address
register (05Fh-058h) instead of using register (000h-004h) to indicate
its system address of data location. The register (000h-004h) is
re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA
may use Auto CMD23.
Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

As SD Host Controller Specification v4.10 documents:
Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode.
Selection of Auto CMD depends on setting of CMD23 Enable in the Host
Control 2 register which indicates whether card supports CMD23. If CMD23
Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is
used. In case of Version 4.10 or later, use of Auto CMD Auto Select is
recommended rather than use of Auto CMD12 Enable or Auto CMD23
Enable.

This patch add this new mode support.
Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Host Controller Version 4.10 re-defines SDMA System Address register
as 32-bit Block Count for v4 mode, and SDMA uses ADMA System
Address register (05Fh-058h) instead if v4 mode is enabled. Also
when using 32-bit block count, 16-bit block count register need
to be set to zero.

Since using 32-bit Block Count would cause problems for auto-cmd23,
it can be chosen via host->quirk2.
Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

ADMA2 64-bit addressing support is divided into V3 mode and V4 mode.
So there are two kinds of descriptors for ADMA2 64-bit addressing
i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4
mode. 128-bit Descriptor is aligned to 8-byte.

For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2
register.
Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
[Ulf: Fixed conflict while applying]
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

According to the SD host controller specification version 4.10, when
Host Version 4 is enabled, SDMA uses ADMA System Address register
(05Fh-058h) instead of using SDMA System Address register to
support both 32-bit and 64-bit addressing.
Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

For SD host controller version 4.00 or later ones, there're two
modes of implementation - Version 3.00 compatible mode or
Version 4 mode.  This patch introduced an interface to enable
v4 mode.
Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Added definitions for v400, v410, v420.
Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add this hook so that it can be overridden with driver specific
implementations. We also let the original sdhci_adma_write_desc()
accept &desc so that the function can set its new value. Then export
the function so that it could be reused by driver's specific
implementations.
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch adds adma_table_cnt member to struct sdhci_host to give more
flexibility to drivers to control the ADMA table count.

Default value of adma_table_cnt is set to (SDHCI_MAX_SEGS * 2 + 1).
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Allow SDHCI drivers to hook code before and after sdhci_request() by
making it externally visible.
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch is to add tuning error codes to
judge tuning state
Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add hardware tuning function instead of software tuning because O2/Bayhub
SD host controller support hardware tuning.
Signed-off-by: Nernest.zhang <ernest.zhang@bayhubtech.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Export sdhci tuning function symbols which are used by other SD Host
controller driver modules.
Signed-off-by: Nernest.zhang <ernest.zhang@bayhubtech.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

For eMMC devices it is valid to only support 1.8V signaling. When
vqmmc is set to a fixed 1.8V regulator the stack tries to set 3.3V
initially and prints the following warning:
   mmc1: Switching to 3.3V signalling voltage failed

Clear the MMC_SIGNAL_VOLTAGE_330 flag in case 3.3V is signaling is
not available. This prevents the stack from even trying to use
3.3V signaling and avoids the above warning.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>