1. 13 11月, 2012 6 次提交
    • J
      ARM: OMAP: Don't restore DMTIMER interrupt status register · 1eaff710
      Jon Hunter 提交于
      Restoring the timer interrupt status is not possible because writing a 1 to any
      bit in the register clears that bit if set and writing a 0 has no affect.
      Furthermore, if an interrupt is pending when someone attempts to disable a
      timer, the timer will fail to transition to the idle state and hence it's
      context will not be lost. Users should take care to service all interrupts
      before disabling the timer.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      1eaff710
    • J
      ARM: OMAP: Don't restore of DMTIMER TISTAT register · d3004bb4
      Jon Hunter 提交于
      The timer TISTAT register is a read-only register and therefore restoring the
      context is not needed. Furthermore, the context of TISTAT is never saved
      anywhere in the current code. The TISTAT register is read-only for all OMAP
      devices from OMAP1 to OMAP4. OMAP5 timers no longer have this register.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      d3004bb4
    • J
      ARM: OMAP: Fix dmtimer reset for timer1 · ffc957bd
      Jon Hunter 提交于
      In commit e32f7ec2 (ARM: OMAP: Fix 32 kHz timer and modify GP timer to use GPT1)
      a fix was added to prevent timer1 being reset in the function
      omap_dm_timer_reset() because timer1 was being used as the system timer for
      OMAP2 devices. Although timer1 is still used by most OMAP2+ devices as a system
      timer, the function omap_dm_timer_reset() is now only being called for OMAP1
      devices and OMAP1 does not use timer1 as a system timer. Therefore, remove the
      check in omap_dm_timer_reset() so that timer1 is reset for OMAP1 devices.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      ffc957bd
    • J
      ARM: OMAP: Fix timer posted mode support · 7b44cf2c
      Jon Hunter 提交于
      Currently the dmtimer posted mode is being enabled when the function
      omap_dm_timer_enable_posted() is called. This function is only being called
      for OMAP1 timers and OMAP2+ timers that are being used as system timers. Hence,
      for OMAP2+ timers that are NOT being used as a system timer, posted mode is
      not enabled but the "timer->posted" variable is still set (incorrectly) in
      the omap_dm_timer_prepare() function.
      
      This is a regression introduced by commit 3392cdd3 (ARM: OMAP: dmtimer:
      switch-over to platform device driver) which was before the
      omap_dm_timer_enable_posted() function was introduced. Although this is a
      regression from the original code it only impacts performance and so is not
      needed for stable.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      7b44cf2c
    • J
      ARM: OMAP3+: Implement timer workaround for errata i103 and i767 · bfd6d021
      Jon Hunter 提交于
      Errata Titles:
      i103: Delay needed to read some GP timer, WD timer and sync timer
            registers after wakeup (OMAP3/4)
      i767: Delay needed to read some GP timer registers after wakeup (OMAP5)
      
      Description (i103/i767):
      If a General Purpose Timer (GPTimer) is in posted mode
      (TSICR [2].POSTED=1), due to internal resynchronizations, values read in
      TCRR, TCAR1 and TCAR2 registers right after the timer interface clock
      (L4) goes from stopped to active may not return the expected values. The
      most common event leading to this situation occurs upon wake up from
      idle.
      
      GPTimer non-posted synchronization mode is not impacted by this
      limitation.
      
      Workarounds:
      1). Disable posted mode
      2). Use static dependency between timer clock domain and MPUSS clock
          domain
      3). Use no-idle mode when the timer is active
      
      Workarounds #2 and #3 are not pratical from a power standpoint and so
      workaround #1 has been implemented. Disabling posted mode adds some CPU
      overhead for configuring and reading the timers as the CPU has to wait
      for accesses to be re-synchronised within the timer. However, disabling
      posted mode guarantees correct operation.
      
      Please note that it is safe to use posted mode for timers if the counter
      (TCRR) and capture (TCARx) registers will never be read. An example of
      this is the clock-event system timer. This is used by the kernel to
      schedule events however, the timers counter is never read and capture
      registers are not used. Given that the kernel configures this timer
      often yet never reads the counter register it is safe to enable posted
      mode in this case. Hence, for the timer used for kernel clock-events,
      posted mode is enabled by overriding the errata for devices that are
      impacted by this defect.
      
      For drivers using the timers that do not read the counter or capture
      registers and wish to use posted mode, can override the errata and
      enable posted mode by making the following function calls.
      
      	__omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767);
      	__omap_dm_timer_enable_posted(timer);
      
      Both dmtimers and watchdogs are impacted by this defect this patch only
      implements the workaround for the dmtimer. Currently the watchdog driver
      does not read the counter register and so no workaround is necessary.
      
      Posted mode will be disabled for all OMAP2+ devices (including AM33xx)
      using a GP timer as a clock-source timer to guarantee correct operation.
      This is not necessary for OMAP24xx devices but the default clock-source
      timer for OMAP24xx devices is the 32k-sync timer and not the GP timer
      and so should not have any impact. This should be re-visited for future
      devices if this errata is fixed.
      
      Confirmed with Vaibhav Hiremath that this bug also impacts AM33xx
      devices.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      bfd6d021
    • J
      ARM: OMAP: Add DMTIMER definitions for posted mode · 971d0254
      Jon Hunter 提交于
      For OMAP2+ devices, when using DMTIMERs for system timers (clock-events and
      clock-source) the posted mode configuration of the timers is used. To allow
      the compiler to optimise the functions for configuring and reading the system
      timers, the posted flag variable is hard-coded with the value 1. To make it
      clear that posted mode is being used add some definitions so that it is more
      readable.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      971d0254
  2. 07 11月, 2012 1 次提交
  3. 03 11月, 2012 3 次提交
    • T
      ARM: OMAP: Remove unnecessary mach and plat includes · 7136f8d8
      Tony Lindgren 提交于
      Now mach/hardware.h is empty for omap2+ and can be
      removed except for plat-omap/dmtimer.c for omap1.
      
      Also the include of mach/irqs.h can now be removed
      for shared plat-omap/i2c.c as it's no longer needed.
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      7136f8d8
    • J
      ARM: OMAP: Add DT support for timer driver · 9725f445
      Jon Hunter 提交于
      In order to add device-tree support to the timer driver the following changes
      were made ...
      
      1. Allocate system timers (used for clock-events and clock-source) based upon
         timer properties rather than using an hard-coded timer instance ID. To allow
         this a new helper function called omap_dmtimer_find_by_property() has been
         added for finding a timer with the particular properties in the device-tree
         blob. Please note that this is an internal helper function for system timers
         only to find a timer in the device-tree blob. This cannot be used by device
         drivers, another API has been added for that (see below). Timers that are
         allocated for system timers are dynamically disabled at boot time by adding
         a status property with the value "disabled" to the timer's device-tree node.
      
         Please note that when allocating system timers we now pass a timer ID and
         timer property. The timer ID is only be used for allocating a timer when
         booting without device-tree. Once device-tree migration is complete, all
         the timer ID references will be removed.
      
      2. System timer resources (memory and interrupts) are directly obtained from
         the device-tree timer node when booting with device-tree, so that system
         timers are no longer reliant upon the OMAP HWMOD framework to provide these
         resources.
      
      3. If DT blob is present, then let device-tree create the timer devices
         dynamically.
      
      4. When device-tree is present the "id" field in the platform_device structure
         (pdev->id) is initialised to -1 and hence cannot be used to identify a timer
         instance. Due to this the following changes were made ...
         a). The API omap_dm_timer_request_specific() is not supported when using
             device-tree, because it uses the device ID to request a specific timer.
             This function will return an error if called when device-tree is present.
             Users of this API should use omap_dm_timer_request_by_cap() instead.
         b). When removing the DMTIMER driver, the timer "id" was used to identify the
             timer instance. The remove function has been modified to use the device
             name instead of the "id".
      
      5. When device-tree is present the platform_data structure will be NULL and so
         check for this.
      
      6. The OMAP timer device tree binding has the following optional parameters ...
         a). ti,timer-alwon  --> Timer is in an always-on power domain
         b). ti,timer-dsp    --> Timer can generate an interrupt to the on-chip DSP
         c). ti,timer-pwm    --> Timer can generate a PWM output
         d). ti,timer-secure --> Timer is reserved on a secure OMAP device
         Search for the above parameters and set the appropriate timer attribute
         flags.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      9725f445
    • J
      ARM: OMAP: Add function to request a timer by capability · 373fe0bd
      Jon Hunter 提交于
      Currently OMAP timers can be requested by requesting any available or by a
      numerical device ID. If a specific timer is required because it has a particular
      capability, such as can interrupt the on-chip DSP in addition to the ARM CPU,
      then the user needs to know the device ID of the timer with this feature.
      Therefore, add a new API called omap_dm_timer_request_by_cap() that allows
      drivers to request a timer by capability.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      373fe0bd
  4. 01 11月, 2012 12 次提交
  5. 25 10月, 2012 6 次提交
  6. 23 10月, 2012 1 次提交
  7. 19 10月, 2012 9 次提交
  8. 18 10月, 2012 2 次提交